i2c_regs.h

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/**
 * @file
 * @brief Generated register defines for i2c
 */
 
// Copyright information found in source file:
// Copyright lowRISC contributors (OpenTitan project).
 
// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#ifndef _I2C_REG_DEFS_
#define _I2C_REG_DEFS_
 
#ifdef __cplusplus
extern "C" {
#endif
// Depth of FMT, RX, and TX FIFOs.
#define I2C_PARAM_FIFO_DEPTH 64
 
// Depth of ACQ FIFO.
#define I2C_PARAM_ACQ_FIFO_DEPTH 268
 
// Number of alerts
#define I2C_PARAM_NUM_ALERTS 1
 
// Register width
#define I2C_PARAM_REG_WIDTH 32
 
// Common Interrupt Offsets
#define I2C_INTR_COMMON_FMT_THRESHOLD_BIT 0
#define I2C_INTR_COMMON_RX_THRESHOLD_BIT 1
#define I2C_INTR_COMMON_ACQ_THRESHOLD_BIT 2
#define I2C_INTR_COMMON_RX_OVERFLOW_BIT 3
#define I2C_INTR_COMMON_CONTROLLER_HALT_BIT 4
#define I2C_INTR_COMMON_SCL_INTERFERENCE_BIT 5
#define I2C_INTR_COMMON_SDA_INTERFERENCE_BIT 6
#define I2C_INTR_COMMON_STRETCH_TIMEOUT_BIT 7
#define I2C_INTR_COMMON_SDA_UNSTABLE_BIT 8
#define I2C_INTR_COMMON_CMD_COMPLETE_BIT 9
#define I2C_INTR_COMMON_TX_STRETCH_BIT 10
#define I2C_INTR_COMMON_TX_THRESHOLD_BIT 11
#define I2C_INTR_COMMON_ACQ_STRETCH_BIT 12
#define I2C_INTR_COMMON_UNEXP_STOP_BIT 13
#define I2C_INTR_COMMON_HOST_TIMEOUT_BIT 14
 
// Interrupt State Register
#define I2C_INTR_STATE_REG_OFFSET 0x0
#define I2C_INTR_STATE_REG_RESVAL 0x0u
#define I2C_INTR_STATE_FMT_THRESHOLD_BIT 0
#define I2C_INTR_STATE_RX_THRESHOLD_BIT 1
#define I2C_INTR_STATE_ACQ_THRESHOLD_BIT 2
#define I2C_INTR_STATE_RX_OVERFLOW_BIT 3
#define I2C_INTR_STATE_CONTROLLER_HALT_BIT 4
#define I2C_INTR_STATE_SCL_INTERFERENCE_BIT 5
#define I2C_INTR_STATE_SDA_INTERFERENCE_BIT 6
#define I2C_INTR_STATE_STRETCH_TIMEOUT_BIT 7
#define I2C_INTR_STATE_SDA_UNSTABLE_BIT 8
#define I2C_INTR_STATE_CMD_COMPLETE_BIT 9
#define I2C_INTR_STATE_TX_STRETCH_BIT 10
#define I2C_INTR_STATE_TX_THRESHOLD_BIT 11
#define I2C_INTR_STATE_ACQ_STRETCH_BIT 12
#define I2C_INTR_STATE_UNEXP_STOP_BIT 13
#define I2C_INTR_STATE_HOST_TIMEOUT_BIT 14
 
// Interrupt Enable Register
#define I2C_INTR_ENABLE_REG_OFFSET 0x4
#define I2C_INTR_ENABLE_REG_RESVAL 0x0u
#define I2C_INTR_ENABLE_FMT_THRESHOLD_BIT 0
#define I2C_INTR_ENABLE_RX_THRESHOLD_BIT 1
#define I2C_INTR_ENABLE_ACQ_THRESHOLD_BIT 2
#define I2C_INTR_ENABLE_RX_OVERFLOW_BIT 3
#define I2C_INTR_ENABLE_CONTROLLER_HALT_BIT 4
#define I2C_INTR_ENABLE_SCL_INTERFERENCE_BIT 5
#define I2C_INTR_ENABLE_SDA_INTERFERENCE_BIT 6
#define I2C_INTR_ENABLE_STRETCH_TIMEOUT_BIT 7
#define I2C_INTR_ENABLE_SDA_UNSTABLE_BIT 8
#define I2C_INTR_ENABLE_CMD_COMPLETE_BIT 9
#define I2C_INTR_ENABLE_TX_STRETCH_BIT 10
#define I2C_INTR_ENABLE_TX_THRESHOLD_BIT 11
#define I2C_INTR_ENABLE_ACQ_STRETCH_BIT 12
#define I2C_INTR_ENABLE_UNEXP_STOP_BIT 13
#define I2C_INTR_ENABLE_HOST_TIMEOUT_BIT 14
 
// Interrupt Test Register
#define I2C_INTR_TEST_REG_OFFSET 0x8
#define I2C_INTR_TEST_REG_RESVAL 0x0u
#define I2C_INTR_TEST_FMT_THRESHOLD_BIT 0
#define I2C_INTR_TEST_RX_THRESHOLD_BIT 1
#define I2C_INTR_TEST_ACQ_THRESHOLD_BIT 2
#define I2C_INTR_TEST_RX_OVERFLOW_BIT 3
#define I2C_INTR_TEST_CONTROLLER_HALT_BIT 4
#define I2C_INTR_TEST_SCL_INTERFERENCE_BIT 5
#define I2C_INTR_TEST_SDA_INTERFERENCE_BIT 6
#define I2C_INTR_TEST_STRETCH_TIMEOUT_BIT 7
#define I2C_INTR_TEST_SDA_UNSTABLE_BIT 8
#define I2C_INTR_TEST_CMD_COMPLETE_BIT 9
#define I2C_INTR_TEST_TX_STRETCH_BIT 10
#define I2C_INTR_TEST_TX_THRESHOLD_BIT 11
#define I2C_INTR_TEST_ACQ_STRETCH_BIT 12
#define I2C_INTR_TEST_UNEXP_STOP_BIT 13
#define I2C_INTR_TEST_HOST_TIMEOUT_BIT 14
 
// Alert Test Register
#define I2C_ALERT_TEST_REG_OFFSET 0xc
#define I2C_ALERT_TEST_REG_RESVAL 0x80000000u
#define I2C_ALERT_TEST_FATAL_FAULT_BIT 0
#define I2C_ALERT_TEST_REGWEN_BIT 31
 
// I2C Control Register
#define I2C_CTRL_REG_OFFSET 0x10
#define I2C_CTRL_REG_RESVAL 0x0u
#define I2C_CTRL_ENABLEHOST_BIT 0
#define I2C_CTRL_ENABLETARGET_BIT 1
#define I2C_CTRL_LLPBK_BIT 2
#define I2C_CTRL_NACK_ADDR_AFTER_TIMEOUT_BIT 3
#define I2C_CTRL_ACK_CTRL_EN_BIT 4
#define I2C_CTRL_MULTI_CONTROLLER_MONITOR_EN_BIT 5
#define I2C_CTRL_TX_STRETCH_CTRL_EN_BIT 6
 
// I2C Live Status Register for Host and Target modes
#define I2C_STATUS_REG_OFFSET 0x14
#define I2C_STATUS_REG_RESVAL 0x33cu
#define I2C_STATUS_FMTFULL_BIT 0
#define I2C_STATUS_RXFULL_BIT 1
#define I2C_STATUS_FMTEMPTY_BIT 2
#define I2C_STATUS_HOSTIDLE_BIT 3
#define I2C_STATUS_TARGETIDLE_BIT 4
#define I2C_STATUS_RXEMPTY_BIT 5
#define I2C_STATUS_TXFULL_BIT 6
#define I2C_STATUS_ACQFULL_BIT 7
#define I2C_STATUS_TXEMPTY_BIT 8
#define I2C_STATUS_ACQEMPTY_BIT 9
#define I2C_STATUS_ACK_CTRL_STRETCH_BIT 10
 
// I2C Read Data
#define I2C_RDATA_REG_OFFSET 0x18
#define I2C_RDATA_REG_RESVAL 0x0u
#define I2C_RDATA_RDATA_MASK 0xffu
#define I2C_RDATA_RDATA_OFFSET 0
#define I2C_RDATA_RDATA_FIELD \
  ((bitfield_field32_t) { .mask = I2C_RDATA_RDATA_MASK, .index = I2C_RDATA_RDATA_OFFSET })
 
// I2C Host Format Data
#define I2C_FDATA_REG_OFFSET 0x1c
#define I2C_FDATA_REG_RESVAL 0x0u
#define I2C_FDATA_FBYTE_MASK 0xffu
#define I2C_FDATA_FBYTE_OFFSET 0
#define I2C_FDATA_FBYTE_FIELD \
  ((bitfield_field32_t) { .mask = I2C_FDATA_FBYTE_MASK, .index = I2C_FDATA_FBYTE_OFFSET })
#define I2C_FDATA_START_BIT 8
#define I2C_FDATA_STOP_BIT 9
#define I2C_FDATA_READB_BIT 10
#define I2C_FDATA_RCONT_BIT 11
#define I2C_FDATA_NAKOK_BIT 12
 
// I2C FIFO control register
#define I2C_FIFO_CTRL_REG_OFFSET 0x20
#define I2C_FIFO_CTRL_REG_RESVAL 0x0u
#define I2C_FIFO_CTRL_RXRST_BIT 0
#define I2C_FIFO_CTRL_FMTRST_BIT 1
#define I2C_FIFO_CTRL_ACQRST_BIT 7
#define I2C_FIFO_CTRL_TXRST_BIT 8
 
// Host mode FIFO configuration
#define I2C_HOST_FIFO_CONFIG_REG_OFFSET 0x24
#define I2C_HOST_FIFO_CONFIG_REG_RESVAL 0x0u
#define I2C_HOST_FIFO_CONFIG_RX_THRESH_MASK 0xfffu
#define I2C_HOST_FIFO_CONFIG_RX_THRESH_OFFSET 0
#define I2C_HOST_FIFO_CONFIG_RX_THRESH_FIELD \
  ((bitfield_field32_t) { .mask = I2C_HOST_FIFO_CONFIG_RX_THRESH_MASK, .index = I2C_HOST_FIFO_CONFIG_RX_THRESH_OFFSET })
#define I2C_HOST_FIFO_CONFIG_FMT_THRESH_MASK 0xfffu
#define I2C_HOST_FIFO_CONFIG_FMT_THRESH_OFFSET 16
#define I2C_HOST_FIFO_CONFIG_FMT_THRESH_FIELD \
  ((bitfield_field32_t) { .mask = I2C_HOST_FIFO_CONFIG_FMT_THRESH_MASK, .index = I2C_HOST_FIFO_CONFIG_FMT_THRESH_OFFSET })
 
// Target mode FIFO configuration
#define I2C_TARGET_FIFO_CONFIG_REG_OFFSET 0x28
#define I2C_TARGET_FIFO_CONFIG_REG_RESVAL 0x0u
#define I2C_TARGET_FIFO_CONFIG_TX_THRESH_MASK 0xfffu
#define I2C_TARGET_FIFO_CONFIG_TX_THRESH_OFFSET 0
#define I2C_TARGET_FIFO_CONFIG_TX_THRESH_FIELD \
  ((bitfield_field32_t) { .mask = I2C_TARGET_FIFO_CONFIG_TX_THRESH_MASK, .index = I2C_TARGET_FIFO_CONFIG_TX_THRESH_OFFSET })
#define I2C_TARGET_FIFO_CONFIG_ACQ_THRESH_MASK 0xfffu
#define I2C_TARGET_FIFO_CONFIG_ACQ_THRESH_OFFSET 16
#define I2C_TARGET_FIFO_CONFIG_ACQ_THRESH_FIELD \
  ((bitfield_field32_t) { .mask = I2C_TARGET_FIFO_CONFIG_ACQ_THRESH_MASK, .index = I2C_TARGET_FIFO_CONFIG_ACQ_THRESH_OFFSET })
 
// Host mode FIFO status register
#define I2C_HOST_FIFO_STATUS_REG_OFFSET 0x2c
#define I2C_HOST_FIFO_STATUS_REG_RESVAL 0x0u
#define I2C_HOST_FIFO_STATUS_FMTLVL_MASK 0xfffu
#define I2C_HOST_FIFO_STATUS_FMTLVL_OFFSET 0
#define I2C_HOST_FIFO_STATUS_FMTLVL_FIELD \
  ((bitfield_field32_t) { .mask = I2C_HOST_FIFO_STATUS_FMTLVL_MASK, .index = I2C_HOST_FIFO_STATUS_FMTLVL_OFFSET })
#define I2C_HOST_FIFO_STATUS_RXLVL_MASK 0xfffu
#define I2C_HOST_FIFO_STATUS_RXLVL_OFFSET 16
#define I2C_HOST_FIFO_STATUS_RXLVL_FIELD \
  ((bitfield_field32_t) { .mask = I2C_HOST_FIFO_STATUS_RXLVL_MASK, .index = I2C_HOST_FIFO_STATUS_RXLVL_OFFSET })
 
// Target mode FIFO status register
#define I2C_TARGET_FIFO_STATUS_REG_OFFSET 0x30
#define I2C_TARGET_FIFO_STATUS_REG_RESVAL 0x0u
#define I2C_TARGET_FIFO_STATUS_TXLVL_MASK 0xfffu
#define I2C_TARGET_FIFO_STATUS_TXLVL_OFFSET 0
#define I2C_TARGET_FIFO_STATUS_TXLVL_FIELD \
  ((bitfield_field32_t) { .mask = I2C_TARGET_FIFO_STATUS_TXLVL_MASK, .index = I2C_TARGET_FIFO_STATUS_TXLVL_OFFSET })
#define I2C_TARGET_FIFO_STATUS_ACQLVL_MASK 0xfffu
#define I2C_TARGET_FIFO_STATUS_ACQLVL_OFFSET 16
#define I2C_TARGET_FIFO_STATUS_ACQLVL_FIELD \
  ((bitfield_field32_t) { .mask = I2C_TARGET_FIFO_STATUS_ACQLVL_MASK, .index = I2C_TARGET_FIFO_STATUS_ACQLVL_OFFSET })
 
// I2C Override Control Register
#define I2C_OVRD_REG_OFFSET 0x34
#define I2C_OVRD_REG_RESVAL 0x0u
#define I2C_OVRD_TXOVRDEN_BIT 0
#define I2C_OVRD_SCLVAL_BIT 1
#define I2C_OVRD_SDAVAL_BIT 2
 
// Oversampled RX values
#define I2C_VAL_REG_OFFSET 0x38
#define I2C_VAL_REG_RESVAL 0x0u
#define I2C_VAL_SCL_RX_MASK 0xffffu
#define I2C_VAL_SCL_RX_OFFSET 0
#define I2C_VAL_SCL_RX_FIELD \
  ((bitfield_field32_t) { .mask = I2C_VAL_SCL_RX_MASK, .index = I2C_VAL_SCL_RX_OFFSET })
#define I2C_VAL_SDA_RX_MASK 0xffffu
#define I2C_VAL_SDA_RX_OFFSET 16
#define I2C_VAL_SDA_RX_FIELD \
  ((bitfield_field32_t) { .mask = I2C_VAL_SDA_RX_MASK, .index = I2C_VAL_SDA_RX_OFFSET })
 
// Detailed I2C Timings (directly corresponding to table 10 in the
// I<sup>2</sup>C Specification (rev. 6)).
#define I2C_TIMING0_REG_OFFSET 0x3c
#define I2C_TIMING0_REG_RESVAL 0x0u
#define I2C_TIMING0_THIGH_MASK 0x1fffu
#define I2C_TIMING0_THIGH_OFFSET 0
#define I2C_TIMING0_THIGH_FIELD \
  ((bitfield_field32_t) { .mask = I2C_TIMING0_THIGH_MASK, .index = I2C_TIMING0_THIGH_OFFSET })
#define I2C_TIMING0_TLOW_MASK 0x1fffu
#define I2C_TIMING0_TLOW_OFFSET 16
#define I2C_TIMING0_TLOW_FIELD \
  ((bitfield_field32_t) { .mask = I2C_TIMING0_TLOW_MASK, .index = I2C_TIMING0_TLOW_OFFSET })
 
// Detailed I2C Timings (directly corresponding to table 10 in the
// I<sup>2</sup>C Specification (rev. 6)).
#define I2C_TIMING1_REG_OFFSET 0x40
#define I2C_TIMING1_REG_RESVAL 0x0u
#define I2C_TIMING1_T_R_MASK 0x3ffu
#define I2C_TIMING1_T_R_OFFSET 0
#define I2C_TIMING1_T_R_FIELD \
  ((bitfield_field32_t) { .mask = I2C_TIMING1_T_R_MASK, .index = I2C_TIMING1_T_R_OFFSET })
#define I2C_TIMING1_T_F_MASK 0x1ffu
#define I2C_TIMING1_T_F_OFFSET 16
#define I2C_TIMING1_T_F_FIELD \
  ((bitfield_field32_t) { .mask = I2C_TIMING1_T_F_MASK, .index = I2C_TIMING1_T_F_OFFSET })
 
// Detailed I2C Timings (directly corresponding to table 10 in the
// I<sup>2</sup>C Specification (rev. 6)).
#define I2C_TIMING2_REG_OFFSET 0x44
#define I2C_TIMING2_REG_RESVAL 0x0u
#define I2C_TIMING2_TSU_STA_MASK 0x1fffu
#define I2C_TIMING2_TSU_STA_OFFSET 0
#define I2C_TIMING2_TSU_STA_FIELD \
  ((bitfield_field32_t) { .mask = I2C_TIMING2_TSU_STA_MASK, .index = I2C_TIMING2_TSU_STA_OFFSET })
#define I2C_TIMING2_THD_STA_MASK 0x1fffu
#define I2C_TIMING2_THD_STA_OFFSET 16
#define I2C_TIMING2_THD_STA_FIELD \
  ((bitfield_field32_t) { .mask = I2C_TIMING2_THD_STA_MASK, .index = I2C_TIMING2_THD_STA_OFFSET })
 
// Detailed I2C Timings (directly corresponding to table 10 in the
// I<sup>2</sup>C Specification (rev. 6)).
#define I2C_TIMING3_REG_OFFSET 0x48
#define I2C_TIMING3_REG_RESVAL 0x0u
#define I2C_TIMING3_TSU_DAT_MASK 0x1ffu
#define I2C_TIMING3_TSU_DAT_OFFSET 0
#define I2C_TIMING3_TSU_DAT_FIELD \
  ((bitfield_field32_t) { .mask = I2C_TIMING3_TSU_DAT_MASK, .index = I2C_TIMING3_TSU_DAT_OFFSET })
#define I2C_TIMING3_THD_DAT_MASK 0x1fffu
#define I2C_TIMING3_THD_DAT_OFFSET 16
#define I2C_TIMING3_THD_DAT_FIELD \
  ((bitfield_field32_t) { .mask = I2C_TIMING3_THD_DAT_MASK, .index = I2C_TIMING3_THD_DAT_OFFSET })
 
// Detailed I2C Timings (directly corresponding to table 10 in the
// I<sup>2</sup>C Specification (rev. 6)).
#define I2C_TIMING4_REG_OFFSET 0x4c
#define I2C_TIMING4_REG_RESVAL 0x0u
#define I2C_TIMING4_TSU_STO_MASK 0x1fffu
#define I2C_TIMING4_TSU_STO_OFFSET 0
#define I2C_TIMING4_TSU_STO_FIELD \
  ((bitfield_field32_t) { .mask = I2C_TIMING4_TSU_STO_MASK, .index = I2C_TIMING4_TSU_STO_OFFSET })
#define I2C_TIMING4_T_BUF_MASK 0x1fffu
#define I2C_TIMING4_T_BUF_OFFSET 16
#define I2C_TIMING4_T_BUF_FIELD \
  ((bitfield_field32_t) { .mask = I2C_TIMING4_T_BUF_MASK, .index = I2C_TIMING4_T_BUF_OFFSET })
 
// I2C clock stretching and bus timeout control.
#define I2C_TIMEOUT_CTRL_REG_OFFSET 0x50
#define I2C_TIMEOUT_CTRL_REG_RESVAL 0x0u
#define I2C_TIMEOUT_CTRL_VAL_MASK 0x3fffffffu
#define I2C_TIMEOUT_CTRL_VAL_OFFSET 0
#define I2C_TIMEOUT_CTRL_VAL_FIELD \
  ((bitfield_field32_t) { .mask = I2C_TIMEOUT_CTRL_VAL_MASK, .index = I2C_TIMEOUT_CTRL_VAL_OFFSET })
#define I2C_TIMEOUT_CTRL_MODE_BIT 30
#define I2C_TIMEOUT_CTRL_MODE_VALUE_STRETCH_TIMEOUT 0x0
#define I2C_TIMEOUT_CTRL_MODE_VALUE_BUS_TIMEOUT 0x1
#define I2C_TIMEOUT_CTRL_EN_BIT 31
 
// I2C target address and mask pairs
#define I2C_TARGET_ID_REG_OFFSET 0x54
#define I2C_TARGET_ID_REG_RESVAL 0x0u
#define I2C_TARGET_ID_ADDRESS0_MASK 0x7fu
#define I2C_TARGET_ID_ADDRESS0_OFFSET 0
#define I2C_TARGET_ID_ADDRESS0_FIELD \
  ((bitfield_field32_t) { .mask = I2C_TARGET_ID_ADDRESS0_MASK, .index = I2C_TARGET_ID_ADDRESS0_OFFSET })
#define I2C_TARGET_ID_MASK0_MASK 0x7fu
#define I2C_TARGET_ID_MASK0_OFFSET 7
#define I2C_TARGET_ID_MASK0_FIELD \
  ((bitfield_field32_t) { .mask = I2C_TARGET_ID_MASK0_MASK, .index = I2C_TARGET_ID_MASK0_OFFSET })
#define I2C_TARGET_ID_ADDRESS1_MASK 0x7fu
#define I2C_TARGET_ID_ADDRESS1_OFFSET 14
#define I2C_TARGET_ID_ADDRESS1_FIELD \
  ((bitfield_field32_t) { .mask = I2C_TARGET_ID_ADDRESS1_MASK, .index = I2C_TARGET_ID_ADDRESS1_OFFSET })
#define I2C_TARGET_ID_MASK1_MASK 0x7fu
#define I2C_TARGET_ID_MASK1_OFFSET 21
#define I2C_TARGET_ID_MASK1_FIELD \
  ((bitfield_field32_t) { .mask = I2C_TARGET_ID_MASK1_MASK, .index = I2C_TARGET_ID_MASK1_OFFSET })
 
// I2C target acquired data
#define I2C_ACQDATA_REG_OFFSET 0x58
#define I2C_ACQDATA_REG_RESVAL 0x0u
#define I2C_ACQDATA_ABYTE_MASK 0xffu
#define I2C_ACQDATA_ABYTE_OFFSET 0
#define I2C_ACQDATA_ABYTE_FIELD \
  ((bitfield_field32_t) { .mask = I2C_ACQDATA_ABYTE_MASK, .index = I2C_ACQDATA_ABYTE_OFFSET })
#define I2C_ACQDATA_SIGNAL_MASK 0x7u
#define I2C_ACQDATA_SIGNAL_OFFSET 8
#define I2C_ACQDATA_SIGNAL_FIELD \
  ((bitfield_field32_t) { .mask = I2C_ACQDATA_SIGNAL_MASK, .index = I2C_ACQDATA_SIGNAL_OFFSET })
#define I2C_ACQDATA_SIGNAL_VALUE_NONE 0x0
#define I2C_ACQDATA_SIGNAL_VALUE_START 0x1
#define I2C_ACQDATA_SIGNAL_VALUE_STOP 0x2
#define I2C_ACQDATA_SIGNAL_VALUE_RESTART 0x3
#define I2C_ACQDATA_SIGNAL_VALUE_NACK 0x4
#define I2C_ACQDATA_SIGNAL_VALUE_NACK_START 0x5
#define I2C_ACQDATA_SIGNAL_VALUE_NACK_STOP 0x6
 
// I2C target transmit data
#define I2C_TXDATA_REG_OFFSET 0x5c
#define I2C_TXDATA_REG_RESVAL 0x0u
#define I2C_TXDATA_TXDATA_MASK 0xffu
#define I2C_TXDATA_TXDATA_OFFSET 0
#define I2C_TXDATA_TXDATA_FIELD \
  ((bitfield_field32_t) { .mask = I2C_TXDATA_TXDATA_MASK, .index = I2C_TXDATA_TXDATA_OFFSET })
 
// I2C host clock generation timeout value (in units of input clock
// frequency).
#define I2C_HOST_TIMEOUT_CTRL_REG_OFFSET 0x60
#define I2C_HOST_TIMEOUT_CTRL_REG_RESVAL 0x0u
#define I2C_HOST_TIMEOUT_CTRL_HOST_TIMEOUT_CTRL_MASK 0xfffffu
#define I2C_HOST_TIMEOUT_CTRL_HOST_TIMEOUT_CTRL_OFFSET 0
#define I2C_HOST_TIMEOUT_CTRL_HOST_TIMEOUT_CTRL_FIELD \
  ((bitfield_field32_t) { .mask = I2C_HOST_TIMEOUT_CTRL_HOST_TIMEOUT_CTRL_MASK, .index = I2C_HOST_TIMEOUT_CTRL_HOST_TIMEOUT_CTRL_OFFSET })
 
// I2C target internal stretching timeout control.
#define I2C_TARGET_TIMEOUT_CTRL_REG_OFFSET 0x64
#define I2C_TARGET_TIMEOUT_CTRL_REG_RESVAL 0x0u
#define I2C_TARGET_TIMEOUT_CTRL_VAL_MASK 0x7fffffffu
#define I2C_TARGET_TIMEOUT_CTRL_VAL_OFFSET 0
#define I2C_TARGET_TIMEOUT_CTRL_VAL_FIELD \
  ((bitfield_field32_t) { .mask = I2C_TARGET_TIMEOUT_CTRL_VAL_MASK, .index = I2C_TARGET_TIMEOUT_CTRL_VAL_OFFSET })
#define I2C_TARGET_TIMEOUT_CTRL_EN_BIT 31
 
// Number of times the I2C target has NACK'ed a new transaction since the
// last read of this register.
#define I2C_TARGET_NACK_COUNT_REG_OFFSET 0x68
#define I2C_TARGET_NACK_COUNT_REG_RESVAL 0x0u
#define I2C_TARGET_NACK_COUNT_TARGET_NACK_COUNT_MASK 0xffu
#define I2C_TARGET_NACK_COUNT_TARGET_NACK_COUNT_OFFSET 0
#define I2C_TARGET_NACK_COUNT_TARGET_NACK_COUNT_FIELD \
  ((bitfield_field32_t) { .mask = I2C_TARGET_NACK_COUNT_TARGET_NACK_COUNT_MASK, .index = I2C_TARGET_NACK_COUNT_TARGET_NACK_COUNT_OFFSET })
 
// Controls for mid-transfer (N)ACK phase handling
#define I2C_TARGET_ACK_CTRL_REG_OFFSET 0x6c
#define I2C_TARGET_ACK_CTRL_REG_RESVAL 0x0u
#define I2C_TARGET_ACK_CTRL_NBYTES_MASK 0x1ffu
#define I2C_TARGET_ACK_CTRL_NBYTES_OFFSET 0
#define I2C_TARGET_ACK_CTRL_NBYTES_FIELD \
  ((bitfield_field32_t) { .mask = I2C_TARGET_ACK_CTRL_NBYTES_MASK, .index = I2C_TARGET_ACK_CTRL_NBYTES_OFFSET })
#define I2C_TARGET_ACK_CTRL_NACK_BIT 31
 
// The data byte pending to be written to the ACQ FIFO.
#define I2C_ACQ_FIFO_NEXT_DATA_REG_OFFSET 0x70
#define I2C_ACQ_FIFO_NEXT_DATA_REG_RESVAL 0x0u
#define I2C_ACQ_FIFO_NEXT_DATA_ACQ_FIFO_NEXT_DATA_MASK 0xffu
#define I2C_ACQ_FIFO_NEXT_DATA_ACQ_FIFO_NEXT_DATA_OFFSET 0
#define I2C_ACQ_FIFO_NEXT_DATA_ACQ_FIFO_NEXT_DATA_FIELD \
  ((bitfield_field32_t) { .mask = I2C_ACQ_FIFO_NEXT_DATA_ACQ_FIFO_NEXT_DATA_MASK, .index = I2C_ACQ_FIFO_NEXT_DATA_ACQ_FIFO_NEXT_DATA_OFFSET })
 
// Timeout in Host-Mode for an unhandled NACK before hardware automatically
// ends the transaction.
#define I2C_HOST_NACK_HANDLER_TIMEOUT_REG_OFFSET 0x74
#define I2C_HOST_NACK_HANDLER_TIMEOUT_REG_RESVAL 0x0u
#define I2C_HOST_NACK_HANDLER_TIMEOUT_VAL_MASK 0x7fffffffu
#define I2C_HOST_NACK_HANDLER_TIMEOUT_VAL_OFFSET 0
#define I2C_HOST_NACK_HANDLER_TIMEOUT_VAL_FIELD \
  ((bitfield_field32_t) { .mask = I2C_HOST_NACK_HANDLER_TIMEOUT_VAL_MASK, .index = I2C_HOST_NACK_HANDLER_TIMEOUT_VAL_OFFSET })
#define I2C_HOST_NACK_HANDLER_TIMEOUT_EN_BIT 31
 
// Latched events that explain why the controller halted.
#define I2C_CONTROLLER_EVENTS_REG_OFFSET 0x78
#define I2C_CONTROLLER_EVENTS_REG_RESVAL 0x0u
#define I2C_CONTROLLER_EVENTS_NACK_BIT 0
#define I2C_CONTROLLER_EVENTS_UNHANDLED_NACK_TIMEOUT_BIT 1
#define I2C_CONTROLLER_EVENTS_BUS_TIMEOUT_BIT 2
#define I2C_CONTROLLER_EVENTS_ARBITRATION_LOST_BIT 3
 
// Latched events that can cause the target module to stretch the clock at
// the beginning of a read transfer.
#define I2C_TARGET_EVENTS_REG_OFFSET 0x7c
#define I2C_TARGET_EVENTS_REG_RESVAL 0x0u
#define I2C_TARGET_EVENTS_TX_PENDING_BIT 0
#define I2C_TARGET_EVENTS_BUS_TIMEOUT_BIT 1
#define I2C_TARGET_EVENTS_ARBITRATION_LOST_BIT 2
 
#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _I2C_REG_DEFS_
// End generated register defines for i2c