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Software APIs
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Software APIs
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Generated register defines for edn. More...
Go to the source code of this file.
Generated register defines for edn.
Definition in file edn_regs.h.
| #define EDN_ALERT_TEST_FATAL_ALERT_BIT 1 |
Definition at line 51 of file edn_regs.h.
| #define EDN_ALERT_TEST_RECOV_ALERT_BIT 0 |
Definition at line 50 of file edn_regs.h.
| #define EDN_ALERT_TEST_REG_OFFSET 0xc |
Definition at line 48 of file edn_regs.h.
| #define EDN_ALERT_TEST_REG_RESVAL 0x0u |
Definition at line 49 of file edn_regs.h.
| #define EDN_BOOT_GEN_CMD_REG_OFFSET 0x1c |
Definition at line 83 of file edn_regs.h.
| #define EDN_BOOT_GEN_CMD_REG_RESVAL 0xfff003u |
Definition at line 84 of file edn_regs.h.
| #define EDN_BOOT_INS_CMD_REG_OFFSET 0x18 |
Definition at line 79 of file edn_regs.h.
| #define EDN_BOOT_INS_CMD_REG_RESVAL 0x901u |
Definition at line 80 of file edn_regs.h.
| #define EDN_CTRL_AUTO_REQ_MODE_FIELD ((bitfield_field32_t) { .mask = EDN_CTRL_AUTO_REQ_MODE_MASK, .index = EDN_CTRL_AUTO_REQ_MODE_OFFSET }) |
Definition at line 71 of file edn_regs.h.
| #define EDN_CTRL_AUTO_REQ_MODE_MASK 0xfu |
Definition at line 69 of file edn_regs.h.
| #define EDN_CTRL_AUTO_REQ_MODE_OFFSET 8 |
Definition at line 70 of file edn_regs.h.
| #define EDN_CTRL_BOOT_REQ_MODE_FIELD ((bitfield_field32_t) { .mask = EDN_CTRL_BOOT_REQ_MODE_MASK, .index = EDN_CTRL_BOOT_REQ_MODE_OFFSET }) |
Definition at line 67 of file edn_regs.h.
| #define EDN_CTRL_BOOT_REQ_MODE_MASK 0xfu |
Definition at line 65 of file edn_regs.h.
| #define EDN_CTRL_BOOT_REQ_MODE_OFFSET 4 |
Definition at line 66 of file edn_regs.h.
| #define EDN_CTRL_CMD_FIFO_RST_FIELD ((bitfield_field32_t) { .mask = EDN_CTRL_CMD_FIFO_RST_MASK, .index = EDN_CTRL_CMD_FIFO_RST_OFFSET }) |
Definition at line 75 of file edn_regs.h.
| #define EDN_CTRL_CMD_FIFO_RST_MASK 0xfu |
Definition at line 73 of file edn_regs.h.
| #define EDN_CTRL_CMD_FIFO_RST_OFFSET 12 |
Definition at line 74 of file edn_regs.h.
| #define EDN_CTRL_EDN_ENABLE_FIELD ((bitfield_field32_t) { .mask = EDN_CTRL_EDN_ENABLE_MASK, .index = EDN_CTRL_EDN_ENABLE_OFFSET }) |
Definition at line 63 of file edn_regs.h.
| #define EDN_CTRL_EDN_ENABLE_MASK 0xfu |
Definition at line 61 of file edn_regs.h.
| #define EDN_CTRL_EDN_ENABLE_OFFSET 0 |
Definition at line 62 of file edn_regs.h.
| #define EDN_CTRL_REG_OFFSET 0x14 |
Definition at line 59 of file edn_regs.h.
| #define EDN_CTRL_REG_RESVAL 0x9999u |
Definition at line 60 of file edn_regs.h.
| #define EDN_ERR_CODE_EDN_ACK_SM_ERR_BIT 20 |
Definition at line 143 of file edn_regs.h.
| #define EDN_ERR_CODE_EDN_CNTR_ERR_BIT 22 |
Definition at line 145 of file edn_regs.h.
| #define EDN_ERR_CODE_EDN_MAIN_SM_ERR_BIT 21 |
Definition at line 144 of file edn_regs.h.
| #define EDN_ERR_CODE_FIFO_READ_ERR_BIT 29 |
Definition at line 147 of file edn_regs.h.
| #define EDN_ERR_CODE_FIFO_STATE_ERR_BIT 30 |
Definition at line 148 of file edn_regs.h.
| #define EDN_ERR_CODE_FIFO_WRITE_ERR_BIT 28 |
Definition at line 146 of file edn_regs.h.
| #define EDN_ERR_CODE_REG_OFFSET 0x3c |
Definition at line 139 of file edn_regs.h.
| #define EDN_ERR_CODE_REG_RESVAL 0x0u |
Definition at line 140 of file edn_regs.h.
| #define EDN_ERR_CODE_SFIFO_GENCMD_ERR_BIT 1 |
Definition at line 142 of file edn_regs.h.
| #define EDN_ERR_CODE_SFIFO_RESCMD_ERR_BIT 0 |
Definition at line 141 of file edn_regs.h.
| #define EDN_ERR_CODE_TEST_ERR_CODE_TEST_FIELD ((bitfield_field32_t) { .mask = EDN_ERR_CODE_TEST_ERR_CODE_TEST_MASK, .index = EDN_ERR_CODE_TEST_ERR_CODE_TEST_OFFSET }) |
Definition at line 155 of file edn_regs.h.
| #define EDN_ERR_CODE_TEST_ERR_CODE_TEST_MASK 0x1fu |
Definition at line 153 of file edn_regs.h.
| #define EDN_ERR_CODE_TEST_ERR_CODE_TEST_OFFSET 0 |
Definition at line 154 of file edn_regs.h.
| #define EDN_ERR_CODE_TEST_REG_OFFSET 0x40 |
Definition at line 151 of file edn_regs.h.
| #define EDN_ERR_CODE_TEST_REG_RESVAL 0x0u |
Definition at line 152 of file edn_regs.h.
| #define EDN_GENERATE_CMD_REG_OFFSET 0x30 |
Definition at line 121 of file edn_regs.h.
| #define EDN_GENERATE_CMD_REG_RESVAL 0x0u |
Definition at line 122 of file edn_regs.h.
| #define EDN_HW_CMD_STS_AUTO_MODE_BIT 1 |
Definition at line 105 of file edn_regs.h.
| #define EDN_HW_CMD_STS_BOOT_MODE_BIT 0 |
Definition at line 104 of file edn_regs.h.
| #define EDN_HW_CMD_STS_CMD_ACK_BIT 6 |
Definition at line 110 of file edn_regs.h.
| #define EDN_HW_CMD_STS_CMD_STS_FIELD ((bitfield_field32_t) { .mask = EDN_HW_CMD_STS_CMD_STS_MASK, .index = EDN_HW_CMD_STS_CMD_STS_OFFSET }) |
Definition at line 113 of file edn_regs.h.
| #define EDN_HW_CMD_STS_CMD_STS_MASK 0x7u |
Definition at line 111 of file edn_regs.h.
| #define EDN_HW_CMD_STS_CMD_STS_OFFSET 7 |
Definition at line 112 of file edn_regs.h.
| #define EDN_HW_CMD_STS_CMD_TYPE_FIELD ((bitfield_field32_t) { .mask = EDN_HW_CMD_STS_CMD_TYPE_MASK, .index = EDN_HW_CMD_STS_CMD_TYPE_OFFSET }) |
Definition at line 108 of file edn_regs.h.
| #define EDN_HW_CMD_STS_CMD_TYPE_MASK 0xfu |
Definition at line 106 of file edn_regs.h.
| #define EDN_HW_CMD_STS_CMD_TYPE_OFFSET 2 |
Definition at line 107 of file edn_regs.h.
| #define EDN_HW_CMD_STS_REG_OFFSET 0x28 |
Definition at line 102 of file edn_regs.h.
| #define EDN_HW_CMD_STS_REG_RESVAL 0x0u |
Definition at line 103 of file edn_regs.h.
| #define EDN_INTR_COMMON_EDN_CMD_REQ_DONE_BIT 0 |
Definition at line 26 of file edn_regs.h.
| #define EDN_INTR_COMMON_EDN_FATAL_ERR_BIT 1 |
Definition at line 27 of file edn_regs.h.
| #define EDN_INTR_ENABLE_EDN_CMD_REQ_DONE_BIT 0 |
Definition at line 38 of file edn_regs.h.
| #define EDN_INTR_ENABLE_EDN_FATAL_ERR_BIT 1 |
Definition at line 39 of file edn_regs.h.
| #define EDN_INTR_ENABLE_REG_OFFSET 0x4 |
Definition at line 36 of file edn_regs.h.
| #define EDN_INTR_ENABLE_REG_RESVAL 0x0u |
Definition at line 37 of file edn_regs.h.
| #define EDN_INTR_STATE_EDN_CMD_REQ_DONE_BIT 0 |
Definition at line 32 of file edn_regs.h.
| #define EDN_INTR_STATE_EDN_FATAL_ERR_BIT 1 |
Definition at line 33 of file edn_regs.h.
| #define EDN_INTR_STATE_REG_OFFSET 0x0 |
Definition at line 30 of file edn_regs.h.
| #define EDN_INTR_STATE_REG_RESVAL 0x0u |
Definition at line 31 of file edn_regs.h.
| #define EDN_INTR_TEST_EDN_CMD_REQ_DONE_BIT 0 |
Definition at line 44 of file edn_regs.h.
| #define EDN_INTR_TEST_EDN_FATAL_ERR_BIT 1 |
Definition at line 45 of file edn_regs.h.
| #define EDN_INTR_TEST_REG_OFFSET 0x8 |
Definition at line 42 of file edn_regs.h.
| #define EDN_INTR_TEST_REG_RESVAL 0x0u |
Definition at line 43 of file edn_regs.h.
| #define EDN_MAIN_SM_STATE_MAIN_SM_STATE_FIELD ((bitfield_field32_t) { .mask = EDN_MAIN_SM_STATE_MAIN_SM_STATE_MASK, .index = EDN_MAIN_SM_STATE_MAIN_SM_STATE_OFFSET }) |
Definition at line 163 of file edn_regs.h.
| #define EDN_MAIN_SM_STATE_MAIN_SM_STATE_MASK 0x1ffu |
Definition at line 161 of file edn_regs.h.
| #define EDN_MAIN_SM_STATE_MAIN_SM_STATE_OFFSET 0 |
Definition at line 162 of file edn_regs.h.
| #define EDN_MAIN_SM_STATE_REG_OFFSET 0x44 |
Definition at line 159 of file edn_regs.h.
| #define EDN_MAIN_SM_STATE_REG_RESVAL 0xc1u |
Definition at line 160 of file edn_regs.h.
| #define EDN_MAX_NUM_REQS_BETWEEN_RESEEDS_REG_OFFSET 0x34 |
Definition at line 125 of file edn_regs.h.
| #define EDN_MAX_NUM_REQS_BETWEEN_RESEEDS_REG_RESVAL 0x0u |
Definition at line 126 of file edn_regs.h.
| #define EDN_PARAM_NUM_ALERTS 2 |
Definition at line 20 of file edn_regs.h.
| #define EDN_PARAM_REG_WIDTH 32 |
Definition at line 23 of file edn_regs.h.
| #define EDN_RECOV_ALERT_STS_AUTO_REQ_MODE_FIELD_ALERT_BIT 2 |
Definition at line 133 of file edn_regs.h.
| #define EDN_RECOV_ALERT_STS_BOOT_REQ_MODE_FIELD_ALERT_BIT 1 |
Definition at line 132 of file edn_regs.h.
| #define EDN_RECOV_ALERT_STS_CMD_FIFO_RST_FIELD_ALERT_BIT 3 |
Definition at line 134 of file edn_regs.h.
| #define EDN_RECOV_ALERT_STS_CSRNG_ACK_ERR_BIT 13 |
Definition at line 136 of file edn_regs.h.
| #define EDN_RECOV_ALERT_STS_EDN_BUS_CMP_ALERT_BIT 12 |
Definition at line 135 of file edn_regs.h.
| #define EDN_RECOV_ALERT_STS_EDN_ENABLE_FIELD_ALERT_BIT 0 |
Definition at line 131 of file edn_regs.h.
| #define EDN_RECOV_ALERT_STS_REG_OFFSET 0x38 |
Definition at line 129 of file edn_regs.h.
| #define EDN_RECOV_ALERT_STS_REG_RESVAL 0x0u |
Definition at line 130 of file edn_regs.h.
| #define EDN_REGWEN_REG_OFFSET 0x10 |
Definition at line 54 of file edn_regs.h.
| #define EDN_REGWEN_REG_RESVAL 0x1u |
Definition at line 55 of file edn_regs.h.
| #define EDN_REGWEN_REGWEN_BIT 0 |
Definition at line 56 of file edn_regs.h.
| #define EDN_RESEED_CMD_REG_OFFSET 0x2c |
Definition at line 117 of file edn_regs.h.
| #define EDN_RESEED_CMD_REG_RESVAL 0x0u |
Definition at line 118 of file edn_regs.h.
| #define EDN_SW_CMD_REQ_REG_OFFSET 0x20 |
Definition at line 87 of file edn_regs.h.
| #define EDN_SW_CMD_REQ_REG_RESVAL 0x0u |
Definition at line 88 of file edn_regs.h.
| #define EDN_SW_CMD_STS_CMD_ACK_BIT 2 |
Definition at line 95 of file edn_regs.h.
| #define EDN_SW_CMD_STS_CMD_RDY_BIT 1 |
Definition at line 94 of file edn_regs.h.
| #define EDN_SW_CMD_STS_CMD_REG_RDY_BIT 0 |
Definition at line 93 of file edn_regs.h.
| #define EDN_SW_CMD_STS_CMD_STS_FIELD ((bitfield_field32_t) { .mask = EDN_SW_CMD_STS_CMD_STS_MASK, .index = EDN_SW_CMD_STS_CMD_STS_OFFSET }) |
Definition at line 98 of file edn_regs.h.
| #define EDN_SW_CMD_STS_CMD_STS_MASK 0x7u |
Definition at line 96 of file edn_regs.h.
| #define EDN_SW_CMD_STS_CMD_STS_OFFSET 3 |
Definition at line 97 of file edn_regs.h.
| #define EDN_SW_CMD_STS_REG_OFFSET 0x24 |
Definition at line 91 of file edn_regs.h.
| #define EDN_SW_CMD_STS_REG_RESVAL 0x0u |
Definition at line 92 of file edn_regs.h.