Software APIs
dt_uart.c
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7/**
8 * @file
9 * @brief Device Tables (DT) for IP uart and top earlgrey.
10 */
11
12#include "hw/top/dt/dt_uart.h"
13
14
15
16/**
17 * Description of instances.
18 */
19typedef struct dt_desc_uart {
20 dt_instance_id_t inst_id; /**< Instance ID */
21 uint32_t reg_addr[kDtUartRegBlockCount]; /**< Base address of each register block */
22 uint32_t mem_addr[kDtUartMemoryCount]; /**< Base address of each memory */
23 uint32_t mem_size[kDtUartMemoryCount]; /**< Size in bytes of each memory */
24 /**
25 * PLIC ID of the first IRQ of this instance
26 *
27 * This can be `kDtPlicIrqIdNone` if the block is not connected to the PLIC.
28 */
30 /**
31 * Alert ID of the first Alert of this instance.
32 *
33 * This value is undefined if the block is not connected to the Alert Handler.
34 */
36 dt_clock_t clock[kDtUartClockCount]; /**< Clock signal connected to each clock port */
37 dt_reset_t reset[kDtUartResetCount]; /**< Reset signal connected to each reset port */
38 dt_periph_io_t periph_io[kDtUartPeriphIoCount]; /**< Description of each peripheral I/O */
40
41
42
43
44static const dt_desc_uart_t uart_desc[kDtUartCount] = {
45 [kDtUart0] = {
46 .inst_id = kDtInstanceIdUart0,
47 .reg_addr = {
48 [kDtUartRegBlockCore] = 0x40000000,
49 },
50 .mem_addr = {
51 },
52 .mem_size = {
53 },
56 .clock = {
58 },
59 .reset = {
61 },
62 .periph_io = {
63 [kDtUartPeriphIoRx] = {
64 .__internal = {
65 .type = kDtPeriphIoTypeMio,
66 .dir = kDtPeriphIoDirIn,
67 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInUart0Rx,
68 .outsel_or_dt_pad = 0,
69 },
70 },
71 [kDtUartPeriphIoTx] = {
72 .__internal = {
73 .type = kDtPeriphIoTypeMio,
74 .dir = kDtPeriphIoDirOut,
75 .periph_input_or_direct_pad = 0,
76 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselUart0Tx,
77 },
78 },
79 },
80 },
81 [kDtUart1] = {
82 .inst_id = kDtInstanceIdUart1,
83 .reg_addr = {
84 [kDtUartRegBlockCore] = 0x40010000,
85 },
86 .mem_addr = {
87 },
88 .mem_size = {
89 },
92 .clock = {
94 },
95 .reset = {
97 },
98 .periph_io = {
99 [kDtUartPeriphIoRx] = {
100 .__internal = {
101 .type = kDtPeriphIoTypeMio,
102 .dir = kDtPeriphIoDirIn,
103 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInUart1Rx,
104 .outsel_or_dt_pad = 0,
105 },
106 },
107 [kDtUartPeriphIoTx] = {
108 .__internal = {
109 .type = kDtPeriphIoTypeMio,
110 .dir = kDtPeriphIoDirOut,
111 .periph_input_or_direct_pad = 0,
112 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselUart1Tx,
113 },
114 },
115 },
116 },
117 [kDtUart2] = {
118 .inst_id = kDtInstanceIdUart2,
119 .reg_addr = {
120 [kDtUartRegBlockCore] = 0x40020000,
121 },
122 .mem_addr = {
123 },
124 .mem_size = {
125 },
128 .clock = {
130 },
131 .reset = {
133 },
134 .periph_io = {
135 [kDtUartPeriphIoRx] = {
136 .__internal = {
137 .type = kDtPeriphIoTypeMio,
138 .dir = kDtPeriphIoDirIn,
139 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInUart2Rx,
140 .outsel_or_dt_pad = 0,
141 },
142 },
143 [kDtUartPeriphIoTx] = {
144 .__internal = {
145 .type = kDtPeriphIoTypeMio,
146 .dir = kDtPeriphIoDirOut,
147 .periph_input_or_direct_pad = 0,
148 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselUart2Tx,
149 },
150 },
151 },
152 },
153 [kDtUart3] = {
154 .inst_id = kDtInstanceIdUart3,
155 .reg_addr = {
156 [kDtUartRegBlockCore] = 0x40030000,
157 },
158 .mem_addr = {
159 },
160 .mem_size = {
161 },
164 .clock = {
166 },
167 .reset = {
169 },
170 .periph_io = {
171 [kDtUartPeriphIoRx] = {
172 .__internal = {
173 .type = kDtPeriphIoTypeMio,
174 .dir = kDtPeriphIoDirIn,
175 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInUart3Rx,
176 .outsel_or_dt_pad = 0,
177 },
178 },
179 [kDtUartPeriphIoTx] = {
180 .__internal = {
181 .type = kDtPeriphIoTypeMio,
182 .dir = kDtPeriphIoDirOut,
183 .periph_input_or_direct_pad = 0,
184 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselUart3Tx,
185 },
186 },
187 },
188 },
189};
190
191/**
192 * Return a pointer to the `dt_uart_desc_t` structure of the requested
193 * `dt` if it's a valid index. Otherwise, this macro will `return` (i.e. exit
194 * the function) with the provided default value.
195 */
196#define TRY_GET_DT(dt, default) ({ if ((dt) < (dt_uart_t)0 || (dt) >= kDtUartCount) return (default); &uart_desc[dt]; })
197
199 if (inst_id >= kDtInstanceIdUart0 && inst_id <= kDtInstanceIdUart3) {
200 return (dt_uart_t)(inst_id - kDtInstanceIdUart0);
201 }
202 return (dt_uart_t)0;
203}
204
209
211 dt_uart_t dt,
212 dt_uart_reg_block_t reg_block) {
213 // Return a recognizable address in case of wrong argument.
214 return TRY_GET_DT(dt, 0xdeadbeef)->reg_addr[reg_block];
215}
216
218 dt_uart_t dt,
219 dt_uart_memory_t mem) {
220 // Return a recognizable address in case of wrong argument.
221 return TRY_GET_DT(dt, 0xdeadbeef)->mem_addr[mem];
222}
223
225 dt_uart_t dt,
226 dt_uart_memory_t mem) {
227 // Return an empty size in case of wrong argument.
228 return TRY_GET_DT(dt, 0)->mem_size[mem];
229}
230
232 dt_uart_t dt,
233 dt_uart_irq_t irq) {
234 dt_plic_irq_id_t first_irq = TRY_GET_DT(dt, kDtPlicIrqIdNone)->first_irq;
235 if (first_irq == kDtPlicIrqIdNone) {
236 return kDtPlicIrqIdNone;
237 }
238 return (dt_plic_irq_id_t)((uint32_t)first_irq + (uint32_t)irq);
239}
240
242 dt_uart_t dt,
243 dt_plic_irq_id_t irq) {
244 dt_uart_irq_t count = kDtUartIrqCount;
245 dt_plic_irq_id_t first_irq = TRY_GET_DT(dt, count)->first_irq;
246 if (first_irq == kDtPlicIrqIdNone) {
247 return count;
248 }
249 if (irq < first_irq || irq >= first_irq + (dt_plic_irq_id_t)count) {
250 return count;
251 }
252 return (dt_uart_irq_t)(irq - first_irq);
253}
254
255
257 dt_uart_t dt,
258 dt_uart_alert_t alert) {
259 return (dt_alert_id_t)((uint32_t)uart_desc[dt].first_alert + (uint32_t)alert);
260}
261
263 dt_uart_t dt,
264 dt_alert_id_t alert) {
265 dt_uart_alert_t count = kDtUartAlertCount;
266 if (alert < uart_desc[dt].first_alert || alert >= uart_desc[dt].first_alert + (dt_alert_id_t)count) {
267 return count;
268 }
269 return (dt_uart_alert_t)(alert - uart_desc[dt].first_alert);
270}
271
272
274 dt_uart_t dt,
276 // Return a harmless value in case of wrong argument.
277 return TRY_GET_DT(dt, kDtPeriphIoConstantHighZ)->periph_io[sig];
278}
279
281 dt_uart_t dt,
282 dt_uart_clock_t clk) {
283 // Return the first clock in case of invalid argument.
284 return TRY_GET_DT(dt, (dt_clock_t)0)->clock[clk];
285}
286
288 dt_uart_t dt,
289 dt_uart_reset_t rst) {
290 const dt_uart_reset_t count = kDtUartResetCount;
291 if (rst >= count) {
292 return kDtResetUnknown;
293 }
294 return TRY_GET_DT(dt, kDtResetUnknown)->reset[rst];
295}
296
297