Software APIs
dt_pwrmgr.c
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7/**
8 * @file
9 * @brief Device Tables (DT) for IP pwrmgr and top earlgrey.
10 */
11
12#include "hw/top/dt/dt_pwrmgr.h"
13
14
15#include "dt_sysrst_ctrl.h"
16#include "dt_adc_ctrl.h"
17#include "dt_pinmux.h"
18#include "dt_aon_timer.h"
19#include "dt_sensor_ctrl.h"
20
21
22
23/**
24 * Description of instances.
25 */
26typedef struct dt_desc_pwrmgr {
27 dt_instance_id_t inst_id; /**< Instance ID */
28 uint32_t reg_addr[kDtPwrmgrRegBlockCount]; /**< Base address of each register block */
29 uint32_t mem_addr[kDtPwrmgrMemoryCount]; /**< Base address of each memory */
30 uint32_t mem_size[kDtPwrmgrMemoryCount]; /**< Size in bytes of each memory */
31 /**
32 * PLIC ID of the first IRQ of this instance
33 *
34 * This can be `kDtPlicIrqIdNone` if the block is not connected to the PLIC.
35 */
37 /**
38 * Alert ID of the first Alert of this instance.
39 *
40 * This value is undefined if the block is not connected to the Alert Handler.
41 */
43 dt_clock_t clock[kDtPwrmgrClockCount]; /**< Clock signal connected to each clock port */
44 dt_reset_t reset[kDtPwrmgrResetCount]; /**< Reset signal connected to each reset port */
45 struct {
46 dt_pwrmgr_wakeup_src_t wakeup_src[6]; /**< List of wakeup sources, in the order of the register fields */
47 dt_pwrmgr_reset_req_src_t rst_reqs[2]; /**< List of reset requests, in the order of the register fields */
48 } pwrmgr_ext; /**< Extension */
50
51
52
53
54static const dt_desc_pwrmgr_t pwrmgr_desc[kDtPwrmgrCount] = {
55 [kDtPwrmgrAon] = {
56 .inst_id = kDtInstanceIdPwrmgrAon,
57 .reg_addr = {
58 [kDtPwrmgrRegBlockCore] = 0x40400000,
59 },
60 .mem_addr = {
61 },
62 .mem_size = {
63 },
66 .clock = {
71 },
72 .reset = {
78 },
79 .pwrmgr_ext = {
80 .wakeup_src = {
81 [0] = {
84 },
85 [1] = {
86 .inst_id = kDtInstanceIdAdcCtrlAon,
88 },
89 [2] = {
90 .inst_id = kDtInstanceIdPinmuxAon,
92 },
93 [3] = {
94 .inst_id = kDtInstanceIdPinmuxAon,
96 },
97 [4] = {
98 .inst_id = kDtInstanceIdAonTimerAon,
100 },
101 [5] = {
104 },
105 },
106 .rst_reqs = {
107 [0] = {
109 .reset_req = kDtSysrstCtrlResetReqRstReq,
110 },
111 [1] = {
112 .inst_id = kDtInstanceIdAonTimerAon,
113 .reset_req = kDtAonTimerResetReqAonTimer,
114 },
115 },
116 },
117 },
118};
119
120/**
121 * Return a pointer to the `dt_pwrmgr_desc_t` structure of the requested
122 * `dt` if it's a valid index. Otherwise, this macro will `return` (i.e. exit
123 * the function) with the provided default value.
124 */
125#define TRY_GET_DT(dt, default) ({ if ((dt) < (dt_pwrmgr_t)0 || (dt) >= kDtPwrmgrCount) return (default); &pwrmgr_desc[dt]; })
126
128 if (inst_id >= kDtInstanceIdPwrmgrAon && inst_id <= kDtInstanceIdPwrmgrAon) {
129 return (dt_pwrmgr_t)(inst_id - kDtInstanceIdPwrmgrAon);
130 }
131 return (dt_pwrmgr_t)0;
132}
133
138
140 dt_pwrmgr_t dt,
141 dt_pwrmgr_reg_block_t reg_block) {
142 // Return a recognizable address in case of wrong argument.
143 return TRY_GET_DT(dt, 0xdeadbeef)->reg_addr[reg_block];
144}
145
147 dt_pwrmgr_t dt,
148 dt_pwrmgr_memory_t mem) {
149 // Return a recognizable address in case of wrong argument.
150 return TRY_GET_DT(dt, 0xdeadbeef)->mem_addr[mem];
151}
152
154 dt_pwrmgr_t dt,
155 dt_pwrmgr_memory_t mem) {
156 // Return an empty size in case of wrong argument.
157 return TRY_GET_DT(dt, 0)->mem_size[mem];
158}
159
161 dt_pwrmgr_t dt,
162 dt_pwrmgr_irq_t irq) {
163 dt_plic_irq_id_t first_irq = TRY_GET_DT(dt, kDtPlicIrqIdNone)->first_irq;
164 if (first_irq == kDtPlicIrqIdNone) {
165 return kDtPlicIrqIdNone;
166 }
167 return (dt_plic_irq_id_t)((uint32_t)first_irq + (uint32_t)irq);
168}
169
171 dt_pwrmgr_t dt,
172 dt_plic_irq_id_t irq) {
173 dt_pwrmgr_irq_t count = kDtPwrmgrIrqCount;
174 dt_plic_irq_id_t first_irq = TRY_GET_DT(dt, count)->first_irq;
175 if (first_irq == kDtPlicIrqIdNone) {
176 return count;
177 }
178 if (irq < first_irq || irq >= first_irq + (dt_plic_irq_id_t)count) {
179 return count;
180 }
181 return (dt_pwrmgr_irq_t)(irq - first_irq);
182}
183
184
186 dt_pwrmgr_t dt,
187 dt_pwrmgr_alert_t alert) {
188 return (dt_alert_id_t)((uint32_t)pwrmgr_desc[dt].first_alert + (uint32_t)alert);
189}
190
192 dt_pwrmgr_t dt,
193 dt_alert_id_t alert) {
194 dt_pwrmgr_alert_t count = kDtPwrmgrAlertCount;
195 if (alert < pwrmgr_desc[dt].first_alert || alert >= pwrmgr_desc[dt].first_alert + (dt_alert_id_t)count) {
196 return count;
197 }
198 return (dt_pwrmgr_alert_t)(alert - pwrmgr_desc[dt].first_alert);
199}
200
201
202
204 dt_pwrmgr_t dt,
205 dt_pwrmgr_clock_t clk) {
206 // Return the first clock in case of invalid argument.
207 return TRY_GET_DT(dt, (dt_clock_t)0)->clock[clk];
208}
209
211 dt_pwrmgr_t dt,
212 dt_pwrmgr_reset_t rst) {
213 const dt_pwrmgr_reset_t count = kDtPwrmgrResetCount;
214 if (rst >= count) {
215 return kDtResetUnknown;
216 }
217 return TRY_GET_DT(dt, kDtResetUnknown)->reset[rst];
218}
219
220
221
223 return 6;
224}
225
227 dt_pwrmgr_wakeup_src_t invalid = {.inst_id = kDtInstanceIdUnknown, .wakeup = 0};
228 return TRY_GET_DT(dt, invalid)->pwrmgr_ext.wakeup_src[idx];
229}
230
232 return 2;
233}
234
236 dt_pwrmgr_reset_req_src_t invalid = {.inst_id = kDtInstanceIdUnknown, .reset_req = 0};
237 return TRY_GET_DT(dt, invalid)->pwrmgr_ext.rst_reqs[idx];
238}
239
240