Software APIs
dt_otp_ctrl.c
Go to the documentation of this file.
1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7/**
8 * @file
9 * @brief Device Tables (DT) for IP otp_ctrl and top earlgrey.
10 */
11
12#include "dt/dt_otp_ctrl.h"
13
14
15#include "otp_ctrl_regs.h"
16
17
18/**
19 * Description of instances.
20 */
21typedef struct dt_desc_otp_ctrl {
22 dt_instance_id_t inst_id; /**< Instance ID */
23 uint32_t base_addr[kDtOtpCtrlRegBlockCount]; /**< Base address of each register block */
24 /**
25 * PLIC ID of the first IRQ of this instance
26 *
27 * This can be `kDtPlicIrqIdNone` if the block is not connected to the PLIC.
28 */
30 /**
31 * Alert ID of the first Alert of this instance.
32 *
33 * This value is undefined if the block is not connected to the Alert Handler.
34 */
36 dt_clock_t clock[kDtOtpCtrlClockCount]; /**< Clock signal connected to each clock port */
37 dt_reset_t reset[kDtOtpCtrlResetCount]; /**< Reset signal connected to each reset port */
38 struct {
39 dt_otp_partition_info_t info[7]; /**< List of SW readable OTP partitions */
40 } sw_readable_partitions; /**< Extension */
42
43
44
45
46static const dt_desc_otp_ctrl_t otp_ctrl_desc[kDtOtpCtrlCount] = {
47 [kDtOtpCtrl] = {
48 .inst_id = kDtInstanceIdOtpCtrl,
49 .base_addr = {
50 [kDtOtpCtrlRegBlockCore] = 0x40130000,
51 },
54 .clock = {
57 },
58 .reset = {
61 },
62 .sw_readable_partitions = {
63 .info = {
64 [kOtpPartitionVendorTest] = {
65 .start_addr = OTP_CTRL_PARAM_VENDOR_TEST_OFFSET,
66 .size = OTP_CTRL_PARAM_VENDOR_TEST_SIZE - OTP_CTRL_PARAM_VENDOR_TEST_DIGEST_SIZE,
67 .digest_addr = OTP_CTRL_VENDOR_TEST_DIGEST_0_REG_OFFSET,
68 .align_mask = 0x3,
69 },
70 [kOtpPartitionCreatorSwCfg] = {
71 .start_addr = OTP_CTRL_PARAM_CREATOR_SW_CFG_OFFSET,
72 .size = OTP_CTRL_PARAM_CREATOR_SW_CFG_SIZE - OTP_CTRL_PARAM_CREATOR_SW_CFG_DIGEST_SIZE,
73 .digest_addr = OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_REG_OFFSET,
74 .align_mask = 0x3,
75 },
76 [kOtpPartitionOwnerSwCfg] = {
77 .start_addr = OTP_CTRL_PARAM_OWNER_SW_CFG_OFFSET,
78 .size = OTP_CTRL_PARAM_OWNER_SW_CFG_SIZE - OTP_CTRL_PARAM_OWNER_SW_CFG_DIGEST_SIZE,
79 .digest_addr = OTP_CTRL_OWNER_SW_CFG_DIGEST_0_REG_OFFSET,
80 .align_mask = 0x3,
81 },
82 [kOtpPartitionRotCreatorAuthCodesign] = {
83 .start_addr = OTP_CTRL_PARAM_ROT_CREATOR_AUTH_CODESIGN_OFFSET,
84 .size = OTP_CTRL_PARAM_ROT_CREATOR_AUTH_CODESIGN_SIZE - OTP_CTRL_PARAM_ROT_CREATOR_AUTH_CODESIGN_DIGEST_SIZE,
85 .digest_addr = OTP_CTRL_ROT_CREATOR_AUTH_CODESIGN_DIGEST_0_REG_OFFSET,
86 .align_mask = 0x3,
87 },
88 [kOtpPartitionRotCreatorAuthState] = {
89 .start_addr = OTP_CTRL_PARAM_ROT_CREATOR_AUTH_STATE_OFFSET,
90 .size = OTP_CTRL_PARAM_ROT_CREATOR_AUTH_STATE_SIZE - OTP_CTRL_PARAM_ROT_CREATOR_AUTH_STATE_DIGEST_SIZE,
91 .digest_addr = OTP_CTRL_ROT_CREATOR_AUTH_STATE_DIGEST_0_REG_OFFSET,
92 .align_mask = 0x3,
93 },
94 [kOtpPartitionHwCfg0] = {
95 .start_addr = OTP_CTRL_PARAM_HW_CFG0_OFFSET,
96 .size = OTP_CTRL_PARAM_HW_CFG0_SIZE - OTP_CTRL_PARAM_HW_CFG0_DIGEST_SIZE,
97 .digest_addr = OTP_CTRL_HW_CFG0_DIGEST_0_REG_OFFSET,
98 .align_mask = 0x3,
99 },
100 [kOtpPartitionHwCfg1] = {
101 .start_addr = OTP_CTRL_PARAM_HW_CFG1_OFFSET,
102 .size = OTP_CTRL_PARAM_HW_CFG1_SIZE - OTP_CTRL_PARAM_HW_CFG1_DIGEST_SIZE,
103 .digest_addr = OTP_CTRL_HW_CFG1_DIGEST_0_REG_OFFSET,
104 .align_mask = 0x3,
105 },
106 },
107 },
108 },
109};
110
111/**
112 * Return a pointer to the `dt_otp_ctrl_desc_t` structure of the requested
113 * `dt` if it's a valid index. Otherwise, this macro will `return` (i.e. exit
114 * the function) with the provided default value.
115 */
116#define TRY_GET_DT(dt, default) ({ if ((dt) < (dt_otp_ctrl_t)0 || (dt) >= kDtOtpCtrlCount) return (default); &otp_ctrl_desc[dt]; })
117
119 if (inst_id >= kDtInstanceIdOtpCtrl && inst_id <= kDtInstanceIdOtpCtrl) {
120 return (dt_otp_ctrl_t)(inst_id - kDtInstanceIdOtpCtrl);
121 }
122 return (dt_otp_ctrl_t)0;
123}
124
129
131 dt_otp_ctrl_t dt,
132 dt_otp_ctrl_reg_block_t reg_block) {
133 // Return a recognizable address in case of wrong argument.
134 return TRY_GET_DT(dt, 0xdeadbeef)->base_addr[reg_block];
135}
136
138 dt_otp_ctrl_t dt,
139 dt_otp_ctrl_irq_t irq) {
140 dt_plic_irq_id_t first_irq = TRY_GET_DT(dt, kDtPlicIrqIdNone)->first_irq;
141 if (first_irq == kDtPlicIrqIdNone) {
142 return kDtPlicIrqIdNone;
143 }
144 return (dt_plic_irq_id_t)((uint32_t)first_irq + (uint32_t)irq);
145}
146
148 dt_otp_ctrl_t dt,
149 dt_plic_irq_id_t irq) {
150 dt_otp_ctrl_irq_t count = kDtOtpCtrlIrqCount;
151 dt_plic_irq_id_t first_irq = TRY_GET_DT(dt, count)->first_irq;
152 if (first_irq == kDtPlicIrqIdNone) {
153 return count;
154 }
155 if (irq < first_irq || irq >= first_irq + (dt_plic_irq_id_t)count) {
156 return count;
157 }
158 return (dt_otp_ctrl_irq_t)(irq - first_irq);
159}
160
161
163 dt_otp_ctrl_t dt,
164 dt_otp_ctrl_alert_t alert) {
165 return (dt_alert_id_t)((uint32_t)otp_ctrl_desc[dt].first_alert + (uint32_t)alert);
166}
167
169 dt_otp_ctrl_t dt,
170 dt_alert_id_t alert) {
171 dt_otp_ctrl_alert_t count = kDtOtpCtrlAlertCount;
172 if (alert < otp_ctrl_desc[dt].first_alert || alert >= otp_ctrl_desc[dt].first_alert + (dt_alert_id_t)count) {
173 return count;
174 }
175 return (dt_otp_ctrl_alert_t)(alert - otp_ctrl_desc[dt].first_alert);
176}
177
178
179
181 dt_otp_ctrl_t dt,
183 // Return the first clock in case of invalid argument.
184 return TRY_GET_DT(dt, (dt_clock_t)0)->clock[clk];
185}
186
188 dt_otp_ctrl_t dt,
190 const dt_otp_ctrl_reset_t count = kDtOtpCtrlResetCount;
191 if (rst >= count) {
192 return kDtResetUnknown;
193 }
194 return TRY_GET_DT(dt, kDtResetUnknown)->reset[rst];
195}
196
197
198
199
202 dt_otp_partition_info_t invalid_part = {
203 .start_addr = 0xdeadbeef,
204 .size = 0x0,
205 .digest_addr = 0xdeadbeef,
206 .align_mask = 0x0,
207 };
208 return TRY_GET_DT(dt, invalid_part)->sw_readable_partitions.info[partition];
209}
210
211
212