dt_lc_ctrl.c

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// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Device table API auto-generated by `dtgen`
 
/**
 * @file
 * @brief Device Tables (DT) for IP lc_ctrl and top earlgrey.
 */
 
#include "hw/top/dt/dt_lc_ctrl.h"
 
 
 
/**
 * Description of instances.
 */
typedef struct dt_desc_lc_ctrl {
  dt_instance_id_t inst_id; /**< Instance ID */
  uint32_t reg_addr[kDtLcCtrlRegBlockCount]; /**< Base address of each register block */
  uint32_t mem_addr[kDtLcCtrlMemoryCount]; /**< Base address of each memory */
  uint32_t mem_size[kDtLcCtrlMemoryCount]; /**< Size in bytes of each memory */
  /**
   * Alert ID of the first Alert of this instance.
   * 
   * This value is undefined if the block is not connected to the Alert Handler.
   */
  top_earlgrey_alert_id_t first_alert;
  dt_clock_t clock[kDtLcCtrlClockCount]; /**< Clock signal connected to each clock port */
  dt_reset_t reset[kDtLcCtrlResetCount]; /**< Reset signal connected to each reset port */
} dt_desc_lc_ctrl_t;
 
 
 
 
static const dt_desc_lc_ctrl_t lc_ctrl_desc[kDtLcCtrlCount] = {
  [kDtLcCtrl] = {
    .inst_id = kDtInstanceIdLcCtrl,
    .reg_addr = {
      [kDtLcCtrlRegBlockRegs] = 0x40140000,
      [kDtLcCtrlRegBlockDmi] = 0x0,
    },
    .mem_addr = {
    },
    .mem_size = {
    },
    .first_alert = kTopEarlgreyAlertIdLcCtrlFatalProgError,
    .clock = {
      [kDtLcCtrlClockClk] = kDtClockIoDiv4,
      [kDtLcCtrlClockKmac] = kDtClockMain,
    },
    .reset = {
      [kDtLcCtrlResetRst] = kDtResetLcIoDiv4,
      [kDtLcCtrlResetKmac] = kDtResetLc,
    },
  },
};
 
/**
 * Return a pointer to the `dt_lc_ctrl_desc_t` structure of the requested
 * `dt` if it's a valid index. Otherwise, this macro will `return` (i.e. exit
 * the function) with the provided default value.
 */
#define TRY_GET_DT(dt, default)   ({     if ((dt) < (dt_lc_ctrl_t)0 || (dt) >= kDtLcCtrlCount)       return (default);     &lc_ctrl_desc[dt];   })
 
dt_lc_ctrl_t dt_lc_ctrl_from_instance_id(dt_instance_id_t inst_id) {
  if (inst_id >= kDtInstanceIdLcCtrl && inst_id <= kDtInstanceIdLcCtrl) {
    return (dt_lc_ctrl_t)(inst_id - kDtInstanceIdLcCtrl);
  }
  return (dt_lc_ctrl_t)0;
}
 
dt_instance_id_t dt_lc_ctrl_instance_id(
    dt_lc_ctrl_t dt) {
  return TRY_GET_DT(dt, kDtInstanceIdUnknown)->inst_id;
}
 
uint32_t dt_lc_ctrl_reg_block(
    dt_lc_ctrl_t dt,
    dt_lc_ctrl_reg_block_t reg_block) {
  // Return a recognizable address in case of wrong argument.
  return TRY_GET_DT(dt, 0xdeadbeef)->reg_addr[reg_block];
}
 
uint32_t dt_lc_ctrl_memory_base(
    dt_lc_ctrl_t dt,
    dt_lc_ctrl_memory_t mem) {
  // Return a recognizable address in case of wrong argument.
  return TRY_GET_DT(dt, 0xdeadbeef)->mem_addr[mem];
}
 
uint32_t dt_lc_ctrl_memory_size(
    dt_lc_ctrl_t dt,
    dt_lc_ctrl_memory_t mem)  {
  // Return an empty size in case of wrong argument.
  return TRY_GET_DT(dt, 0)->mem_size[mem];
}
 
 
dt_alert_id_t dt_lc_ctrl_alert_to_alert_id(
    dt_lc_ctrl_t dt,
    dt_lc_ctrl_alert_t alert) {
  return (dt_alert_id_t)((uint32_t)lc_ctrl_desc[dt].first_alert + (uint32_t)alert);
}
 
dt_lc_ctrl_alert_t dt_lc_ctrl_alert_from_alert_id(
    dt_lc_ctrl_t dt,
    dt_alert_id_t alert) {
  dt_lc_ctrl_alert_t count = kDtLcCtrlAlertCount;
  if (alert < lc_ctrl_desc[dt].first_alert || alert >= lc_ctrl_desc[dt].first_alert + (dt_alert_id_t)count) {
    return count;
  }
  return (dt_lc_ctrl_alert_t)(alert - lc_ctrl_desc[dt].first_alert);
}
 
 
 
dt_clock_t dt_lc_ctrl_clock(
    dt_lc_ctrl_t dt,
    dt_lc_ctrl_clock_t clk) {
  // Return the first clock in case of invalid argument.
  return TRY_GET_DT(dt, (dt_clock_t)0)->clock[clk];
}
 
dt_reset_t dt_lc_ctrl_reset(
    dt_lc_ctrl_t dt,
    dt_lc_ctrl_reset_t rst) {
  const dt_lc_ctrl_reset_t count = kDtLcCtrlResetCount;
  if (rst >= count) {
    return kDtResetUnknown;
  }
  return TRY_GET_DT(dt, kDtResetUnknown)->reset[rst];
}