Software APIs
dt_gpio.c
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7/**
8 * @file
9 * @brief Device Tables (DT) for IP gpio and top earlgrey.
10 */
11
12#include "hw/top/dt/dt_gpio.h"
13
14
15
16
17
18/**
19 * Description of instances.
20 */
21typedef struct dt_desc_gpio {
22 dt_instance_id_t inst_id; /**< Instance ID */
23 uint32_t reg_addr[kDtGpioRegBlockCount]; /**< Base address of each register block */
24 uint32_t mem_addr[kDtGpioMemoryCount]; /**< Base address of each memory */
25 uint32_t mem_size[kDtGpioMemoryCount]; /**< Size in bytes of each memory */
26 /**
27 * PLIC ID of the first IRQ of this instance
28 *
29 * This can be `kDtPlicIrqIdNone` if the block is not connected to the PLIC.
30 */
31 top_earlgrey_plic_irq_id_t first_irq;
32 /**
33 * Alert ID of the first Alert of this instance.
34 *
35 * This value is undefined if the block is not connected to the Alert Handler.
36 */
37 top_earlgrey_alert_id_t first_alert;
38 dt_clock_t clock[kDtGpioClockCount]; /**< Clock signal connected to each clock port */
39 dt_reset_t reset[kDtGpioResetCount]; /**< Reset signal connected to each reset port */
40 dt_periph_io_t periph_io[kDtGpioPeriphIoCount]; /**< Description of each peripheral I/O */
41 struct {
42 uint8_t input_period_counter_count; /**< number of input period counters */
43 } ipgen_ext; /**< Extension */
44} dt_desc_gpio_t;
45
46
47
48
49static const dt_desc_gpio_t gpio_desc[kDtGpioCount] = {
50 [kDtGpio] = {
51 .inst_id = kDtInstanceIdGpio,
52 .reg_addr = {
53 [kDtGpioRegBlockCore] = 0x40040000,
54 },
55 .mem_addr = {
56 },
57 .mem_size = {
58 },
59 .first_irq = kTopEarlgreyPlicIrqIdGpioGpio0,
60 .first_alert = kTopEarlgreyAlertIdGpioFatalFault,
61 .clock = {
62 [kDtGpioClockClk] = kDtClockIoDiv4,
63 },
64 .reset = {
65 [kDtGpioResetRst] = kDtResetLcIoDiv4,
66 },
67 .periph_io = {
68 [kDtGpioPeriphIoGpio0] = {
69 .__internal = {
70 .type = kDtPeriphIoTypeMio,
71 .dir = kDtPeriphIoDirInout,
72 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio0,
73 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio0,
74 },
75 },
76 [kDtGpioPeriphIoGpio1] = {
77 .__internal = {
78 .type = kDtPeriphIoTypeMio,
79 .dir = kDtPeriphIoDirInout,
80 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio1,
81 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio1,
82 },
83 },
84 [kDtGpioPeriphIoGpio2] = {
85 .__internal = {
86 .type = kDtPeriphIoTypeMio,
87 .dir = kDtPeriphIoDirInout,
88 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio2,
89 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio2,
90 },
91 },
92 [kDtGpioPeriphIoGpio3] = {
93 .__internal = {
94 .type = kDtPeriphIoTypeMio,
95 .dir = kDtPeriphIoDirInout,
96 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio3,
97 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio3,
98 },
99 },
100 [kDtGpioPeriphIoGpio4] = {
101 .__internal = {
102 .type = kDtPeriphIoTypeMio,
103 .dir = kDtPeriphIoDirInout,
104 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio4,
105 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio4,
106 },
107 },
108 [kDtGpioPeriphIoGpio5] = {
109 .__internal = {
110 .type = kDtPeriphIoTypeMio,
111 .dir = kDtPeriphIoDirInout,
112 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio5,
113 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio5,
114 },
115 },
116 [kDtGpioPeriphIoGpio6] = {
117 .__internal = {
118 .type = kDtPeriphIoTypeMio,
119 .dir = kDtPeriphIoDirInout,
120 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio6,
121 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio6,
122 },
123 },
124 [kDtGpioPeriphIoGpio7] = {
125 .__internal = {
126 .type = kDtPeriphIoTypeMio,
127 .dir = kDtPeriphIoDirInout,
128 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio7,
129 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio7,
130 },
131 },
132 [kDtGpioPeriphIoGpio8] = {
133 .__internal = {
134 .type = kDtPeriphIoTypeMio,
135 .dir = kDtPeriphIoDirInout,
136 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio8,
137 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio8,
138 },
139 },
140 [kDtGpioPeriphIoGpio9] = {
141 .__internal = {
142 .type = kDtPeriphIoTypeMio,
143 .dir = kDtPeriphIoDirInout,
144 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio9,
145 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio9,
146 },
147 },
148 [kDtGpioPeriphIoGpio10] = {
149 .__internal = {
150 .type = kDtPeriphIoTypeMio,
151 .dir = kDtPeriphIoDirInout,
152 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio10,
153 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio10,
154 },
155 },
156 [kDtGpioPeriphIoGpio11] = {
157 .__internal = {
158 .type = kDtPeriphIoTypeMio,
159 .dir = kDtPeriphIoDirInout,
160 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio11,
161 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio11,
162 },
163 },
164 [kDtGpioPeriphIoGpio12] = {
165 .__internal = {
166 .type = kDtPeriphIoTypeMio,
167 .dir = kDtPeriphIoDirInout,
168 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio12,
169 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio12,
170 },
171 },
172 [kDtGpioPeriphIoGpio13] = {
173 .__internal = {
174 .type = kDtPeriphIoTypeMio,
175 .dir = kDtPeriphIoDirInout,
176 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio13,
177 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio13,
178 },
179 },
180 [kDtGpioPeriphIoGpio14] = {
181 .__internal = {
182 .type = kDtPeriphIoTypeMio,
183 .dir = kDtPeriphIoDirInout,
184 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio14,
185 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio14,
186 },
187 },
188 [kDtGpioPeriphIoGpio15] = {
189 .__internal = {
190 .type = kDtPeriphIoTypeMio,
191 .dir = kDtPeriphIoDirInout,
192 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio15,
193 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio15,
194 },
195 },
196 [kDtGpioPeriphIoGpio16] = {
197 .__internal = {
198 .type = kDtPeriphIoTypeMio,
199 .dir = kDtPeriphIoDirInout,
200 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio16,
201 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio16,
202 },
203 },
204 [kDtGpioPeriphIoGpio17] = {
205 .__internal = {
206 .type = kDtPeriphIoTypeMio,
207 .dir = kDtPeriphIoDirInout,
208 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio17,
209 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio17,
210 },
211 },
212 [kDtGpioPeriphIoGpio18] = {
213 .__internal = {
214 .type = kDtPeriphIoTypeMio,
215 .dir = kDtPeriphIoDirInout,
216 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio18,
217 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio18,
218 },
219 },
220 [kDtGpioPeriphIoGpio19] = {
221 .__internal = {
222 .type = kDtPeriphIoTypeMio,
223 .dir = kDtPeriphIoDirInout,
224 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio19,
225 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio19,
226 },
227 },
228 [kDtGpioPeriphIoGpio20] = {
229 .__internal = {
230 .type = kDtPeriphIoTypeMio,
231 .dir = kDtPeriphIoDirInout,
232 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio20,
233 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio20,
234 },
235 },
236 [kDtGpioPeriphIoGpio21] = {
237 .__internal = {
238 .type = kDtPeriphIoTypeMio,
239 .dir = kDtPeriphIoDirInout,
240 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio21,
241 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio21,
242 },
243 },
244 [kDtGpioPeriphIoGpio22] = {
245 .__internal = {
246 .type = kDtPeriphIoTypeMio,
247 .dir = kDtPeriphIoDirInout,
248 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio22,
249 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio22,
250 },
251 },
252 [kDtGpioPeriphIoGpio23] = {
253 .__internal = {
254 .type = kDtPeriphIoTypeMio,
255 .dir = kDtPeriphIoDirInout,
256 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio23,
257 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio23,
258 },
259 },
260 [kDtGpioPeriphIoGpio24] = {
261 .__internal = {
262 .type = kDtPeriphIoTypeMio,
263 .dir = kDtPeriphIoDirInout,
264 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio24,
265 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio24,
266 },
267 },
268 [kDtGpioPeriphIoGpio25] = {
269 .__internal = {
270 .type = kDtPeriphIoTypeMio,
271 .dir = kDtPeriphIoDirInout,
272 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio25,
273 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio25,
274 },
275 },
276 [kDtGpioPeriphIoGpio26] = {
277 .__internal = {
278 .type = kDtPeriphIoTypeMio,
279 .dir = kDtPeriphIoDirInout,
280 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio26,
281 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio26,
282 },
283 },
284 [kDtGpioPeriphIoGpio27] = {
285 .__internal = {
286 .type = kDtPeriphIoTypeMio,
287 .dir = kDtPeriphIoDirInout,
288 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio27,
289 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio27,
290 },
291 },
292 [kDtGpioPeriphIoGpio28] = {
293 .__internal = {
294 .type = kDtPeriphIoTypeMio,
295 .dir = kDtPeriphIoDirInout,
296 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio28,
297 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio28,
298 },
299 },
300 [kDtGpioPeriphIoGpio29] = {
301 .__internal = {
302 .type = kDtPeriphIoTypeMio,
303 .dir = kDtPeriphIoDirInout,
304 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio29,
305 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio29,
306 },
307 },
308 [kDtGpioPeriphIoGpio30] = {
309 .__internal = {
310 .type = kDtPeriphIoTypeMio,
311 .dir = kDtPeriphIoDirInout,
312 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio30,
313 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio30,
314 },
315 },
316 [kDtGpioPeriphIoGpio31] = {
317 .__internal = {
318 .type = kDtPeriphIoTypeMio,
319 .dir = kDtPeriphIoDirInout,
320 .periph_input_or_direct_pad = kTopEarlgreyPinmuxPeripheralInGpioGpio31,
321 .outsel_or_dt_pad = kTopEarlgreyPinmuxOutselGpioGpio31,
322 },
323 },
324 },
325 .ipgen_ext = {
326 .input_period_counter_count = 0,
327 },
328 },
329};
330
331/**
332 * Return a pointer to the `dt_gpio_desc_t` structure of the requested
333 * `dt` if it's a valid index. Otherwise, this macro will `return` (i.e. exit
334 * the function) with the provided default value.
335 */
336#define TRY_GET_DT(dt, default) ({ if ((dt) < (dt_gpio_t)0 || (dt) >= kDtGpioCount) return (default); &gpio_desc[dt]; })
337
338dt_gpio_t dt_gpio_from_instance_id(dt_instance_id_t inst_id) {
339 if (inst_id >= kDtInstanceIdGpio && inst_id <= kDtInstanceIdGpio) {
340 return (dt_gpio_t)(inst_id - kDtInstanceIdGpio);
341 }
342 return (dt_gpio_t)0;
343}
344
349
350uint32_t dt_gpio_reg_block(
351 dt_gpio_t dt,
352 dt_gpio_reg_block_t reg_block) {
353 // Return a recognizable address in case of wrong argument.
354 return TRY_GET_DT(dt, 0xdeadbeef)->reg_addr[reg_block];
355}
356
357uint32_t dt_gpio_memory_base(
358 dt_gpio_t dt,
359 dt_gpio_memory_t mem) {
360 // Return a recognizable address in case of wrong argument.
361 return TRY_GET_DT(dt, 0xdeadbeef)->mem_addr[mem];
362}
363
364uint32_t dt_gpio_memory_size(
365 dt_gpio_t dt,
366 dt_gpio_memory_t mem) {
367 // Return an empty size in case of wrong argument.
368 return TRY_GET_DT(dt, 0)->mem_size[mem];
369}
370
371dt_plic_irq_id_t dt_gpio_irq_to_plic_id(
372 dt_gpio_t dt,
373 dt_gpio_irq_t irq) {
374 dt_plic_irq_id_t first_irq = TRY_GET_DT(dt, kDtPlicIrqIdNone)->first_irq;
375 if (first_irq == kDtPlicIrqIdNone) {
376 return kDtPlicIrqIdNone;
377 }
378 return (dt_plic_irq_id_t)((uint32_t)first_irq + (uint32_t)irq);
379}
380
381dt_gpio_irq_t dt_gpio_irq_from_plic_id(
382 dt_gpio_t dt,
383 dt_plic_irq_id_t irq) {
384 dt_gpio_irq_t count = kDtGpioIrqCount;
385 dt_plic_irq_id_t first_irq = TRY_GET_DT(dt, count)->first_irq;
386 if (first_irq == kDtPlicIrqIdNone) {
387 return count;
388 }
389 if (irq < first_irq || irq >= first_irq + (dt_plic_irq_id_t)count) {
390 return count;
391 }
392 return (dt_gpio_irq_t)(irq - first_irq);
393}
394
395
396dt_alert_id_t dt_gpio_alert_to_alert_id(
397 dt_gpio_t dt,
398 dt_gpio_alert_t alert) {
399 return (dt_alert_id_t)((uint32_t)gpio_desc[dt].first_alert + (uint32_t)alert);
400}
401
402dt_gpio_alert_t dt_gpio_alert_from_alert_id(
403 dt_gpio_t dt,
404 dt_alert_id_t alert) {
405 dt_gpio_alert_t count = kDtGpioAlertCount;
406 if (alert < gpio_desc[dt].first_alert || alert >= gpio_desc[dt].first_alert + (dt_alert_id_t)count) {
407 return count;
408 }
409 return (dt_gpio_alert_t)(alert - gpio_desc[dt].first_alert);
410}
411
412
413dt_periph_io_t dt_gpio_periph_io(
414 dt_gpio_t dt,
415 dt_gpio_periph_io_t sig) {
416 // Return a harmless value in case of wrong argument.
417 return TRY_GET_DT(dt, kDtPeriphIoConstantHighZ)->periph_io[sig];
418}
419
420dt_clock_t dt_gpio_clock(
421 dt_gpio_t dt,
422 dt_gpio_clock_t clk) {
423 // Return the first clock in case of invalid argument.
424 return TRY_GET_DT(dt, (dt_clock_t)0)->clock[clk];
425}
426
427dt_reset_t dt_gpio_reset(
428 dt_gpio_t dt,
429 dt_gpio_reset_t rst) {
430 const dt_gpio_reset_t count = kDtGpioResetCount;
431 if (rst >= count) {
432 return kDtResetUnknown;
433 }
434 return TRY_GET_DT(dt, kDtResetUnknown)->reset[rst];
435}
436
437
438
439uint8_t dt_gpio_input_period_counter_count(dt_gpio_t dt) {
440 return TRY_GET_DT(dt, 0)->ipgen_ext.input_period_counter_count;
441}
442
443