dt_csrng.c

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// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Device table API auto-generated by `dtgen`
 
/**
 * @file
 * @brief Device Tables (DT) for IP csrng and top earlgrey.
 */
 
#include "hw/top/dt/dt_csrng.h"
 
 
 
/**
 * Description of instances.
 */
typedef struct dt_desc_csrng {
  dt_instance_id_t inst_id; /**< Instance ID */
  uint32_t reg_addr[kDtCsrngRegBlockCount]; /**< Base address of each register block */
  uint32_t mem_addr[kDtCsrngMemoryCount]; /**< Base address of each memory */
  uint32_t mem_size[kDtCsrngMemoryCount]; /**< Size in bytes of each memory */
  /**
   * PLIC ID of the first IRQ of this instance
   * 
   * This can be `kDtPlicIrqIdNone` if the block is not connected to the PLIC.
   */
  top_earlgrey_plic_irq_id_t first_irq;
  /**
   * Alert ID of the first Alert of this instance.
   * 
   * This value is undefined if the block is not connected to the Alert Handler.
   */
  top_earlgrey_alert_id_t first_alert;
  dt_clock_t clock[kDtCsrngClockCount]; /**< Clock signal connected to each clock port */
  dt_reset_t reset[kDtCsrngResetCount]; /**< Reset signal connected to each reset port */
} dt_desc_csrng_t;
 
 
 
 
static const dt_desc_csrng_t csrng_desc[kDtCsrngCount] = {
  [kDtCsrng] = {
    .inst_id = kDtInstanceIdCsrng,
    .reg_addr = {
      [kDtCsrngRegBlockCore] = 0x41150000,
    },
    .mem_addr = {
    },
    .mem_size = {
    },
    .first_irq = kTopEarlgreyPlicIrqIdCsrngCsCmdReqDone,
    .first_alert = kTopEarlgreyAlertIdCsrngRecovAlert,
    .clock = {
      [kDtCsrngClockClk] = kDtClockMain,
    },
    .reset = {
      [kDtCsrngResetRst] = kDtResetLc,
    },
  },
};
 
/**
 * Return a pointer to the `dt_csrng_desc_t` structure of the requested
 * `dt` if it's a valid index. Otherwise, this macro will `return` (i.e. exit
 * the function) with the provided default value.
 */
#define TRY_GET_DT(dt, default)   ({     if ((dt) < (dt_csrng_t)0 || (dt) >= kDtCsrngCount)       return (default);     &csrng_desc[dt];   })
 
dt_csrng_t dt_csrng_from_instance_id(dt_instance_id_t inst_id) {
  if (inst_id >= kDtInstanceIdCsrng && inst_id <= kDtInstanceIdCsrng) {
    return (dt_csrng_t)(inst_id - kDtInstanceIdCsrng);
  }
  return (dt_csrng_t)0;
}
 
dt_instance_id_t dt_csrng_instance_id(
    dt_csrng_t dt) {
  return TRY_GET_DT(dt, kDtInstanceIdUnknown)->inst_id;
}
 
uint32_t dt_csrng_reg_block(
    dt_csrng_t dt,
    dt_csrng_reg_block_t reg_block) {
  // Return a recognizable address in case of wrong argument.
  return TRY_GET_DT(dt, 0xdeadbeef)->reg_addr[reg_block];
}
 
uint32_t dt_csrng_memory_base(
    dt_csrng_t dt,
    dt_csrng_memory_t mem) {
  // Return a recognizable address in case of wrong argument.
  return TRY_GET_DT(dt, 0xdeadbeef)->mem_addr[mem];
}
 
uint32_t dt_csrng_memory_size(
    dt_csrng_t dt,
    dt_csrng_memory_t mem)  {
  // Return an empty size in case of wrong argument.
  return TRY_GET_DT(dt, 0)->mem_size[mem];
}
 
dt_plic_irq_id_t dt_csrng_irq_to_plic_id(
    dt_csrng_t dt,
    dt_csrng_irq_t irq) {
  dt_plic_irq_id_t first_irq = TRY_GET_DT(dt, kDtPlicIrqIdNone)->first_irq;
  if (first_irq == kDtPlicIrqIdNone) {
    return kDtPlicIrqIdNone;
  }
  return (dt_plic_irq_id_t)((uint32_t)first_irq + (uint32_t)irq);
}
 
dt_csrng_irq_t dt_csrng_irq_from_plic_id(
    dt_csrng_t dt,
    dt_plic_irq_id_t irq) {
  dt_csrng_irq_t count = kDtCsrngIrqCount;
  dt_plic_irq_id_t first_irq = TRY_GET_DT(dt, count)->first_irq;
  if (first_irq == kDtPlicIrqIdNone) {
    return count;
  }
  if (irq < first_irq || irq >= first_irq + (dt_plic_irq_id_t)count) {
    return count;
  }
  return (dt_csrng_irq_t)(irq - first_irq);
}
 
 
dt_alert_id_t dt_csrng_alert_to_alert_id(
    dt_csrng_t dt,
    dt_csrng_alert_t alert) {
  return (dt_alert_id_t)((uint32_t)csrng_desc[dt].first_alert + (uint32_t)alert);
}
 
dt_csrng_alert_t dt_csrng_alert_from_alert_id(
    dt_csrng_t dt,
    dt_alert_id_t alert) {
  dt_csrng_alert_t count = kDtCsrngAlertCount;
  if (alert < csrng_desc[dt].first_alert || alert >= csrng_desc[dt].first_alert + (dt_alert_id_t)count) {
    return count;
  }
  return (dt_csrng_alert_t)(alert - csrng_desc[dt].first_alert);
}
 
 
 
dt_clock_t dt_csrng_clock(
    dt_csrng_t dt,
    dt_csrng_clock_t clk) {
  // Return the first clock in case of invalid argument.
  return TRY_GET_DT(dt, (dt_clock_t)0)->clock[clk];
}
 
dt_reset_t dt_csrng_reset(
    dt_csrng_t dt,
    dt_csrng_reset_t rst) {
  const dt_csrng_reset_t count = kDtCsrngResetCount;
  if (rst >= count) {
    return kDtResetUnknown;
  }
  return TRY_GET_DT(dt, kDtResetUnknown)->reset[rst];
}