Software APIs
dt_clkmgr.c
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7/**
8 * @file
9 * @brief Device Tables (DT) for IP clkmgr and top earlgrey.
10 */
11
12#include "dt/dt_clkmgr.h"
13
14
15#include "clkmgr_regs.h"
16
17
18/**
19 * Description of instances.
20 */
21typedef struct dt_desc_clkmgr {
22 dt_instance_id_t inst_id; /**< Instance ID */
23 uint32_t base_addr[kDtClkmgrRegBlockCount]; /**< Base address of each register block */
24 /**
25 * Alert ID of the first Alert of this instance.
26 *
27 * This value is undefined if the block is not connected to the Alert Handler.
28 */
30 dt_clock_t clock[kDtClkmgrClockCount]; /**< Clock signal connected to each clock port */
31 dt_reset_t reset[kDtClkmgrResetCount]; /**< Reset signal connected to each reset port */
32 struct {
33 dt_instance_id_t sw_clks[4]; /**< List of gateable clocks, in the order of the register fields */
34 dt_instance_id_t hint_clks[4]; /**< List of hintable clocks, in the order of the register fields */
35 dt_clkmgr_measurable_clk_t measurable_clks[5]; /**< List of measurables clocks */
36 } clkmgr_ext; /**< Extension */
38
39
40
41
42static const dt_desc_clkmgr_t clkmgr_desc[kDtClkmgrCount] = {
43 [kDtClkmgrAon] = {
44 .inst_id = kDtInstanceIdClkmgrAon,
45 .base_addr = {
46 [kDtClkmgrRegBlockCore] = 0x40420000,
47 },
49 .clock = {
55 },
56 .reset = {
70 },
71 .clkmgr_ext = {
72 .sw_clks = {
77 },
78 .hint_clks = {
79 [0] = kDtInstanceIdAes,
83 },
84 .measurable_clks = {
85 [0] = {
86 .clock = kDtClockIo,
87 .meas_ctrl_en_off = CLKMGR_IO_MEAS_CTRL_EN_REG_OFFSET,
88 .meas_ctrl_en_en_field = CLKMGR_IO_MEAS_CTRL_EN_EN_FIELD,
89 .meas_ctrl_shadowed_off = CLKMGR_IO_MEAS_CTRL_SHADOWED_REG_OFFSET,
90 .meas_ctrl_shadowed_lo_field = CLKMGR_IO_MEAS_CTRL_SHADOWED_LO_FIELD,
91 .meas_ctrl_shadowed_hi_field = CLKMGR_IO_MEAS_CTRL_SHADOWED_HI_FIELD,
92 },
93 [1] = {
94 .clock = kDtClockIoDiv2,
95 .meas_ctrl_en_off = CLKMGR_IO_DIV2_MEAS_CTRL_EN_REG_OFFSET,
96 .meas_ctrl_en_en_field = CLKMGR_IO_DIV2_MEAS_CTRL_EN_EN_FIELD,
97 .meas_ctrl_shadowed_off = CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_REG_OFFSET,
98 .meas_ctrl_shadowed_lo_field = CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_LO_FIELD,
99 .meas_ctrl_shadowed_hi_field = CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_HI_FIELD,
100 },
101 [2] = {
102 .clock = kDtClockIoDiv4,
103 .meas_ctrl_en_off = CLKMGR_IO_DIV4_MEAS_CTRL_EN_REG_OFFSET,
104 .meas_ctrl_en_en_field = CLKMGR_IO_DIV4_MEAS_CTRL_EN_EN_FIELD,
105 .meas_ctrl_shadowed_off = CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_REG_OFFSET,
106 .meas_ctrl_shadowed_lo_field = CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_LO_FIELD,
107 .meas_ctrl_shadowed_hi_field = CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_HI_FIELD,
108 },
109 [3] = {
110 .clock = kDtClockMain,
111 .meas_ctrl_en_off = CLKMGR_MAIN_MEAS_CTRL_EN_REG_OFFSET,
112 .meas_ctrl_en_en_field = CLKMGR_MAIN_MEAS_CTRL_EN_EN_FIELD,
113 .meas_ctrl_shadowed_off = CLKMGR_MAIN_MEAS_CTRL_SHADOWED_REG_OFFSET,
114 .meas_ctrl_shadowed_lo_field = CLKMGR_MAIN_MEAS_CTRL_SHADOWED_LO_FIELD,
115 .meas_ctrl_shadowed_hi_field = CLKMGR_MAIN_MEAS_CTRL_SHADOWED_HI_FIELD,
116 },
117 [4] = {
118 .clock = kDtClockUsb,
119 .meas_ctrl_en_off = CLKMGR_USB_MEAS_CTRL_EN_REG_OFFSET,
120 .meas_ctrl_en_en_field = CLKMGR_USB_MEAS_CTRL_EN_EN_FIELD,
121 .meas_ctrl_shadowed_off = CLKMGR_USB_MEAS_CTRL_SHADOWED_REG_OFFSET,
122 .meas_ctrl_shadowed_lo_field = CLKMGR_USB_MEAS_CTRL_SHADOWED_LO_FIELD,
123 .meas_ctrl_shadowed_hi_field = CLKMGR_USB_MEAS_CTRL_SHADOWED_HI_FIELD,
124 },
125 },
126 },
127 },
128};
129
130/**
131 * Return a pointer to the `dt_clkmgr_desc_t` structure of the requested
132 * `dt` if it's a valid index. Otherwise, this macro will `return` (i.e. exit
133 * the function) with the provided default value.
134 */
135#define TRY_GET_DT(dt, default) ({ if ((dt) < (dt_clkmgr_t)0 || (dt) >= kDtClkmgrCount) return (default); &clkmgr_desc[dt]; })
136
138 if (inst_id >= kDtInstanceIdClkmgrAon && inst_id <= kDtInstanceIdClkmgrAon) {
139 return (dt_clkmgr_t)(inst_id - kDtInstanceIdClkmgrAon);
140 }
141 return (dt_clkmgr_t)0;
142}
143
148
150 dt_clkmgr_t dt,
151 dt_clkmgr_reg_block_t reg_block) {
152 // Return a recognizable address in case of wrong argument.
153 return TRY_GET_DT(dt, 0xdeadbeef)->base_addr[reg_block];
154}
155
156
158 dt_clkmgr_t dt,
159 dt_clkmgr_alert_t alert) {
160 return (dt_alert_id_t)((uint32_t)clkmgr_desc[dt].first_alert + (uint32_t)alert);
161}
162
164 dt_clkmgr_t dt,
165 dt_alert_id_t alert) {
166 dt_clkmgr_alert_t count = kDtClkmgrAlertCount;
167 if (alert < clkmgr_desc[dt].first_alert || alert >= clkmgr_desc[dt].first_alert + (dt_alert_id_t)count) {
168 return count;
169 }
170 return (dt_clkmgr_alert_t)(alert - clkmgr_desc[dt].first_alert);
171}
172
173
174
176 dt_clkmgr_t dt,
177 dt_clkmgr_clock_t clk) {
178 // Return the first clock in case of invalid argument.
179 return TRY_GET_DT(dt, (dt_clock_t)0)->clock[clk];
180}
181
183 dt_clkmgr_t dt,
184 dt_clkmgr_reset_t rst) {
185 const dt_clkmgr_reset_t count = kDtClkmgrResetCount;
186 if (rst >= count) {
187 return kDtResetUnknown;
188 }
189 return TRY_GET_DT(dt, kDtResetUnknown)->reset[rst];
190}
191
192
193
195 return 4;
196}
197
199 return TRY_GET_DT(dt, kDtInstanceIdUnknown)->clkmgr_ext.sw_clks[idx];
200}
201
203 return 4;
204}
205
207 return TRY_GET_DT(dt, kDtInstanceIdUnknown)->clkmgr_ext.hint_clks[idx];
208}
209
211 return 5;
212}
213
215 dt_clkmgr_measurable_clk_t invalid_clk = {
216 .clock = kDtClockCount,
217 .meas_ctrl_en_off = 0xdead,
218 .meas_ctrl_en_en_field = ((bitfield_field32_t) { .mask = 0, .index = 0 }),
219 .meas_ctrl_shadowed_off = 0xdead,
220 .meas_ctrl_shadowed_lo_field = ((bitfield_field32_t) { .mask = 0, .index = 0 }),
221 .meas_ctrl_shadowed_hi_field = ((bitfield_field32_t) { .mask = 0, .index = 0 }),
222 };
223 return TRY_GET_DT(dt, invalid_clk)->clkmgr_ext.measurable_clks[idx];
224}
225
226