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Software APIs
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Software APIs
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Generated register defines for aes. More...
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Generated register defines for aes.
Definition in file aes_regs.h.
| #define AES_ALERT_TEST_FATAL_FAULT_BIT 1 |
Definition at line 38 of file aes_regs.h.
| #define AES_ALERT_TEST_RECOV_CTRL_UPDATE_ERR_BIT 0 |
Definition at line 37 of file aes_regs.h.
| #define AES_ALERT_TEST_REG_OFFSET 0x0 |
Definition at line 35 of file aes_regs.h.
| #define AES_ALERT_TEST_REG_RESVAL 0x0u |
Definition at line 36 of file aes_regs.h.
| #define AES_CTRL_AUX_REGWEN_CTRL_AUX_REGWEN_BIT 0 |
Definition at line 217 of file aes_regs.h.
| #define AES_CTRL_AUX_REGWEN_REG_OFFSET 0x7c |
Definition at line 215 of file aes_regs.h.
| #define AES_CTRL_AUX_REGWEN_REG_RESVAL 0x1u |
Definition at line 216 of file aes_regs.h.
| #define AES_CTRL_AUX_SHADOWED_FORCE_MASKS_BIT 1 |
Definition at line 212 of file aes_regs.h.
| #define AES_CTRL_AUX_SHADOWED_KEY_TOUCH_FORCES_RESEED_BIT 0 |
Definition at line 211 of file aes_regs.h.
| #define AES_CTRL_AUX_SHADOWED_REG_OFFSET 0x78 |
Definition at line 209 of file aes_regs.h.
| #define AES_CTRL_AUX_SHADOWED_REG_RESVAL 0x1u |
Definition at line 210 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_KEY_LEN_FIELD ((bitfield_field32_t) { .mask = AES_CTRL_SHADOWED_KEY_LEN_MASK, .index = AES_CTRL_SHADOWED_KEY_LEN_OFFSET }) |
Definition at line 193 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_KEY_LEN_MASK 0x7u |
Definition at line 191 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_KEY_LEN_OFFSET 8 |
Definition at line 192 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_KEY_LEN_VALUE_AES_128 0x1 |
Definition at line 195 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_KEY_LEN_VALUE_AES_192 0x2 |
Definition at line 196 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_KEY_LEN_VALUE_AES_256 0x4 |
Definition at line 197 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_MANUAL_OPERATION_BIT 15 |
Definition at line 206 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_MODE_FIELD ((bitfield_field32_t) { .mask = AES_CTRL_SHADOWED_MODE_MASK, .index = AES_CTRL_SHADOWED_MODE_OFFSET }) |
Definition at line 183 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_MODE_MASK 0x3fu |
Definition at line 181 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_MODE_OFFSET 2 |
Definition at line 182 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_MODE_VALUE_AES_CBC 0x2 |
Definition at line 186 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_MODE_VALUE_AES_CFB 0x4 |
Definition at line 187 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_MODE_VALUE_AES_CTR 0x10 |
Definition at line 189 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_MODE_VALUE_AES_ECB 0x1 |
Definition at line 185 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_MODE_VALUE_AES_NONE 0x20 |
Definition at line 190 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_MODE_VALUE_AES_OFB 0x8 |
Definition at line 188 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_OPERATION_FIELD ((bitfield_field32_t) { .mask = AES_CTRL_SHADOWED_OPERATION_MASK, .index = AES_CTRL_SHADOWED_OPERATION_OFFSET }) |
Definition at line 177 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_OPERATION_MASK 0x3u |
Definition at line 175 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_OPERATION_OFFSET 0 |
Definition at line 176 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_OPERATION_VALUE_AES_DEC 0x2 |
Definition at line 180 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_OPERATION_VALUE_AES_ENC 0x1 |
Definition at line 179 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_PRNG_RESEED_RATE_FIELD ((bitfield_field32_t) { .mask = AES_CTRL_SHADOWED_PRNG_RESEED_RATE_MASK, .index = AES_CTRL_SHADOWED_PRNG_RESEED_RATE_OFFSET }) |
Definition at line 201 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_PRNG_RESEED_RATE_MASK 0x7u |
Definition at line 199 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_PRNG_RESEED_RATE_OFFSET 12 |
Definition at line 200 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_PRNG_RESEED_RATE_VALUE_PER_1 0x1 |
Definition at line 203 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_PRNG_RESEED_RATE_VALUE_PER_64 0x2 |
Definition at line 204 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_PRNG_RESEED_RATE_VALUE_PER_8K 0x4 |
Definition at line 205 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_REG_OFFSET 0x74 |
Definition at line 173 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_REG_RESVAL 0x1181u |
Definition at line 174 of file aes_regs.h.
| #define AES_CTRL_SHADOWED_SIDELOAD_BIT 11 |
Definition at line 198 of file aes_regs.h.
| #define AES_DATA_IN_0_REG_OFFSET 0x54 |
Definition at line 137 of file aes_regs.h.
| #define AES_DATA_IN_0_REG_RESVAL 0x0u |
Definition at line 138 of file aes_regs.h.
| #define AES_DATA_IN_1_REG_OFFSET 0x58 |
Definition at line 141 of file aes_regs.h.
| #define AES_DATA_IN_1_REG_RESVAL 0x0u |
Definition at line 142 of file aes_regs.h.
| #define AES_DATA_IN_2_REG_OFFSET 0x5c |
Definition at line 145 of file aes_regs.h.
| #define AES_DATA_IN_2_REG_RESVAL 0x0u |
Definition at line 146 of file aes_regs.h.
| #define AES_DATA_IN_3_REG_OFFSET 0x60 |
Definition at line 149 of file aes_regs.h.
| #define AES_DATA_IN_3_REG_RESVAL 0x0u |
Definition at line 150 of file aes_regs.h.
| #define AES_DATA_IN_DATA_IN_FIELD_WIDTH 32 |
Definition at line 133 of file aes_regs.h.
| #define AES_DATA_IN_MULTIREG_COUNT 4 |
Definition at line 134 of file aes_regs.h.
| #define AES_DATA_OUT_0_REG_OFFSET 0x64 |
Definition at line 157 of file aes_regs.h.
| #define AES_DATA_OUT_0_REG_RESVAL 0x0u |
Definition at line 158 of file aes_regs.h.
| #define AES_DATA_OUT_1_REG_OFFSET 0x68 |
Definition at line 161 of file aes_regs.h.
| #define AES_DATA_OUT_1_REG_RESVAL 0x0u |
Definition at line 162 of file aes_regs.h.
| #define AES_DATA_OUT_2_REG_OFFSET 0x6c |
Definition at line 165 of file aes_regs.h.
| #define AES_DATA_OUT_2_REG_RESVAL 0x0u |
Definition at line 166 of file aes_regs.h.
| #define AES_DATA_OUT_3_REG_OFFSET 0x70 |
Definition at line 169 of file aes_regs.h.
| #define AES_DATA_OUT_3_REG_RESVAL 0x0u |
Definition at line 170 of file aes_regs.h.
| #define AES_DATA_OUT_DATA_OUT_FIELD_WIDTH 32 |
Definition at line 153 of file aes_regs.h.
| #define AES_DATA_OUT_MULTIREG_COUNT 4 |
Definition at line 154 of file aes_regs.h.
| #define AES_IV_0_REG_OFFSET 0x44 |
Definition at line 117 of file aes_regs.h.
| #define AES_IV_0_REG_RESVAL 0x0u |
Definition at line 118 of file aes_regs.h.
| #define AES_IV_1_REG_OFFSET 0x48 |
Definition at line 121 of file aes_regs.h.
| #define AES_IV_1_REG_RESVAL 0x0u |
Definition at line 122 of file aes_regs.h.
| #define AES_IV_2_REG_OFFSET 0x4c |
Definition at line 125 of file aes_regs.h.
| #define AES_IV_2_REG_RESVAL 0x0u |
Definition at line 126 of file aes_regs.h.
| #define AES_IV_3_REG_OFFSET 0x50 |
Definition at line 129 of file aes_regs.h.
| #define AES_IV_3_REG_RESVAL 0x0u |
Definition at line 130 of file aes_regs.h.
| #define AES_IV_IV_FIELD_WIDTH 32 |
Definition at line 113 of file aes_regs.h.
| #define AES_IV_MULTIREG_COUNT 4 |
Definition at line 114 of file aes_regs.h.
| #define AES_KEY_SHARE0_0_REG_OFFSET 0x4 |
Definition at line 45 of file aes_regs.h.
| #define AES_KEY_SHARE0_0_REG_RESVAL 0x0u |
Definition at line 46 of file aes_regs.h.
| #define AES_KEY_SHARE0_1_REG_OFFSET 0x8 |
Definition at line 49 of file aes_regs.h.
| #define AES_KEY_SHARE0_1_REG_RESVAL 0x0u |
Definition at line 50 of file aes_regs.h.
| #define AES_KEY_SHARE0_2_REG_OFFSET 0xc |
Definition at line 53 of file aes_regs.h.
| #define AES_KEY_SHARE0_2_REG_RESVAL 0x0u |
Definition at line 54 of file aes_regs.h.
| #define AES_KEY_SHARE0_3_REG_OFFSET 0x10 |
Definition at line 57 of file aes_regs.h.
| #define AES_KEY_SHARE0_3_REG_RESVAL 0x0u |
Definition at line 58 of file aes_regs.h.
| #define AES_KEY_SHARE0_4_REG_OFFSET 0x14 |
Definition at line 61 of file aes_regs.h.
| #define AES_KEY_SHARE0_4_REG_RESVAL 0x0u |
Definition at line 62 of file aes_regs.h.
| #define AES_KEY_SHARE0_5_REG_OFFSET 0x18 |
Definition at line 65 of file aes_regs.h.
| #define AES_KEY_SHARE0_5_REG_RESVAL 0x0u |
Definition at line 66 of file aes_regs.h.
| #define AES_KEY_SHARE0_6_REG_OFFSET 0x1c |
Definition at line 69 of file aes_regs.h.
| #define AES_KEY_SHARE0_6_REG_RESVAL 0x0u |
Definition at line 70 of file aes_regs.h.
| #define AES_KEY_SHARE0_7_REG_OFFSET 0x20 |
Definition at line 73 of file aes_regs.h.
| #define AES_KEY_SHARE0_7_REG_RESVAL 0x0u |
Definition at line 74 of file aes_regs.h.
| #define AES_KEY_SHARE0_KEY_SHARE0_FIELD_WIDTH 32 |
Definition at line 41 of file aes_regs.h.
| #define AES_KEY_SHARE0_MULTIREG_COUNT 8 |
Definition at line 42 of file aes_regs.h.
| #define AES_KEY_SHARE1_0_REG_OFFSET 0x24 |
Definition at line 81 of file aes_regs.h.
| #define AES_KEY_SHARE1_0_REG_RESVAL 0x0u |
Definition at line 82 of file aes_regs.h.
| #define AES_KEY_SHARE1_1_REG_OFFSET 0x28 |
Definition at line 85 of file aes_regs.h.
| #define AES_KEY_SHARE1_1_REG_RESVAL 0x0u |
Definition at line 86 of file aes_regs.h.
| #define AES_KEY_SHARE1_2_REG_OFFSET 0x2c |
Definition at line 89 of file aes_regs.h.
| #define AES_KEY_SHARE1_2_REG_RESVAL 0x0u |
Definition at line 90 of file aes_regs.h.
| #define AES_KEY_SHARE1_3_REG_OFFSET 0x30 |
Definition at line 93 of file aes_regs.h.
| #define AES_KEY_SHARE1_3_REG_RESVAL 0x0u |
Definition at line 94 of file aes_regs.h.
| #define AES_KEY_SHARE1_4_REG_OFFSET 0x34 |
Definition at line 97 of file aes_regs.h.
| #define AES_KEY_SHARE1_4_REG_RESVAL 0x0u |
Definition at line 98 of file aes_regs.h.
| #define AES_KEY_SHARE1_5_REG_OFFSET 0x38 |
Definition at line 101 of file aes_regs.h.
| #define AES_KEY_SHARE1_5_REG_RESVAL 0x0u |
Definition at line 102 of file aes_regs.h.
| #define AES_KEY_SHARE1_6_REG_OFFSET 0x3c |
Definition at line 105 of file aes_regs.h.
| #define AES_KEY_SHARE1_6_REG_RESVAL 0x0u |
Definition at line 106 of file aes_regs.h.
| #define AES_KEY_SHARE1_7_REG_OFFSET 0x40 |
Definition at line 109 of file aes_regs.h.
| #define AES_KEY_SHARE1_7_REG_RESVAL 0x0u |
Definition at line 110 of file aes_regs.h.
| #define AES_KEY_SHARE1_KEY_SHARE1_FIELD_WIDTH 32 |
Definition at line 77 of file aes_regs.h.
| #define AES_KEY_SHARE1_MULTIREG_COUNT 8 |
Definition at line 78 of file aes_regs.h.
| #define AES_PARAM_NUM_ALERTS 2 |
Definition at line 29 of file aes_regs.h.
| #define AES_PARAM_NUM_REGS_DATA 4 |
Definition at line 26 of file aes_regs.h.
| #define AES_PARAM_NUM_REGS_IV 4 |
Definition at line 23 of file aes_regs.h.
| #define AES_PARAM_NUM_REGS_KEY 8 |
Definition at line 20 of file aes_regs.h.
| #define AES_PARAM_REG_WIDTH 32 |
Definition at line 32 of file aes_regs.h.
| #define AES_STATUS_ALERT_FATAL_FAULT_BIT 6 |
Definition at line 236 of file aes_regs.h.
| #define AES_STATUS_ALERT_RECOV_CTRL_UPDATE_ERR_BIT 5 |
Definition at line 235 of file aes_regs.h.
| #define AES_STATUS_IDLE_BIT 0 |
Definition at line 230 of file aes_regs.h.
| #define AES_STATUS_INPUT_READY_BIT 4 |
Definition at line 234 of file aes_regs.h.
| #define AES_STATUS_OUTPUT_LOST_BIT 2 |
Definition at line 232 of file aes_regs.h.
| #define AES_STATUS_OUTPUT_VALID_BIT 3 |
Definition at line 233 of file aes_regs.h.
| #define AES_STATUS_REG_OFFSET 0x84 |
Definition at line 228 of file aes_regs.h.
| #define AES_STATUS_REG_RESVAL 0x0u |
Definition at line 229 of file aes_regs.h.
| #define AES_STATUS_STALL_BIT 1 |
Definition at line 231 of file aes_regs.h.
| #define AES_TRIGGER_DATA_OUT_CLEAR_BIT 2 |
Definition at line 224 of file aes_regs.h.
| #define AES_TRIGGER_KEY_IV_DATA_IN_CLEAR_BIT 1 |
Definition at line 223 of file aes_regs.h.
| #define AES_TRIGGER_PRNG_RESEED_BIT 3 |
Definition at line 225 of file aes_regs.h.
| #define AES_TRIGGER_REG_OFFSET 0x80 |
Definition at line 220 of file aes_regs.h.
| #define AES_TRIGGER_REG_RESVAL 0xeu |
Definition at line 221 of file aes_regs.h.
| #define AES_TRIGGER_START_BIT 0 |
Definition at line 222 of file aes_regs.h.