Generated register defines for pinmux. More...

Macros
#define	PINMUX_PARAM_N_MIO_PERIPH_IN 4

#define	PINMUX_PARAM_N_MIO_PERIPH_OUT 5

#define	PINMUX_PARAM_N_MIO_PADS 12

#define	PINMUX_PARAM_N_DIO_PADS 73

#define	PINMUX_PARAM_N_WKUP_DETECT 8

#define	PINMUX_PARAM_WKUP_CNT_WIDTH 8

#define	PINMUX_PARAM_NUM_ALERTS 1

#define	PINMUX_PARAM_REG_WIDTH 32

#define	PINMUX_ALERT_TEST_REG_OFFSET 0x0

#define	PINMUX_ALERT_TEST_REG_RESVAL 0x0u

#define	PINMUX_ALERT_TEST_FATAL_FAULT_BIT 0

#define	PINMUX_MIO_PERIPH_INSEL_REGWEN_EN_FIELD_WIDTH 1

#define	PINMUX_MIO_PERIPH_INSEL_REGWEN_MULTIREG_COUNT 4

#define	PINMUX_MIO_PERIPH_INSEL_REGWEN_0_REG_OFFSET 0x4

#define	PINMUX_MIO_PERIPH_INSEL_REGWEN_0_REG_RESVAL 0x1u

#define	PINMUX_MIO_PERIPH_INSEL_REGWEN_0_EN_0_BIT 0

#define	PINMUX_MIO_PERIPH_INSEL_REGWEN_1_REG_OFFSET 0x8

#define	PINMUX_MIO_PERIPH_INSEL_REGWEN_1_REG_RESVAL 0x1u

#define	PINMUX_MIO_PERIPH_INSEL_REGWEN_1_EN_1_BIT 0

#define	PINMUX_MIO_PERIPH_INSEL_REGWEN_2_REG_OFFSET 0xc

#define	PINMUX_MIO_PERIPH_INSEL_REGWEN_2_REG_RESVAL 0x1u

#define	PINMUX_MIO_PERIPH_INSEL_REGWEN_2_EN_2_BIT 0

#define	PINMUX_MIO_PERIPH_INSEL_REGWEN_3_REG_OFFSET 0x10

#define	PINMUX_MIO_PERIPH_INSEL_REGWEN_3_REG_RESVAL 0x1u

#define	PINMUX_MIO_PERIPH_INSEL_REGWEN_3_EN_3_BIT 0

#define	PINMUX_MIO_PERIPH_INSEL_IN_FIELD_WIDTH 4

#define	PINMUX_MIO_PERIPH_INSEL_MULTIREG_COUNT 4

#define	PINMUX_MIO_PERIPH_INSEL_0_REG_OFFSET 0x14

#define	PINMUX_MIO_PERIPH_INSEL_0_REG_RESVAL 0x0u

#define	PINMUX_MIO_PERIPH_INSEL_0_IN_0_MASK 0xfu

#define	PINMUX_MIO_PERIPH_INSEL_0_IN_0_OFFSET 0

#define	PINMUX_MIO_PERIPH_INSEL_0_IN_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_0_IN_0_MASK, .index = PINMUX_MIO_PERIPH_INSEL_0_IN_0_OFFSET })

#define	PINMUX_MIO_PERIPH_INSEL_1_REG_OFFSET 0x18

#define	PINMUX_MIO_PERIPH_INSEL_1_REG_RESVAL 0x0u

#define	PINMUX_MIO_PERIPH_INSEL_1_IN_1_MASK 0xfu

#define	PINMUX_MIO_PERIPH_INSEL_1_IN_1_OFFSET 0

#define	PINMUX_MIO_PERIPH_INSEL_1_IN_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_1_IN_1_MASK, .index = PINMUX_MIO_PERIPH_INSEL_1_IN_1_OFFSET })

#define	PINMUX_MIO_PERIPH_INSEL_2_REG_OFFSET 0x1c

#define	PINMUX_MIO_PERIPH_INSEL_2_REG_RESVAL 0x0u

#define	PINMUX_MIO_PERIPH_INSEL_2_IN_2_MASK 0xfu

#define	PINMUX_MIO_PERIPH_INSEL_2_IN_2_OFFSET 0

#define	PINMUX_MIO_PERIPH_INSEL_2_IN_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_2_IN_2_MASK, .index = PINMUX_MIO_PERIPH_INSEL_2_IN_2_OFFSET })

#define	PINMUX_MIO_PERIPH_INSEL_3_REG_OFFSET 0x20

#define	PINMUX_MIO_PERIPH_INSEL_3_REG_RESVAL 0x0u

#define	PINMUX_MIO_PERIPH_INSEL_3_IN_3_MASK 0xfu

#define	PINMUX_MIO_PERIPH_INSEL_3_IN_3_OFFSET 0

#define	PINMUX_MIO_PERIPH_INSEL_3_IN_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_3_IN_3_MASK, .index = PINMUX_MIO_PERIPH_INSEL_3_IN_3_OFFSET })

#define	PINMUX_MIO_OUTSEL_REGWEN_EN_FIELD_WIDTH 1

#define	PINMUX_MIO_OUTSEL_REGWEN_MULTIREG_COUNT 12

#define	PINMUX_MIO_OUTSEL_REGWEN_0_REG_OFFSET 0x24

#define	PINMUX_MIO_OUTSEL_REGWEN_0_REG_RESVAL 0x1u

#define	PINMUX_MIO_OUTSEL_REGWEN_0_EN_0_BIT 0

#define	PINMUX_MIO_OUTSEL_REGWEN_1_REG_OFFSET 0x28

#define	PINMUX_MIO_OUTSEL_REGWEN_1_REG_RESVAL 0x1u

#define	PINMUX_MIO_OUTSEL_REGWEN_1_EN_1_BIT 0

#define	PINMUX_MIO_OUTSEL_REGWEN_2_REG_OFFSET 0x2c

#define	PINMUX_MIO_OUTSEL_REGWEN_2_REG_RESVAL 0x1u

#define	PINMUX_MIO_OUTSEL_REGWEN_2_EN_2_BIT 0

#define	PINMUX_MIO_OUTSEL_REGWEN_3_REG_OFFSET 0x30

#define	PINMUX_MIO_OUTSEL_REGWEN_3_REG_RESVAL 0x1u

#define	PINMUX_MIO_OUTSEL_REGWEN_3_EN_3_BIT 0

#define	PINMUX_MIO_OUTSEL_REGWEN_4_REG_OFFSET 0x34

#define	PINMUX_MIO_OUTSEL_REGWEN_4_REG_RESVAL 0x1u

#define	PINMUX_MIO_OUTSEL_REGWEN_4_EN_4_BIT 0

#define	PINMUX_MIO_OUTSEL_REGWEN_5_REG_OFFSET 0x38

#define	PINMUX_MIO_OUTSEL_REGWEN_5_REG_RESVAL 0x1u

#define	PINMUX_MIO_OUTSEL_REGWEN_5_EN_5_BIT 0

#define	PINMUX_MIO_OUTSEL_REGWEN_6_REG_OFFSET 0x3c

#define	PINMUX_MIO_OUTSEL_REGWEN_6_REG_RESVAL 0x1u

#define	PINMUX_MIO_OUTSEL_REGWEN_6_EN_6_BIT 0

#define	PINMUX_MIO_OUTSEL_REGWEN_7_REG_OFFSET 0x40

#define	PINMUX_MIO_OUTSEL_REGWEN_7_REG_RESVAL 0x1u

#define	PINMUX_MIO_OUTSEL_REGWEN_7_EN_7_BIT 0

#define	PINMUX_MIO_OUTSEL_REGWEN_8_REG_OFFSET 0x44

#define	PINMUX_MIO_OUTSEL_REGWEN_8_REG_RESVAL 0x1u

#define	PINMUX_MIO_OUTSEL_REGWEN_8_EN_8_BIT 0

#define	PINMUX_MIO_OUTSEL_REGWEN_9_REG_OFFSET 0x48

#define	PINMUX_MIO_OUTSEL_REGWEN_9_REG_RESVAL 0x1u

#define	PINMUX_MIO_OUTSEL_REGWEN_9_EN_9_BIT 0

#define	PINMUX_MIO_OUTSEL_REGWEN_10_REG_OFFSET 0x4c

#define	PINMUX_MIO_OUTSEL_REGWEN_10_REG_RESVAL 0x1u

#define	PINMUX_MIO_OUTSEL_REGWEN_10_EN_10_BIT 0

#define	PINMUX_MIO_OUTSEL_REGWEN_11_REG_OFFSET 0x50

#define	PINMUX_MIO_OUTSEL_REGWEN_11_REG_RESVAL 0x1u

#define	PINMUX_MIO_OUTSEL_REGWEN_11_EN_11_BIT 0

#define	PINMUX_MIO_OUTSEL_OUT_FIELD_WIDTH 3

#define	PINMUX_MIO_OUTSEL_MULTIREG_COUNT 12

#define	PINMUX_MIO_OUTSEL_0_REG_OFFSET 0x54

#define	PINMUX_MIO_OUTSEL_0_REG_RESVAL 0x2u

#define	PINMUX_MIO_OUTSEL_0_OUT_0_MASK 0x7u

#define	PINMUX_MIO_OUTSEL_0_OUT_0_OFFSET 0

#define	PINMUX_MIO_OUTSEL_0_OUT_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_0_OUT_0_MASK, .index = PINMUX_MIO_OUTSEL_0_OUT_0_OFFSET })

#define	PINMUX_MIO_OUTSEL_1_REG_OFFSET 0x58

#define	PINMUX_MIO_OUTSEL_1_REG_RESVAL 0x2u

#define	PINMUX_MIO_OUTSEL_1_OUT_1_MASK 0x7u

#define	PINMUX_MIO_OUTSEL_1_OUT_1_OFFSET 0

#define	PINMUX_MIO_OUTSEL_1_OUT_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_1_OUT_1_MASK, .index = PINMUX_MIO_OUTSEL_1_OUT_1_OFFSET })

#define	PINMUX_MIO_OUTSEL_2_REG_OFFSET 0x5c

#define	PINMUX_MIO_OUTSEL_2_REG_RESVAL 0x2u

#define	PINMUX_MIO_OUTSEL_2_OUT_2_MASK 0x7u

#define	PINMUX_MIO_OUTSEL_2_OUT_2_OFFSET 0

#define	PINMUX_MIO_OUTSEL_2_OUT_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_2_OUT_2_MASK, .index = PINMUX_MIO_OUTSEL_2_OUT_2_OFFSET })

#define	PINMUX_MIO_OUTSEL_3_REG_OFFSET 0x60

#define	PINMUX_MIO_OUTSEL_3_REG_RESVAL 0x2u

#define	PINMUX_MIO_OUTSEL_3_OUT_3_MASK 0x7u

#define	PINMUX_MIO_OUTSEL_3_OUT_3_OFFSET 0

#define	PINMUX_MIO_OUTSEL_3_OUT_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_3_OUT_3_MASK, .index = PINMUX_MIO_OUTSEL_3_OUT_3_OFFSET })

#define	PINMUX_MIO_OUTSEL_4_REG_OFFSET 0x64

#define	PINMUX_MIO_OUTSEL_4_REG_RESVAL 0x2u

#define	PINMUX_MIO_OUTSEL_4_OUT_4_MASK 0x7u

#define	PINMUX_MIO_OUTSEL_4_OUT_4_OFFSET 0

#define	PINMUX_MIO_OUTSEL_4_OUT_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_4_OUT_4_MASK, .index = PINMUX_MIO_OUTSEL_4_OUT_4_OFFSET })

#define	PINMUX_MIO_OUTSEL_5_REG_OFFSET 0x68

#define	PINMUX_MIO_OUTSEL_5_REG_RESVAL 0x2u

#define	PINMUX_MIO_OUTSEL_5_OUT_5_MASK 0x7u

#define	PINMUX_MIO_OUTSEL_5_OUT_5_OFFSET 0

#define	PINMUX_MIO_OUTSEL_5_OUT_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_5_OUT_5_MASK, .index = PINMUX_MIO_OUTSEL_5_OUT_5_OFFSET })

#define	PINMUX_MIO_OUTSEL_6_REG_OFFSET 0x6c

#define	PINMUX_MIO_OUTSEL_6_REG_RESVAL 0x2u

#define	PINMUX_MIO_OUTSEL_6_OUT_6_MASK 0x7u

#define	PINMUX_MIO_OUTSEL_6_OUT_6_OFFSET 0

#define	PINMUX_MIO_OUTSEL_6_OUT_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_6_OUT_6_MASK, .index = PINMUX_MIO_OUTSEL_6_OUT_6_OFFSET })

#define	PINMUX_MIO_OUTSEL_7_REG_OFFSET 0x70

#define	PINMUX_MIO_OUTSEL_7_REG_RESVAL 0x2u

#define	PINMUX_MIO_OUTSEL_7_OUT_7_MASK 0x7u

#define	PINMUX_MIO_OUTSEL_7_OUT_7_OFFSET 0

#define	PINMUX_MIO_OUTSEL_7_OUT_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_7_OUT_7_MASK, .index = PINMUX_MIO_OUTSEL_7_OUT_7_OFFSET })

#define	PINMUX_MIO_OUTSEL_8_REG_OFFSET 0x74

#define	PINMUX_MIO_OUTSEL_8_REG_RESVAL 0x2u

#define	PINMUX_MIO_OUTSEL_8_OUT_8_MASK 0x7u

#define	PINMUX_MIO_OUTSEL_8_OUT_8_OFFSET 0

#define	PINMUX_MIO_OUTSEL_8_OUT_8_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_8_OUT_8_MASK, .index = PINMUX_MIO_OUTSEL_8_OUT_8_OFFSET })

#define	PINMUX_MIO_OUTSEL_9_REG_OFFSET 0x78

#define	PINMUX_MIO_OUTSEL_9_REG_RESVAL 0x2u

#define	PINMUX_MIO_OUTSEL_9_OUT_9_MASK 0x7u

#define	PINMUX_MIO_OUTSEL_9_OUT_9_OFFSET 0

#define	PINMUX_MIO_OUTSEL_9_OUT_9_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_9_OUT_9_MASK, .index = PINMUX_MIO_OUTSEL_9_OUT_9_OFFSET })

#define	PINMUX_MIO_OUTSEL_10_REG_OFFSET 0x7c

#define	PINMUX_MIO_OUTSEL_10_REG_RESVAL 0x2u

#define	PINMUX_MIO_OUTSEL_10_OUT_10_MASK 0x7u

#define	PINMUX_MIO_OUTSEL_10_OUT_10_OFFSET 0

#define	PINMUX_MIO_OUTSEL_10_OUT_10_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_10_OUT_10_MASK, .index = PINMUX_MIO_OUTSEL_10_OUT_10_OFFSET })

#define	PINMUX_MIO_OUTSEL_11_REG_OFFSET 0x80

#define	PINMUX_MIO_OUTSEL_11_REG_RESVAL 0x2u

#define	PINMUX_MIO_OUTSEL_11_OUT_11_MASK 0x7u

#define	PINMUX_MIO_OUTSEL_11_OUT_11_OFFSET 0

#define	PINMUX_MIO_OUTSEL_11_OUT_11_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_11_OUT_11_MASK, .index = PINMUX_MIO_OUTSEL_11_OUT_11_OFFSET })

#define	PINMUX_MIO_PAD_ATTR_REGWEN_EN_FIELD_WIDTH 1

#define	PINMUX_MIO_PAD_ATTR_REGWEN_MULTIREG_COUNT 12

#define	PINMUX_MIO_PAD_ATTR_REGWEN_0_REG_OFFSET 0x84

#define	PINMUX_MIO_PAD_ATTR_REGWEN_0_REG_RESVAL 0x1u

#define	PINMUX_MIO_PAD_ATTR_REGWEN_0_EN_0_BIT 0

#define	PINMUX_MIO_PAD_ATTR_REGWEN_1_REG_OFFSET 0x88

#define	PINMUX_MIO_PAD_ATTR_REGWEN_1_REG_RESVAL 0x1u

#define	PINMUX_MIO_PAD_ATTR_REGWEN_1_EN_1_BIT 0

#define	PINMUX_MIO_PAD_ATTR_REGWEN_2_REG_OFFSET 0x8c

#define	PINMUX_MIO_PAD_ATTR_REGWEN_2_REG_RESVAL 0x1u

#define	PINMUX_MIO_PAD_ATTR_REGWEN_2_EN_2_BIT 0

#define	PINMUX_MIO_PAD_ATTR_REGWEN_3_REG_OFFSET 0x90

#define	PINMUX_MIO_PAD_ATTR_REGWEN_3_REG_RESVAL 0x1u

#define	PINMUX_MIO_PAD_ATTR_REGWEN_3_EN_3_BIT 0

#define	PINMUX_MIO_PAD_ATTR_REGWEN_4_REG_OFFSET 0x94

#define	PINMUX_MIO_PAD_ATTR_REGWEN_4_REG_RESVAL 0x1u

#define	PINMUX_MIO_PAD_ATTR_REGWEN_4_EN_4_BIT 0

#define	PINMUX_MIO_PAD_ATTR_REGWEN_5_REG_OFFSET 0x98

#define	PINMUX_MIO_PAD_ATTR_REGWEN_5_REG_RESVAL 0x1u

#define	PINMUX_MIO_PAD_ATTR_REGWEN_5_EN_5_BIT 0

#define	PINMUX_MIO_PAD_ATTR_REGWEN_6_REG_OFFSET 0x9c

#define	PINMUX_MIO_PAD_ATTR_REGWEN_6_REG_RESVAL 0x1u

#define	PINMUX_MIO_PAD_ATTR_REGWEN_6_EN_6_BIT 0

#define	PINMUX_MIO_PAD_ATTR_REGWEN_7_REG_OFFSET 0xa0

#define	PINMUX_MIO_PAD_ATTR_REGWEN_7_REG_RESVAL 0x1u

#define	PINMUX_MIO_PAD_ATTR_REGWEN_7_EN_7_BIT 0

#define	PINMUX_MIO_PAD_ATTR_REGWEN_8_REG_OFFSET 0xa4

#define	PINMUX_MIO_PAD_ATTR_REGWEN_8_REG_RESVAL 0x1u

#define	PINMUX_MIO_PAD_ATTR_REGWEN_8_EN_8_BIT 0

#define	PINMUX_MIO_PAD_ATTR_REGWEN_9_REG_OFFSET 0xa8

#define	PINMUX_MIO_PAD_ATTR_REGWEN_9_REG_RESVAL 0x1u

#define	PINMUX_MIO_PAD_ATTR_REGWEN_9_EN_9_BIT 0

#define	PINMUX_MIO_PAD_ATTR_REGWEN_10_REG_OFFSET 0xac

#define	PINMUX_MIO_PAD_ATTR_REGWEN_10_REG_RESVAL 0x1u

#define	PINMUX_MIO_PAD_ATTR_REGWEN_10_EN_10_BIT 0

#define	PINMUX_MIO_PAD_ATTR_REGWEN_11_REG_OFFSET 0xb0

#define	PINMUX_MIO_PAD_ATTR_REGWEN_11_REG_RESVAL 0x1u

#define	PINMUX_MIO_PAD_ATTR_REGWEN_11_EN_11_BIT 0

#define	PINMUX_MIO_PAD_ATTR_INVERT_FIELD_WIDTH 1

#define	PINMUX_MIO_PAD_ATTR_VIRTUAL_OD_EN_FIELD_WIDTH 1

#define	PINMUX_MIO_PAD_ATTR_PULL_EN_FIELD_WIDTH 1

#define	PINMUX_MIO_PAD_ATTR_PULL_SELECT_FIELD_WIDTH 1

#define	PINMUX_MIO_PAD_ATTR_KEEPER_EN_FIELD_WIDTH 1

#define	PINMUX_MIO_PAD_ATTR_SCHMITT_EN_FIELD_WIDTH 1

#define	PINMUX_MIO_PAD_ATTR_OD_EN_FIELD_WIDTH 1

#define	PINMUX_MIO_PAD_ATTR_INPUT_DISABLE_FIELD_WIDTH 1

#define	PINMUX_MIO_PAD_ATTR_SLEW_RATE_FIELD_WIDTH 2

#define	PINMUX_MIO_PAD_ATTR_DRIVE_STRENGTH_FIELD_WIDTH 4

#define	PINMUX_MIO_PAD_ATTR_MULTIREG_COUNT 12

#define	PINMUX_MIO_PAD_ATTR_0_REG_OFFSET 0xb4

#define	PINMUX_MIO_PAD_ATTR_0_REG_RESVAL 0x0u

#define	PINMUX_MIO_PAD_ATTR_0_INVERT_0_BIT 0

#define	PINMUX_MIO_PAD_ATTR_0_VIRTUAL_OD_EN_0_BIT 1

#define	PINMUX_MIO_PAD_ATTR_0_PULL_EN_0_BIT 2

#define	PINMUX_MIO_PAD_ATTR_0_PULL_SELECT_0_BIT 3

#define	PINMUX_MIO_PAD_ATTR_0_PULL_SELECT_0_VALUE_PULL_DOWN 0x0

#define	PINMUX_MIO_PAD_ATTR_0_PULL_SELECT_0_VALUE_PULL_UP 0x1

#define	PINMUX_MIO_PAD_ATTR_0_KEEPER_EN_0_BIT 4

#define	PINMUX_MIO_PAD_ATTR_0_SCHMITT_EN_0_BIT 5

#define	PINMUX_MIO_PAD_ATTR_0_OD_EN_0_BIT 6

#define	PINMUX_MIO_PAD_ATTR_0_INPUT_DISABLE_0_BIT 7

#define	PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_MASK 0x3u

#define	PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_OFFSET 16

#define	PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_MASK, .index = PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_OFFSET })

#define	PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_MASK 0xfu

#define	PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_OFFSET 20

#define	PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_MASK, .index = PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_OFFSET })

#define	PINMUX_MIO_PAD_ATTR_1_REG_OFFSET 0xb8

#define	PINMUX_MIO_PAD_ATTR_1_REG_RESVAL 0x0u

#define	PINMUX_MIO_PAD_ATTR_1_INVERT_1_BIT 0

#define	PINMUX_MIO_PAD_ATTR_1_VIRTUAL_OD_EN_1_BIT 1

#define	PINMUX_MIO_PAD_ATTR_1_PULL_EN_1_BIT 2

#define	PINMUX_MIO_PAD_ATTR_1_PULL_SELECT_1_BIT 3

#define	PINMUX_MIO_PAD_ATTR_1_KEEPER_EN_1_BIT 4

#define	PINMUX_MIO_PAD_ATTR_1_SCHMITT_EN_1_BIT 5

#define	PINMUX_MIO_PAD_ATTR_1_OD_EN_1_BIT 6

#define	PINMUX_MIO_PAD_ATTR_1_INPUT_DISABLE_1_BIT 7

#define	PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_MASK 0x3u

#define	PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_OFFSET 16

#define	PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_MASK, .index = PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_OFFSET })

#define	PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_MASK 0xfu

#define	PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_OFFSET 20

#define	PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_MASK, .index = PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_OFFSET })

#define	PINMUX_MIO_PAD_ATTR_2_REG_OFFSET 0xbc

#define	PINMUX_MIO_PAD_ATTR_2_REG_RESVAL 0x0u

#define	PINMUX_MIO_PAD_ATTR_2_INVERT_2_BIT 0

#define	PINMUX_MIO_PAD_ATTR_2_VIRTUAL_OD_EN_2_BIT 1

#define	PINMUX_MIO_PAD_ATTR_2_PULL_EN_2_BIT 2

#define	PINMUX_MIO_PAD_ATTR_2_PULL_SELECT_2_BIT 3

#define	PINMUX_MIO_PAD_ATTR_2_KEEPER_EN_2_BIT 4

#define	PINMUX_MIO_PAD_ATTR_2_SCHMITT_EN_2_BIT 5

#define	PINMUX_MIO_PAD_ATTR_2_OD_EN_2_BIT 6

#define	PINMUX_MIO_PAD_ATTR_2_INPUT_DISABLE_2_BIT 7

#define	PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_MASK 0x3u

#define	PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_OFFSET 16

#define	PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_MASK, .index = PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_OFFSET })

#define	PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_MASK 0xfu

#define	PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_OFFSET 20

#define	PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_MASK, .index = PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_OFFSET })

#define	PINMUX_MIO_PAD_ATTR_3_REG_OFFSET 0xc0

#define	PINMUX_MIO_PAD_ATTR_3_REG_RESVAL 0x0u

#define	PINMUX_MIO_PAD_ATTR_3_INVERT_3_BIT 0

#define	PINMUX_MIO_PAD_ATTR_3_VIRTUAL_OD_EN_3_BIT 1

#define	PINMUX_MIO_PAD_ATTR_3_PULL_EN_3_BIT 2

#define	PINMUX_MIO_PAD_ATTR_3_PULL_SELECT_3_BIT 3

#define	PINMUX_MIO_PAD_ATTR_3_KEEPER_EN_3_BIT 4

#define	PINMUX_MIO_PAD_ATTR_3_SCHMITT_EN_3_BIT 5

#define	PINMUX_MIO_PAD_ATTR_3_OD_EN_3_BIT 6

#define	PINMUX_MIO_PAD_ATTR_3_INPUT_DISABLE_3_BIT 7

#define	PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_MASK 0x3u

#define	PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_OFFSET 16

#define	PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_MASK, .index = PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_OFFSET })

#define	PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_MASK 0xfu

#define	PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_OFFSET 20

#define	PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_MASK, .index = PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_OFFSET })

#define	PINMUX_MIO_PAD_ATTR_4_REG_OFFSET 0xc4

#define	PINMUX_MIO_PAD_ATTR_4_REG_RESVAL 0x0u

#define	PINMUX_MIO_PAD_ATTR_4_INVERT_4_BIT 0

#define	PINMUX_MIO_PAD_ATTR_4_VIRTUAL_OD_EN_4_BIT 1

#define	PINMUX_MIO_PAD_ATTR_4_PULL_EN_4_BIT 2

#define	PINMUX_MIO_PAD_ATTR_4_PULL_SELECT_4_BIT 3

#define	PINMUX_MIO_PAD_ATTR_4_KEEPER_EN_4_BIT 4

#define	PINMUX_MIO_PAD_ATTR_4_SCHMITT_EN_4_BIT 5

#define	PINMUX_MIO_PAD_ATTR_4_OD_EN_4_BIT 6

#define	PINMUX_MIO_PAD_ATTR_4_INPUT_DISABLE_4_BIT 7

#define	PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_MASK 0x3u

#define	PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_OFFSET 16

#define	PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_MASK, .index = PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_OFFSET })

#define	PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_MASK 0xfu

#define	PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_OFFSET 20

#define	PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_MASK, .index = PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_OFFSET })

#define	PINMUX_MIO_PAD_ATTR_5_REG_OFFSET 0xc8

#define	PINMUX_MIO_PAD_ATTR_5_REG_RESVAL 0x0u

#define	PINMUX_MIO_PAD_ATTR_5_INVERT_5_BIT 0

#define	PINMUX_MIO_PAD_ATTR_5_VIRTUAL_OD_EN_5_BIT 1

#define	PINMUX_MIO_PAD_ATTR_5_PULL_EN_5_BIT 2

#define	PINMUX_MIO_PAD_ATTR_5_PULL_SELECT_5_BIT 3

#define	PINMUX_MIO_PAD_ATTR_5_KEEPER_EN_5_BIT 4

#define	PINMUX_MIO_PAD_ATTR_5_SCHMITT_EN_5_BIT 5

#define	PINMUX_MIO_PAD_ATTR_5_OD_EN_5_BIT 6

#define	PINMUX_MIO_PAD_ATTR_5_INPUT_DISABLE_5_BIT 7

#define	PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_MASK 0x3u

#define	PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_OFFSET 16

#define	PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_MASK, .index = PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_OFFSET })

#define	PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_MASK 0xfu

#define	PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_OFFSET 20

#define	PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_MASK, .index = PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_OFFSET })

#define	PINMUX_MIO_PAD_ATTR_6_REG_OFFSET 0xcc

#define	PINMUX_MIO_PAD_ATTR_6_REG_RESVAL 0x0u

#define	PINMUX_MIO_PAD_ATTR_6_INVERT_6_BIT 0

#define	PINMUX_MIO_PAD_ATTR_6_VIRTUAL_OD_EN_6_BIT 1

#define	PINMUX_MIO_PAD_ATTR_6_PULL_EN_6_BIT 2

#define	PINMUX_MIO_PAD_ATTR_6_PULL_SELECT_6_BIT 3

#define	PINMUX_MIO_PAD_ATTR_6_KEEPER_EN_6_BIT 4

#define	PINMUX_MIO_PAD_ATTR_6_SCHMITT_EN_6_BIT 5

#define	PINMUX_MIO_PAD_ATTR_6_OD_EN_6_BIT 6

#define	PINMUX_MIO_PAD_ATTR_6_INPUT_DISABLE_6_BIT 7

#define	PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_MASK 0x3u

#define	PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_OFFSET 16

#define	PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_MASK, .index = PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_OFFSET })

#define	PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_MASK 0xfu

#define	PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_OFFSET 20

#define	PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_MASK, .index = PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_OFFSET })

#define	PINMUX_MIO_PAD_ATTR_7_REG_OFFSET 0xd0

#define	PINMUX_MIO_PAD_ATTR_7_REG_RESVAL 0x0u

#define	PINMUX_MIO_PAD_ATTR_7_INVERT_7_BIT 0

#define	PINMUX_MIO_PAD_ATTR_7_VIRTUAL_OD_EN_7_BIT 1

#define	PINMUX_MIO_PAD_ATTR_7_PULL_EN_7_BIT 2

#define	PINMUX_MIO_PAD_ATTR_7_PULL_SELECT_7_BIT 3

#define	PINMUX_MIO_PAD_ATTR_7_KEEPER_EN_7_BIT 4

#define	PINMUX_MIO_PAD_ATTR_7_SCHMITT_EN_7_BIT 5

#define	PINMUX_MIO_PAD_ATTR_7_OD_EN_7_BIT 6

#define	PINMUX_MIO_PAD_ATTR_7_INPUT_DISABLE_7_BIT 7

#define	PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_MASK 0x3u

#define	PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_OFFSET 16

#define	PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_MASK, .index = PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_OFFSET })

#define	PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_MASK 0xfu

#define	PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_OFFSET 20

#define	PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_MASK, .index = PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_OFFSET })

#define	PINMUX_MIO_PAD_ATTR_8_REG_OFFSET 0xd4

#define	PINMUX_MIO_PAD_ATTR_8_REG_RESVAL 0x0u

#define	PINMUX_MIO_PAD_ATTR_8_INVERT_8_BIT 0

#define	PINMUX_MIO_PAD_ATTR_8_VIRTUAL_OD_EN_8_BIT 1

#define	PINMUX_MIO_PAD_ATTR_8_PULL_EN_8_BIT 2

#define	PINMUX_MIO_PAD_ATTR_8_PULL_SELECT_8_BIT 3

#define	PINMUX_MIO_PAD_ATTR_8_KEEPER_EN_8_BIT 4

#define	PINMUX_MIO_PAD_ATTR_8_SCHMITT_EN_8_BIT 5

#define	PINMUX_MIO_PAD_ATTR_8_OD_EN_8_BIT 6

#define	PINMUX_MIO_PAD_ATTR_8_INPUT_DISABLE_8_BIT 7

#define	PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_MASK 0x3u

#define	PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_OFFSET 16

#define	PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_MASK, .index = PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_OFFSET })

#define	PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_MASK 0xfu

#define	PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_OFFSET 20

#define	PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_MASK, .index = PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_OFFSET })

#define	PINMUX_MIO_PAD_ATTR_9_REG_OFFSET 0xd8

#define	PINMUX_MIO_PAD_ATTR_9_REG_RESVAL 0x0u

#define	PINMUX_MIO_PAD_ATTR_9_INVERT_9_BIT 0

#define	PINMUX_MIO_PAD_ATTR_9_VIRTUAL_OD_EN_9_BIT 1

#define	PINMUX_MIO_PAD_ATTR_9_PULL_EN_9_BIT 2

#define	PINMUX_MIO_PAD_ATTR_9_PULL_SELECT_9_BIT 3

#define	PINMUX_MIO_PAD_ATTR_9_KEEPER_EN_9_BIT 4

#define	PINMUX_MIO_PAD_ATTR_9_SCHMITT_EN_9_BIT 5

#define	PINMUX_MIO_PAD_ATTR_9_OD_EN_9_BIT 6

#define	PINMUX_MIO_PAD_ATTR_9_INPUT_DISABLE_9_BIT 7

#define	PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_MASK 0x3u

#define	PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_OFFSET 16

#define	PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_MASK, .index = PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_OFFSET })

#define	PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_MASK 0xfu

#define	PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_OFFSET 20

#define	PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_MASK, .index = PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_OFFSET })

#define	PINMUX_MIO_PAD_ATTR_10_REG_OFFSET 0xdc

#define	PINMUX_MIO_PAD_ATTR_10_REG_RESVAL 0x0u

#define	PINMUX_MIO_PAD_ATTR_10_INVERT_10_BIT 0

#define	PINMUX_MIO_PAD_ATTR_10_VIRTUAL_OD_EN_10_BIT 1

#define	PINMUX_MIO_PAD_ATTR_10_PULL_EN_10_BIT 2

#define	PINMUX_MIO_PAD_ATTR_10_PULL_SELECT_10_BIT 3

#define	PINMUX_MIO_PAD_ATTR_10_KEEPER_EN_10_BIT 4

#define	PINMUX_MIO_PAD_ATTR_10_SCHMITT_EN_10_BIT 5

#define	PINMUX_MIO_PAD_ATTR_10_OD_EN_10_BIT 6

#define	PINMUX_MIO_PAD_ATTR_10_INPUT_DISABLE_10_BIT 7

#define	PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_MASK 0x3u

#define	PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_OFFSET 16

#define	PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_MASK, .index = PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_OFFSET })

#define	PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_MASK 0xfu

#define	PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_OFFSET 20

#define	PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_MASK, .index = PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_OFFSET })

#define	PINMUX_MIO_PAD_ATTR_11_REG_OFFSET 0xe0

#define	PINMUX_MIO_PAD_ATTR_11_REG_RESVAL 0x0u

#define	PINMUX_MIO_PAD_ATTR_11_INVERT_11_BIT 0

#define	PINMUX_MIO_PAD_ATTR_11_VIRTUAL_OD_EN_11_BIT 1

#define	PINMUX_MIO_PAD_ATTR_11_PULL_EN_11_BIT 2

#define	PINMUX_MIO_PAD_ATTR_11_PULL_SELECT_11_BIT 3

#define	PINMUX_MIO_PAD_ATTR_11_KEEPER_EN_11_BIT 4

#define	PINMUX_MIO_PAD_ATTR_11_SCHMITT_EN_11_BIT 5

#define	PINMUX_MIO_PAD_ATTR_11_OD_EN_11_BIT 6

#define	PINMUX_MIO_PAD_ATTR_11_INPUT_DISABLE_11_BIT 7

#define	PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_MASK 0x3u

#define	PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_OFFSET 16

#define	PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_MASK, .index = PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_OFFSET })

#define	PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_MASK 0xfu

#define	PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_OFFSET 20

#define	PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_MASK, .index = PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_REGWEN_EN_FIELD_WIDTH 1

#define	PINMUX_DIO_PAD_ATTR_REGWEN_MULTIREG_COUNT 73

#define	PINMUX_DIO_PAD_ATTR_REGWEN_0_REG_OFFSET 0xe4

#define	PINMUX_DIO_PAD_ATTR_REGWEN_0_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_0_EN_0_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_1_REG_OFFSET 0xe8

#define	PINMUX_DIO_PAD_ATTR_REGWEN_1_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_1_EN_1_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_2_REG_OFFSET 0xec

#define	PINMUX_DIO_PAD_ATTR_REGWEN_2_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_2_EN_2_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_3_REG_OFFSET 0xf0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_3_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_3_EN_3_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_4_REG_OFFSET 0xf4

#define	PINMUX_DIO_PAD_ATTR_REGWEN_4_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_4_EN_4_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_5_REG_OFFSET 0xf8

#define	PINMUX_DIO_PAD_ATTR_REGWEN_5_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_5_EN_5_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_6_REG_OFFSET 0xfc

#define	PINMUX_DIO_PAD_ATTR_REGWEN_6_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_6_EN_6_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_7_REG_OFFSET 0x100

#define	PINMUX_DIO_PAD_ATTR_REGWEN_7_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_7_EN_7_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_8_REG_OFFSET 0x104

#define	PINMUX_DIO_PAD_ATTR_REGWEN_8_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_8_EN_8_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_9_REG_OFFSET 0x108

#define	PINMUX_DIO_PAD_ATTR_REGWEN_9_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_9_EN_9_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_10_REG_OFFSET 0x10c

#define	PINMUX_DIO_PAD_ATTR_REGWEN_10_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_10_EN_10_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_11_REG_OFFSET 0x110

#define	PINMUX_DIO_PAD_ATTR_REGWEN_11_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_11_EN_11_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_12_REG_OFFSET 0x114

#define	PINMUX_DIO_PAD_ATTR_REGWEN_12_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_12_EN_12_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_13_REG_OFFSET 0x118

#define	PINMUX_DIO_PAD_ATTR_REGWEN_13_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_13_EN_13_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_14_REG_OFFSET 0x11c

#define	PINMUX_DIO_PAD_ATTR_REGWEN_14_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_14_EN_14_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_15_REG_OFFSET 0x120

#define	PINMUX_DIO_PAD_ATTR_REGWEN_15_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_15_EN_15_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_16_REG_OFFSET 0x124

#define	PINMUX_DIO_PAD_ATTR_REGWEN_16_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_16_EN_16_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_17_REG_OFFSET 0x128

#define	PINMUX_DIO_PAD_ATTR_REGWEN_17_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_17_EN_17_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_18_REG_OFFSET 0x12c

#define	PINMUX_DIO_PAD_ATTR_REGWEN_18_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_18_EN_18_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_19_REG_OFFSET 0x130

#define	PINMUX_DIO_PAD_ATTR_REGWEN_19_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_19_EN_19_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_20_REG_OFFSET 0x134

#define	PINMUX_DIO_PAD_ATTR_REGWEN_20_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_20_EN_20_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_21_REG_OFFSET 0x138

#define	PINMUX_DIO_PAD_ATTR_REGWEN_21_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_21_EN_21_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_22_REG_OFFSET 0x13c

#define	PINMUX_DIO_PAD_ATTR_REGWEN_22_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_22_EN_22_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_23_REG_OFFSET 0x140

#define	PINMUX_DIO_PAD_ATTR_REGWEN_23_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_23_EN_23_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_24_REG_OFFSET 0x144

#define	PINMUX_DIO_PAD_ATTR_REGWEN_24_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_24_EN_24_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_25_REG_OFFSET 0x148

#define	PINMUX_DIO_PAD_ATTR_REGWEN_25_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_25_EN_25_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_26_REG_OFFSET 0x14c

#define	PINMUX_DIO_PAD_ATTR_REGWEN_26_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_26_EN_26_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_27_REG_OFFSET 0x150

#define	PINMUX_DIO_PAD_ATTR_REGWEN_27_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_27_EN_27_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_28_REG_OFFSET 0x154

#define	PINMUX_DIO_PAD_ATTR_REGWEN_28_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_28_EN_28_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_29_REG_OFFSET 0x158

#define	PINMUX_DIO_PAD_ATTR_REGWEN_29_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_29_EN_29_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_30_REG_OFFSET 0x15c

#define	PINMUX_DIO_PAD_ATTR_REGWEN_30_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_30_EN_30_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_31_REG_OFFSET 0x160

#define	PINMUX_DIO_PAD_ATTR_REGWEN_31_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_31_EN_31_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_32_REG_OFFSET 0x164

#define	PINMUX_DIO_PAD_ATTR_REGWEN_32_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_32_EN_32_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_33_REG_OFFSET 0x168

#define	PINMUX_DIO_PAD_ATTR_REGWEN_33_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_33_EN_33_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_34_REG_OFFSET 0x16c

#define	PINMUX_DIO_PAD_ATTR_REGWEN_34_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_34_EN_34_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_35_REG_OFFSET 0x170

#define	PINMUX_DIO_PAD_ATTR_REGWEN_35_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_35_EN_35_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_36_REG_OFFSET 0x174

#define	PINMUX_DIO_PAD_ATTR_REGWEN_36_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_36_EN_36_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_37_REG_OFFSET 0x178

#define	PINMUX_DIO_PAD_ATTR_REGWEN_37_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_37_EN_37_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_38_REG_OFFSET 0x17c

#define	PINMUX_DIO_PAD_ATTR_REGWEN_38_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_38_EN_38_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_39_REG_OFFSET 0x180

#define	PINMUX_DIO_PAD_ATTR_REGWEN_39_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_39_EN_39_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_40_REG_OFFSET 0x184

#define	PINMUX_DIO_PAD_ATTR_REGWEN_40_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_40_EN_40_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_41_REG_OFFSET 0x188

#define	PINMUX_DIO_PAD_ATTR_REGWEN_41_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_41_EN_41_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_42_REG_OFFSET 0x18c

#define	PINMUX_DIO_PAD_ATTR_REGWEN_42_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_42_EN_42_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_43_REG_OFFSET 0x190

#define	PINMUX_DIO_PAD_ATTR_REGWEN_43_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_43_EN_43_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_44_REG_OFFSET 0x194

#define	PINMUX_DIO_PAD_ATTR_REGWEN_44_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_44_EN_44_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_45_REG_OFFSET 0x198

#define	PINMUX_DIO_PAD_ATTR_REGWEN_45_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_45_EN_45_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_46_REG_OFFSET 0x19c

#define	PINMUX_DIO_PAD_ATTR_REGWEN_46_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_46_EN_46_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_47_REG_OFFSET 0x1a0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_47_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_47_EN_47_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_48_REG_OFFSET 0x1a4

#define	PINMUX_DIO_PAD_ATTR_REGWEN_48_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_48_EN_48_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_49_REG_OFFSET 0x1a8

#define	PINMUX_DIO_PAD_ATTR_REGWEN_49_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_49_EN_49_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_50_REG_OFFSET 0x1ac

#define	PINMUX_DIO_PAD_ATTR_REGWEN_50_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_50_EN_50_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_51_REG_OFFSET 0x1b0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_51_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_51_EN_51_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_52_REG_OFFSET 0x1b4

#define	PINMUX_DIO_PAD_ATTR_REGWEN_52_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_52_EN_52_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_53_REG_OFFSET 0x1b8

#define	PINMUX_DIO_PAD_ATTR_REGWEN_53_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_53_EN_53_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_54_REG_OFFSET 0x1bc

#define	PINMUX_DIO_PAD_ATTR_REGWEN_54_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_54_EN_54_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_55_REG_OFFSET 0x1c0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_55_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_55_EN_55_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_56_REG_OFFSET 0x1c4

#define	PINMUX_DIO_PAD_ATTR_REGWEN_56_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_56_EN_56_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_57_REG_OFFSET 0x1c8

#define	PINMUX_DIO_PAD_ATTR_REGWEN_57_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_57_EN_57_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_58_REG_OFFSET 0x1cc

#define	PINMUX_DIO_PAD_ATTR_REGWEN_58_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_58_EN_58_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_59_REG_OFFSET 0x1d0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_59_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_59_EN_59_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_60_REG_OFFSET 0x1d4

#define	PINMUX_DIO_PAD_ATTR_REGWEN_60_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_60_EN_60_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_61_REG_OFFSET 0x1d8

#define	PINMUX_DIO_PAD_ATTR_REGWEN_61_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_61_EN_61_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_62_REG_OFFSET 0x1dc

#define	PINMUX_DIO_PAD_ATTR_REGWEN_62_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_62_EN_62_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_63_REG_OFFSET 0x1e0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_63_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_63_EN_63_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_64_REG_OFFSET 0x1e4

#define	PINMUX_DIO_PAD_ATTR_REGWEN_64_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_64_EN_64_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_65_REG_OFFSET 0x1e8

#define	PINMUX_DIO_PAD_ATTR_REGWEN_65_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_65_EN_65_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_66_REG_OFFSET 0x1ec

#define	PINMUX_DIO_PAD_ATTR_REGWEN_66_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_66_EN_66_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_67_REG_OFFSET 0x1f0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_67_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_67_EN_67_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_68_REG_OFFSET 0x1f4

#define	PINMUX_DIO_PAD_ATTR_REGWEN_68_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_68_EN_68_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_69_REG_OFFSET 0x1f8

#define	PINMUX_DIO_PAD_ATTR_REGWEN_69_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_69_EN_69_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_70_REG_OFFSET 0x1fc

#define	PINMUX_DIO_PAD_ATTR_REGWEN_70_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_70_EN_70_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_71_REG_OFFSET 0x200

#define	PINMUX_DIO_PAD_ATTR_REGWEN_71_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_71_EN_71_BIT 0

#define	PINMUX_DIO_PAD_ATTR_REGWEN_72_REG_OFFSET 0x204

#define	PINMUX_DIO_PAD_ATTR_REGWEN_72_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_ATTR_REGWEN_72_EN_72_BIT 0

#define	PINMUX_DIO_PAD_ATTR_INVERT_FIELD_WIDTH 1

#define	PINMUX_DIO_PAD_ATTR_VIRTUAL_OD_EN_FIELD_WIDTH 1

#define	PINMUX_DIO_PAD_ATTR_PULL_EN_FIELD_WIDTH 1

#define	PINMUX_DIO_PAD_ATTR_PULL_SELECT_FIELD_WIDTH 1

#define	PINMUX_DIO_PAD_ATTR_KEEPER_EN_FIELD_WIDTH 1

#define	PINMUX_DIO_PAD_ATTR_SCHMITT_EN_FIELD_WIDTH 1

#define	PINMUX_DIO_PAD_ATTR_OD_EN_FIELD_WIDTH 1

#define	PINMUX_DIO_PAD_ATTR_INPUT_DISABLE_FIELD_WIDTH 1

#define	PINMUX_DIO_PAD_ATTR_SLEW_RATE_FIELD_WIDTH 2

#define	PINMUX_DIO_PAD_ATTR_DRIVE_STRENGTH_FIELD_WIDTH 4

#define	PINMUX_DIO_PAD_ATTR_MULTIREG_COUNT 73

#define	PINMUX_DIO_PAD_ATTR_0_REG_OFFSET 0x208

#define	PINMUX_DIO_PAD_ATTR_0_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_0_INVERT_0_BIT 0

#define	PINMUX_DIO_PAD_ATTR_0_VIRTUAL_OD_EN_0_BIT 1

#define	PINMUX_DIO_PAD_ATTR_0_PULL_EN_0_BIT 2

#define	PINMUX_DIO_PAD_ATTR_0_PULL_SELECT_0_BIT 3

#define	PINMUX_DIO_PAD_ATTR_0_PULL_SELECT_0_VALUE_PULL_DOWN 0x0

#define	PINMUX_DIO_PAD_ATTR_0_PULL_SELECT_0_VALUE_PULL_UP 0x1

#define	PINMUX_DIO_PAD_ATTR_0_KEEPER_EN_0_BIT 4

#define	PINMUX_DIO_PAD_ATTR_0_SCHMITT_EN_0_BIT 5

#define	PINMUX_DIO_PAD_ATTR_0_OD_EN_0_BIT 6

#define	PINMUX_DIO_PAD_ATTR_0_INPUT_DISABLE_0_BIT 7

#define	PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_MASK, .index = PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_MASK, .index = PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_1_REG_OFFSET 0x20c

#define	PINMUX_DIO_PAD_ATTR_1_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_1_INVERT_1_BIT 0

#define	PINMUX_DIO_PAD_ATTR_1_VIRTUAL_OD_EN_1_BIT 1

#define	PINMUX_DIO_PAD_ATTR_1_PULL_EN_1_BIT 2

#define	PINMUX_DIO_PAD_ATTR_1_PULL_SELECT_1_BIT 3

#define	PINMUX_DIO_PAD_ATTR_1_KEEPER_EN_1_BIT 4

#define	PINMUX_DIO_PAD_ATTR_1_SCHMITT_EN_1_BIT 5

#define	PINMUX_DIO_PAD_ATTR_1_OD_EN_1_BIT 6

#define	PINMUX_DIO_PAD_ATTR_1_INPUT_DISABLE_1_BIT 7

#define	PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_MASK, .index = PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_MASK, .index = PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_2_REG_OFFSET 0x210

#define	PINMUX_DIO_PAD_ATTR_2_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_2_INVERT_2_BIT 0

#define	PINMUX_DIO_PAD_ATTR_2_VIRTUAL_OD_EN_2_BIT 1

#define	PINMUX_DIO_PAD_ATTR_2_PULL_EN_2_BIT 2

#define	PINMUX_DIO_PAD_ATTR_2_PULL_SELECT_2_BIT 3

#define	PINMUX_DIO_PAD_ATTR_2_KEEPER_EN_2_BIT 4

#define	PINMUX_DIO_PAD_ATTR_2_SCHMITT_EN_2_BIT 5

#define	PINMUX_DIO_PAD_ATTR_2_OD_EN_2_BIT 6

#define	PINMUX_DIO_PAD_ATTR_2_INPUT_DISABLE_2_BIT 7

#define	PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_MASK, .index = PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_MASK, .index = PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_3_REG_OFFSET 0x214

#define	PINMUX_DIO_PAD_ATTR_3_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_3_INVERT_3_BIT 0

#define	PINMUX_DIO_PAD_ATTR_3_VIRTUAL_OD_EN_3_BIT 1

#define	PINMUX_DIO_PAD_ATTR_3_PULL_EN_3_BIT 2

#define	PINMUX_DIO_PAD_ATTR_3_PULL_SELECT_3_BIT 3

#define	PINMUX_DIO_PAD_ATTR_3_KEEPER_EN_3_BIT 4

#define	PINMUX_DIO_PAD_ATTR_3_SCHMITT_EN_3_BIT 5

#define	PINMUX_DIO_PAD_ATTR_3_OD_EN_3_BIT 6

#define	PINMUX_DIO_PAD_ATTR_3_INPUT_DISABLE_3_BIT 7

#define	PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_MASK, .index = PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_MASK, .index = PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_4_REG_OFFSET 0x218

#define	PINMUX_DIO_PAD_ATTR_4_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_4_INVERT_4_BIT 0

#define	PINMUX_DIO_PAD_ATTR_4_VIRTUAL_OD_EN_4_BIT 1

#define	PINMUX_DIO_PAD_ATTR_4_PULL_EN_4_BIT 2

#define	PINMUX_DIO_PAD_ATTR_4_PULL_SELECT_4_BIT 3

#define	PINMUX_DIO_PAD_ATTR_4_KEEPER_EN_4_BIT 4

#define	PINMUX_DIO_PAD_ATTR_4_SCHMITT_EN_4_BIT 5

#define	PINMUX_DIO_PAD_ATTR_4_OD_EN_4_BIT 6

#define	PINMUX_DIO_PAD_ATTR_4_INPUT_DISABLE_4_BIT 7

#define	PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_MASK, .index = PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_MASK, .index = PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_5_REG_OFFSET 0x21c

#define	PINMUX_DIO_PAD_ATTR_5_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_5_INVERT_5_BIT 0

#define	PINMUX_DIO_PAD_ATTR_5_VIRTUAL_OD_EN_5_BIT 1

#define	PINMUX_DIO_PAD_ATTR_5_PULL_EN_5_BIT 2

#define	PINMUX_DIO_PAD_ATTR_5_PULL_SELECT_5_BIT 3

#define	PINMUX_DIO_PAD_ATTR_5_KEEPER_EN_5_BIT 4

#define	PINMUX_DIO_PAD_ATTR_5_SCHMITT_EN_5_BIT 5

#define	PINMUX_DIO_PAD_ATTR_5_OD_EN_5_BIT 6

#define	PINMUX_DIO_PAD_ATTR_5_INPUT_DISABLE_5_BIT 7

#define	PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_MASK, .index = PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_MASK, .index = PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_6_REG_OFFSET 0x220

#define	PINMUX_DIO_PAD_ATTR_6_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_6_INVERT_6_BIT 0

#define	PINMUX_DIO_PAD_ATTR_6_VIRTUAL_OD_EN_6_BIT 1

#define	PINMUX_DIO_PAD_ATTR_6_PULL_EN_6_BIT 2

#define	PINMUX_DIO_PAD_ATTR_6_PULL_SELECT_6_BIT 3

#define	PINMUX_DIO_PAD_ATTR_6_KEEPER_EN_6_BIT 4

#define	PINMUX_DIO_PAD_ATTR_6_SCHMITT_EN_6_BIT 5

#define	PINMUX_DIO_PAD_ATTR_6_OD_EN_6_BIT 6

#define	PINMUX_DIO_PAD_ATTR_6_INPUT_DISABLE_6_BIT 7

#define	PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_MASK, .index = PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_MASK, .index = PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_7_REG_OFFSET 0x224

#define	PINMUX_DIO_PAD_ATTR_7_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_7_INVERT_7_BIT 0

#define	PINMUX_DIO_PAD_ATTR_7_VIRTUAL_OD_EN_7_BIT 1

#define	PINMUX_DIO_PAD_ATTR_7_PULL_EN_7_BIT 2

#define	PINMUX_DIO_PAD_ATTR_7_PULL_SELECT_7_BIT 3

#define	PINMUX_DIO_PAD_ATTR_7_KEEPER_EN_7_BIT 4

#define	PINMUX_DIO_PAD_ATTR_7_SCHMITT_EN_7_BIT 5

#define	PINMUX_DIO_PAD_ATTR_7_OD_EN_7_BIT 6

#define	PINMUX_DIO_PAD_ATTR_7_INPUT_DISABLE_7_BIT 7

#define	PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_MASK, .index = PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_MASK, .index = PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_8_REG_OFFSET 0x228

#define	PINMUX_DIO_PAD_ATTR_8_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_8_INVERT_8_BIT 0

#define	PINMUX_DIO_PAD_ATTR_8_VIRTUAL_OD_EN_8_BIT 1

#define	PINMUX_DIO_PAD_ATTR_8_PULL_EN_8_BIT 2

#define	PINMUX_DIO_PAD_ATTR_8_PULL_SELECT_8_BIT 3

#define	PINMUX_DIO_PAD_ATTR_8_KEEPER_EN_8_BIT 4

#define	PINMUX_DIO_PAD_ATTR_8_SCHMITT_EN_8_BIT 5

#define	PINMUX_DIO_PAD_ATTR_8_OD_EN_8_BIT 6

#define	PINMUX_DIO_PAD_ATTR_8_INPUT_DISABLE_8_BIT 7

#define	PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_MASK, .index = PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_MASK, .index = PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_9_REG_OFFSET 0x22c

#define	PINMUX_DIO_PAD_ATTR_9_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_9_INVERT_9_BIT 0

#define	PINMUX_DIO_PAD_ATTR_9_VIRTUAL_OD_EN_9_BIT 1

#define	PINMUX_DIO_PAD_ATTR_9_PULL_EN_9_BIT 2

#define	PINMUX_DIO_PAD_ATTR_9_PULL_SELECT_9_BIT 3

#define	PINMUX_DIO_PAD_ATTR_9_KEEPER_EN_9_BIT 4

#define	PINMUX_DIO_PAD_ATTR_9_SCHMITT_EN_9_BIT 5

#define	PINMUX_DIO_PAD_ATTR_9_OD_EN_9_BIT 6

#define	PINMUX_DIO_PAD_ATTR_9_INPUT_DISABLE_9_BIT 7

#define	PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_MASK, .index = PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_MASK, .index = PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_10_REG_OFFSET 0x230

#define	PINMUX_DIO_PAD_ATTR_10_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_10_INVERT_10_BIT 0

#define	PINMUX_DIO_PAD_ATTR_10_VIRTUAL_OD_EN_10_BIT 1

#define	PINMUX_DIO_PAD_ATTR_10_PULL_EN_10_BIT 2

#define	PINMUX_DIO_PAD_ATTR_10_PULL_SELECT_10_BIT 3

#define	PINMUX_DIO_PAD_ATTR_10_KEEPER_EN_10_BIT 4

#define	PINMUX_DIO_PAD_ATTR_10_SCHMITT_EN_10_BIT 5

#define	PINMUX_DIO_PAD_ATTR_10_OD_EN_10_BIT 6

#define	PINMUX_DIO_PAD_ATTR_10_INPUT_DISABLE_10_BIT 7

#define	PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_MASK, .index = PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_MASK, .index = PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_11_REG_OFFSET 0x234

#define	PINMUX_DIO_PAD_ATTR_11_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_11_INVERT_11_BIT 0

#define	PINMUX_DIO_PAD_ATTR_11_VIRTUAL_OD_EN_11_BIT 1

#define	PINMUX_DIO_PAD_ATTR_11_PULL_EN_11_BIT 2

#define	PINMUX_DIO_PAD_ATTR_11_PULL_SELECT_11_BIT 3

#define	PINMUX_DIO_PAD_ATTR_11_KEEPER_EN_11_BIT 4

#define	PINMUX_DIO_PAD_ATTR_11_SCHMITT_EN_11_BIT 5

#define	PINMUX_DIO_PAD_ATTR_11_OD_EN_11_BIT 6

#define	PINMUX_DIO_PAD_ATTR_11_INPUT_DISABLE_11_BIT 7

#define	PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_MASK, .index = PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_MASK, .index = PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_12_REG_OFFSET 0x238

#define	PINMUX_DIO_PAD_ATTR_12_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_12_INVERT_12_BIT 0

#define	PINMUX_DIO_PAD_ATTR_12_VIRTUAL_OD_EN_12_BIT 1

#define	PINMUX_DIO_PAD_ATTR_12_PULL_EN_12_BIT 2

#define	PINMUX_DIO_PAD_ATTR_12_PULL_SELECT_12_BIT 3

#define	PINMUX_DIO_PAD_ATTR_12_KEEPER_EN_12_BIT 4

#define	PINMUX_DIO_PAD_ATTR_12_SCHMITT_EN_12_BIT 5

#define	PINMUX_DIO_PAD_ATTR_12_OD_EN_12_BIT 6

#define	PINMUX_DIO_PAD_ATTR_12_INPUT_DISABLE_12_BIT 7

#define	PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_MASK, .index = PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_MASK, .index = PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_13_REG_OFFSET 0x23c

#define	PINMUX_DIO_PAD_ATTR_13_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_13_INVERT_13_BIT 0

#define	PINMUX_DIO_PAD_ATTR_13_VIRTUAL_OD_EN_13_BIT 1

#define	PINMUX_DIO_PAD_ATTR_13_PULL_EN_13_BIT 2

#define	PINMUX_DIO_PAD_ATTR_13_PULL_SELECT_13_BIT 3

#define	PINMUX_DIO_PAD_ATTR_13_KEEPER_EN_13_BIT 4

#define	PINMUX_DIO_PAD_ATTR_13_SCHMITT_EN_13_BIT 5

#define	PINMUX_DIO_PAD_ATTR_13_OD_EN_13_BIT 6

#define	PINMUX_DIO_PAD_ATTR_13_INPUT_DISABLE_13_BIT 7

#define	PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_MASK, .index = PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_MASK, .index = PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_14_REG_OFFSET 0x240

#define	PINMUX_DIO_PAD_ATTR_14_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_14_INVERT_14_BIT 0

#define	PINMUX_DIO_PAD_ATTR_14_VIRTUAL_OD_EN_14_BIT 1

#define	PINMUX_DIO_PAD_ATTR_14_PULL_EN_14_BIT 2

#define	PINMUX_DIO_PAD_ATTR_14_PULL_SELECT_14_BIT 3

#define	PINMUX_DIO_PAD_ATTR_14_KEEPER_EN_14_BIT 4

#define	PINMUX_DIO_PAD_ATTR_14_SCHMITT_EN_14_BIT 5

#define	PINMUX_DIO_PAD_ATTR_14_OD_EN_14_BIT 6

#define	PINMUX_DIO_PAD_ATTR_14_INPUT_DISABLE_14_BIT 7

#define	PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_MASK, .index = PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_MASK, .index = PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_15_REG_OFFSET 0x244

#define	PINMUX_DIO_PAD_ATTR_15_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_15_INVERT_15_BIT 0

#define	PINMUX_DIO_PAD_ATTR_15_VIRTUAL_OD_EN_15_BIT 1

#define	PINMUX_DIO_PAD_ATTR_15_PULL_EN_15_BIT 2

#define	PINMUX_DIO_PAD_ATTR_15_PULL_SELECT_15_BIT 3

#define	PINMUX_DIO_PAD_ATTR_15_KEEPER_EN_15_BIT 4

#define	PINMUX_DIO_PAD_ATTR_15_SCHMITT_EN_15_BIT 5

#define	PINMUX_DIO_PAD_ATTR_15_OD_EN_15_BIT 6

#define	PINMUX_DIO_PAD_ATTR_15_INPUT_DISABLE_15_BIT 7

#define	PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_MASK, .index = PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_MASK, .index = PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_16_REG_OFFSET 0x248

#define	PINMUX_DIO_PAD_ATTR_16_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_16_INVERT_16_BIT 0

#define	PINMUX_DIO_PAD_ATTR_16_VIRTUAL_OD_EN_16_BIT 1

#define	PINMUX_DIO_PAD_ATTR_16_PULL_EN_16_BIT 2

#define	PINMUX_DIO_PAD_ATTR_16_PULL_SELECT_16_BIT 3

#define	PINMUX_DIO_PAD_ATTR_16_KEEPER_EN_16_BIT 4

#define	PINMUX_DIO_PAD_ATTR_16_SCHMITT_EN_16_BIT 5

#define	PINMUX_DIO_PAD_ATTR_16_OD_EN_16_BIT 6

#define	PINMUX_DIO_PAD_ATTR_16_INPUT_DISABLE_16_BIT 7

#define	PINMUX_DIO_PAD_ATTR_16_SLEW_RATE_16_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_16_SLEW_RATE_16_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_16_SLEW_RATE_16_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_16_SLEW_RATE_16_MASK, .index = PINMUX_DIO_PAD_ATTR_16_SLEW_RATE_16_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_16_DRIVE_STRENGTH_16_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_16_DRIVE_STRENGTH_16_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_16_DRIVE_STRENGTH_16_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_16_DRIVE_STRENGTH_16_MASK, .index = PINMUX_DIO_PAD_ATTR_16_DRIVE_STRENGTH_16_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_17_REG_OFFSET 0x24c

#define	PINMUX_DIO_PAD_ATTR_17_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_17_INVERT_17_BIT 0

#define	PINMUX_DIO_PAD_ATTR_17_VIRTUAL_OD_EN_17_BIT 1

#define	PINMUX_DIO_PAD_ATTR_17_PULL_EN_17_BIT 2

#define	PINMUX_DIO_PAD_ATTR_17_PULL_SELECT_17_BIT 3

#define	PINMUX_DIO_PAD_ATTR_17_KEEPER_EN_17_BIT 4

#define	PINMUX_DIO_PAD_ATTR_17_SCHMITT_EN_17_BIT 5

#define	PINMUX_DIO_PAD_ATTR_17_OD_EN_17_BIT 6

#define	PINMUX_DIO_PAD_ATTR_17_INPUT_DISABLE_17_BIT 7

#define	PINMUX_DIO_PAD_ATTR_17_SLEW_RATE_17_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_17_SLEW_RATE_17_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_17_SLEW_RATE_17_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_17_SLEW_RATE_17_MASK, .index = PINMUX_DIO_PAD_ATTR_17_SLEW_RATE_17_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_17_DRIVE_STRENGTH_17_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_17_DRIVE_STRENGTH_17_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_17_DRIVE_STRENGTH_17_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_17_DRIVE_STRENGTH_17_MASK, .index = PINMUX_DIO_PAD_ATTR_17_DRIVE_STRENGTH_17_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_18_REG_OFFSET 0x250

#define	PINMUX_DIO_PAD_ATTR_18_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_18_INVERT_18_BIT 0

#define	PINMUX_DIO_PAD_ATTR_18_VIRTUAL_OD_EN_18_BIT 1

#define	PINMUX_DIO_PAD_ATTR_18_PULL_EN_18_BIT 2

#define	PINMUX_DIO_PAD_ATTR_18_PULL_SELECT_18_BIT 3

#define	PINMUX_DIO_PAD_ATTR_18_KEEPER_EN_18_BIT 4

#define	PINMUX_DIO_PAD_ATTR_18_SCHMITT_EN_18_BIT 5

#define	PINMUX_DIO_PAD_ATTR_18_OD_EN_18_BIT 6

#define	PINMUX_DIO_PAD_ATTR_18_INPUT_DISABLE_18_BIT 7

#define	PINMUX_DIO_PAD_ATTR_18_SLEW_RATE_18_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_18_SLEW_RATE_18_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_18_SLEW_RATE_18_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_18_SLEW_RATE_18_MASK, .index = PINMUX_DIO_PAD_ATTR_18_SLEW_RATE_18_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_18_DRIVE_STRENGTH_18_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_18_DRIVE_STRENGTH_18_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_18_DRIVE_STRENGTH_18_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_18_DRIVE_STRENGTH_18_MASK, .index = PINMUX_DIO_PAD_ATTR_18_DRIVE_STRENGTH_18_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_19_REG_OFFSET 0x254

#define	PINMUX_DIO_PAD_ATTR_19_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_19_INVERT_19_BIT 0

#define	PINMUX_DIO_PAD_ATTR_19_VIRTUAL_OD_EN_19_BIT 1

#define	PINMUX_DIO_PAD_ATTR_19_PULL_EN_19_BIT 2

#define	PINMUX_DIO_PAD_ATTR_19_PULL_SELECT_19_BIT 3

#define	PINMUX_DIO_PAD_ATTR_19_KEEPER_EN_19_BIT 4

#define	PINMUX_DIO_PAD_ATTR_19_SCHMITT_EN_19_BIT 5

#define	PINMUX_DIO_PAD_ATTR_19_OD_EN_19_BIT 6

#define	PINMUX_DIO_PAD_ATTR_19_INPUT_DISABLE_19_BIT 7

#define	PINMUX_DIO_PAD_ATTR_19_SLEW_RATE_19_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_19_SLEW_RATE_19_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_19_SLEW_RATE_19_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_19_SLEW_RATE_19_MASK, .index = PINMUX_DIO_PAD_ATTR_19_SLEW_RATE_19_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_19_DRIVE_STRENGTH_19_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_19_DRIVE_STRENGTH_19_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_19_DRIVE_STRENGTH_19_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_19_DRIVE_STRENGTH_19_MASK, .index = PINMUX_DIO_PAD_ATTR_19_DRIVE_STRENGTH_19_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_20_REG_OFFSET 0x258

#define	PINMUX_DIO_PAD_ATTR_20_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_20_INVERT_20_BIT 0

#define	PINMUX_DIO_PAD_ATTR_20_VIRTUAL_OD_EN_20_BIT 1

#define	PINMUX_DIO_PAD_ATTR_20_PULL_EN_20_BIT 2

#define	PINMUX_DIO_PAD_ATTR_20_PULL_SELECT_20_BIT 3

#define	PINMUX_DIO_PAD_ATTR_20_KEEPER_EN_20_BIT 4

#define	PINMUX_DIO_PAD_ATTR_20_SCHMITT_EN_20_BIT 5

#define	PINMUX_DIO_PAD_ATTR_20_OD_EN_20_BIT 6

#define	PINMUX_DIO_PAD_ATTR_20_INPUT_DISABLE_20_BIT 7

#define	PINMUX_DIO_PAD_ATTR_20_SLEW_RATE_20_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_20_SLEW_RATE_20_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_20_SLEW_RATE_20_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_20_SLEW_RATE_20_MASK, .index = PINMUX_DIO_PAD_ATTR_20_SLEW_RATE_20_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_20_DRIVE_STRENGTH_20_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_20_DRIVE_STRENGTH_20_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_20_DRIVE_STRENGTH_20_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_20_DRIVE_STRENGTH_20_MASK, .index = PINMUX_DIO_PAD_ATTR_20_DRIVE_STRENGTH_20_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_21_REG_OFFSET 0x25c

#define	PINMUX_DIO_PAD_ATTR_21_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_21_INVERT_21_BIT 0

#define	PINMUX_DIO_PAD_ATTR_21_VIRTUAL_OD_EN_21_BIT 1

#define	PINMUX_DIO_PAD_ATTR_21_PULL_EN_21_BIT 2

#define	PINMUX_DIO_PAD_ATTR_21_PULL_SELECT_21_BIT 3

#define	PINMUX_DIO_PAD_ATTR_21_KEEPER_EN_21_BIT 4

#define	PINMUX_DIO_PAD_ATTR_21_SCHMITT_EN_21_BIT 5

#define	PINMUX_DIO_PAD_ATTR_21_OD_EN_21_BIT 6

#define	PINMUX_DIO_PAD_ATTR_21_INPUT_DISABLE_21_BIT 7

#define	PINMUX_DIO_PAD_ATTR_21_SLEW_RATE_21_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_21_SLEW_RATE_21_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_21_SLEW_RATE_21_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_21_SLEW_RATE_21_MASK, .index = PINMUX_DIO_PAD_ATTR_21_SLEW_RATE_21_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_21_DRIVE_STRENGTH_21_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_21_DRIVE_STRENGTH_21_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_21_DRIVE_STRENGTH_21_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_21_DRIVE_STRENGTH_21_MASK, .index = PINMUX_DIO_PAD_ATTR_21_DRIVE_STRENGTH_21_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_22_REG_OFFSET 0x260

#define	PINMUX_DIO_PAD_ATTR_22_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_22_INVERT_22_BIT 0

#define	PINMUX_DIO_PAD_ATTR_22_VIRTUAL_OD_EN_22_BIT 1

#define	PINMUX_DIO_PAD_ATTR_22_PULL_EN_22_BIT 2

#define	PINMUX_DIO_PAD_ATTR_22_PULL_SELECT_22_BIT 3

#define	PINMUX_DIO_PAD_ATTR_22_KEEPER_EN_22_BIT 4

#define	PINMUX_DIO_PAD_ATTR_22_SCHMITT_EN_22_BIT 5

#define	PINMUX_DIO_PAD_ATTR_22_OD_EN_22_BIT 6

#define	PINMUX_DIO_PAD_ATTR_22_INPUT_DISABLE_22_BIT 7

#define	PINMUX_DIO_PAD_ATTR_22_SLEW_RATE_22_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_22_SLEW_RATE_22_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_22_SLEW_RATE_22_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_22_SLEW_RATE_22_MASK, .index = PINMUX_DIO_PAD_ATTR_22_SLEW_RATE_22_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_22_DRIVE_STRENGTH_22_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_22_DRIVE_STRENGTH_22_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_22_DRIVE_STRENGTH_22_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_22_DRIVE_STRENGTH_22_MASK, .index = PINMUX_DIO_PAD_ATTR_22_DRIVE_STRENGTH_22_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_23_REG_OFFSET 0x264

#define	PINMUX_DIO_PAD_ATTR_23_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_23_INVERT_23_BIT 0

#define	PINMUX_DIO_PAD_ATTR_23_VIRTUAL_OD_EN_23_BIT 1

#define	PINMUX_DIO_PAD_ATTR_23_PULL_EN_23_BIT 2

#define	PINMUX_DIO_PAD_ATTR_23_PULL_SELECT_23_BIT 3

#define	PINMUX_DIO_PAD_ATTR_23_KEEPER_EN_23_BIT 4

#define	PINMUX_DIO_PAD_ATTR_23_SCHMITT_EN_23_BIT 5

#define	PINMUX_DIO_PAD_ATTR_23_OD_EN_23_BIT 6

#define	PINMUX_DIO_PAD_ATTR_23_INPUT_DISABLE_23_BIT 7

#define	PINMUX_DIO_PAD_ATTR_23_SLEW_RATE_23_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_23_SLEW_RATE_23_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_23_SLEW_RATE_23_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_23_SLEW_RATE_23_MASK, .index = PINMUX_DIO_PAD_ATTR_23_SLEW_RATE_23_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_23_DRIVE_STRENGTH_23_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_23_DRIVE_STRENGTH_23_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_23_DRIVE_STRENGTH_23_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_23_DRIVE_STRENGTH_23_MASK, .index = PINMUX_DIO_PAD_ATTR_23_DRIVE_STRENGTH_23_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_24_REG_OFFSET 0x268

#define	PINMUX_DIO_PAD_ATTR_24_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_24_INVERT_24_BIT 0

#define	PINMUX_DIO_PAD_ATTR_24_VIRTUAL_OD_EN_24_BIT 1

#define	PINMUX_DIO_PAD_ATTR_24_PULL_EN_24_BIT 2

#define	PINMUX_DIO_PAD_ATTR_24_PULL_SELECT_24_BIT 3

#define	PINMUX_DIO_PAD_ATTR_24_KEEPER_EN_24_BIT 4

#define	PINMUX_DIO_PAD_ATTR_24_SCHMITT_EN_24_BIT 5

#define	PINMUX_DIO_PAD_ATTR_24_OD_EN_24_BIT 6

#define	PINMUX_DIO_PAD_ATTR_24_INPUT_DISABLE_24_BIT 7

#define	PINMUX_DIO_PAD_ATTR_24_SLEW_RATE_24_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_24_SLEW_RATE_24_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_24_SLEW_RATE_24_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_24_SLEW_RATE_24_MASK, .index = PINMUX_DIO_PAD_ATTR_24_SLEW_RATE_24_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_24_DRIVE_STRENGTH_24_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_24_DRIVE_STRENGTH_24_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_24_DRIVE_STRENGTH_24_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_24_DRIVE_STRENGTH_24_MASK, .index = PINMUX_DIO_PAD_ATTR_24_DRIVE_STRENGTH_24_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_25_REG_OFFSET 0x26c

#define	PINMUX_DIO_PAD_ATTR_25_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_25_INVERT_25_BIT 0

#define	PINMUX_DIO_PAD_ATTR_25_VIRTUAL_OD_EN_25_BIT 1

#define	PINMUX_DIO_PAD_ATTR_25_PULL_EN_25_BIT 2

#define	PINMUX_DIO_PAD_ATTR_25_PULL_SELECT_25_BIT 3

#define	PINMUX_DIO_PAD_ATTR_25_KEEPER_EN_25_BIT 4

#define	PINMUX_DIO_PAD_ATTR_25_SCHMITT_EN_25_BIT 5

#define	PINMUX_DIO_PAD_ATTR_25_OD_EN_25_BIT 6

#define	PINMUX_DIO_PAD_ATTR_25_INPUT_DISABLE_25_BIT 7

#define	PINMUX_DIO_PAD_ATTR_25_SLEW_RATE_25_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_25_SLEW_RATE_25_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_25_SLEW_RATE_25_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_25_SLEW_RATE_25_MASK, .index = PINMUX_DIO_PAD_ATTR_25_SLEW_RATE_25_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_25_DRIVE_STRENGTH_25_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_25_DRIVE_STRENGTH_25_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_25_DRIVE_STRENGTH_25_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_25_DRIVE_STRENGTH_25_MASK, .index = PINMUX_DIO_PAD_ATTR_25_DRIVE_STRENGTH_25_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_26_REG_OFFSET 0x270

#define	PINMUX_DIO_PAD_ATTR_26_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_26_INVERT_26_BIT 0

#define	PINMUX_DIO_PAD_ATTR_26_VIRTUAL_OD_EN_26_BIT 1

#define	PINMUX_DIO_PAD_ATTR_26_PULL_EN_26_BIT 2

#define	PINMUX_DIO_PAD_ATTR_26_PULL_SELECT_26_BIT 3

#define	PINMUX_DIO_PAD_ATTR_26_KEEPER_EN_26_BIT 4

#define	PINMUX_DIO_PAD_ATTR_26_SCHMITT_EN_26_BIT 5

#define	PINMUX_DIO_PAD_ATTR_26_OD_EN_26_BIT 6

#define	PINMUX_DIO_PAD_ATTR_26_INPUT_DISABLE_26_BIT 7

#define	PINMUX_DIO_PAD_ATTR_26_SLEW_RATE_26_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_26_SLEW_RATE_26_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_26_SLEW_RATE_26_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_26_SLEW_RATE_26_MASK, .index = PINMUX_DIO_PAD_ATTR_26_SLEW_RATE_26_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_26_DRIVE_STRENGTH_26_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_26_DRIVE_STRENGTH_26_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_26_DRIVE_STRENGTH_26_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_26_DRIVE_STRENGTH_26_MASK, .index = PINMUX_DIO_PAD_ATTR_26_DRIVE_STRENGTH_26_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_27_REG_OFFSET 0x274

#define	PINMUX_DIO_PAD_ATTR_27_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_27_INVERT_27_BIT 0

#define	PINMUX_DIO_PAD_ATTR_27_VIRTUAL_OD_EN_27_BIT 1

#define	PINMUX_DIO_PAD_ATTR_27_PULL_EN_27_BIT 2

#define	PINMUX_DIO_PAD_ATTR_27_PULL_SELECT_27_BIT 3

#define	PINMUX_DIO_PAD_ATTR_27_KEEPER_EN_27_BIT 4

#define	PINMUX_DIO_PAD_ATTR_27_SCHMITT_EN_27_BIT 5

#define	PINMUX_DIO_PAD_ATTR_27_OD_EN_27_BIT 6

#define	PINMUX_DIO_PAD_ATTR_27_INPUT_DISABLE_27_BIT 7

#define	PINMUX_DIO_PAD_ATTR_27_SLEW_RATE_27_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_27_SLEW_RATE_27_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_27_SLEW_RATE_27_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_27_SLEW_RATE_27_MASK, .index = PINMUX_DIO_PAD_ATTR_27_SLEW_RATE_27_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_27_DRIVE_STRENGTH_27_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_27_DRIVE_STRENGTH_27_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_27_DRIVE_STRENGTH_27_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_27_DRIVE_STRENGTH_27_MASK, .index = PINMUX_DIO_PAD_ATTR_27_DRIVE_STRENGTH_27_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_28_REG_OFFSET 0x278

#define	PINMUX_DIO_PAD_ATTR_28_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_28_INVERT_28_BIT 0

#define	PINMUX_DIO_PAD_ATTR_28_VIRTUAL_OD_EN_28_BIT 1

#define	PINMUX_DIO_PAD_ATTR_28_PULL_EN_28_BIT 2

#define	PINMUX_DIO_PAD_ATTR_28_PULL_SELECT_28_BIT 3

#define	PINMUX_DIO_PAD_ATTR_28_KEEPER_EN_28_BIT 4

#define	PINMUX_DIO_PAD_ATTR_28_SCHMITT_EN_28_BIT 5

#define	PINMUX_DIO_PAD_ATTR_28_OD_EN_28_BIT 6

#define	PINMUX_DIO_PAD_ATTR_28_INPUT_DISABLE_28_BIT 7

#define	PINMUX_DIO_PAD_ATTR_28_SLEW_RATE_28_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_28_SLEW_RATE_28_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_28_SLEW_RATE_28_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_28_SLEW_RATE_28_MASK, .index = PINMUX_DIO_PAD_ATTR_28_SLEW_RATE_28_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_28_DRIVE_STRENGTH_28_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_28_DRIVE_STRENGTH_28_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_28_DRIVE_STRENGTH_28_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_28_DRIVE_STRENGTH_28_MASK, .index = PINMUX_DIO_PAD_ATTR_28_DRIVE_STRENGTH_28_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_29_REG_OFFSET 0x27c

#define	PINMUX_DIO_PAD_ATTR_29_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_29_INVERT_29_BIT 0

#define	PINMUX_DIO_PAD_ATTR_29_VIRTUAL_OD_EN_29_BIT 1

#define	PINMUX_DIO_PAD_ATTR_29_PULL_EN_29_BIT 2

#define	PINMUX_DIO_PAD_ATTR_29_PULL_SELECT_29_BIT 3

#define	PINMUX_DIO_PAD_ATTR_29_KEEPER_EN_29_BIT 4

#define	PINMUX_DIO_PAD_ATTR_29_SCHMITT_EN_29_BIT 5

#define	PINMUX_DIO_PAD_ATTR_29_OD_EN_29_BIT 6

#define	PINMUX_DIO_PAD_ATTR_29_INPUT_DISABLE_29_BIT 7

#define	PINMUX_DIO_PAD_ATTR_29_SLEW_RATE_29_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_29_SLEW_RATE_29_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_29_SLEW_RATE_29_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_29_SLEW_RATE_29_MASK, .index = PINMUX_DIO_PAD_ATTR_29_SLEW_RATE_29_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_29_DRIVE_STRENGTH_29_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_29_DRIVE_STRENGTH_29_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_29_DRIVE_STRENGTH_29_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_29_DRIVE_STRENGTH_29_MASK, .index = PINMUX_DIO_PAD_ATTR_29_DRIVE_STRENGTH_29_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_30_REG_OFFSET 0x280

#define	PINMUX_DIO_PAD_ATTR_30_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_30_INVERT_30_BIT 0

#define	PINMUX_DIO_PAD_ATTR_30_VIRTUAL_OD_EN_30_BIT 1

#define	PINMUX_DIO_PAD_ATTR_30_PULL_EN_30_BIT 2

#define	PINMUX_DIO_PAD_ATTR_30_PULL_SELECT_30_BIT 3

#define	PINMUX_DIO_PAD_ATTR_30_KEEPER_EN_30_BIT 4

#define	PINMUX_DIO_PAD_ATTR_30_SCHMITT_EN_30_BIT 5

#define	PINMUX_DIO_PAD_ATTR_30_OD_EN_30_BIT 6

#define	PINMUX_DIO_PAD_ATTR_30_INPUT_DISABLE_30_BIT 7

#define	PINMUX_DIO_PAD_ATTR_30_SLEW_RATE_30_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_30_SLEW_RATE_30_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_30_SLEW_RATE_30_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_30_SLEW_RATE_30_MASK, .index = PINMUX_DIO_PAD_ATTR_30_SLEW_RATE_30_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_30_DRIVE_STRENGTH_30_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_30_DRIVE_STRENGTH_30_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_30_DRIVE_STRENGTH_30_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_30_DRIVE_STRENGTH_30_MASK, .index = PINMUX_DIO_PAD_ATTR_30_DRIVE_STRENGTH_30_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_31_REG_OFFSET 0x284

#define	PINMUX_DIO_PAD_ATTR_31_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_31_INVERT_31_BIT 0

#define	PINMUX_DIO_PAD_ATTR_31_VIRTUAL_OD_EN_31_BIT 1

#define	PINMUX_DIO_PAD_ATTR_31_PULL_EN_31_BIT 2

#define	PINMUX_DIO_PAD_ATTR_31_PULL_SELECT_31_BIT 3

#define	PINMUX_DIO_PAD_ATTR_31_KEEPER_EN_31_BIT 4

#define	PINMUX_DIO_PAD_ATTR_31_SCHMITT_EN_31_BIT 5

#define	PINMUX_DIO_PAD_ATTR_31_OD_EN_31_BIT 6

#define	PINMUX_DIO_PAD_ATTR_31_INPUT_DISABLE_31_BIT 7

#define	PINMUX_DIO_PAD_ATTR_31_SLEW_RATE_31_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_31_SLEW_RATE_31_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_31_SLEW_RATE_31_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_31_SLEW_RATE_31_MASK, .index = PINMUX_DIO_PAD_ATTR_31_SLEW_RATE_31_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_31_DRIVE_STRENGTH_31_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_31_DRIVE_STRENGTH_31_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_31_DRIVE_STRENGTH_31_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_31_DRIVE_STRENGTH_31_MASK, .index = PINMUX_DIO_PAD_ATTR_31_DRIVE_STRENGTH_31_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_32_REG_OFFSET 0x288

#define	PINMUX_DIO_PAD_ATTR_32_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_32_INVERT_32_BIT 0

#define	PINMUX_DIO_PAD_ATTR_32_VIRTUAL_OD_EN_32_BIT 1

#define	PINMUX_DIO_PAD_ATTR_32_PULL_EN_32_BIT 2

#define	PINMUX_DIO_PAD_ATTR_32_PULL_SELECT_32_BIT 3

#define	PINMUX_DIO_PAD_ATTR_32_KEEPER_EN_32_BIT 4

#define	PINMUX_DIO_PAD_ATTR_32_SCHMITT_EN_32_BIT 5

#define	PINMUX_DIO_PAD_ATTR_32_OD_EN_32_BIT 6

#define	PINMUX_DIO_PAD_ATTR_32_INPUT_DISABLE_32_BIT 7

#define	PINMUX_DIO_PAD_ATTR_32_SLEW_RATE_32_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_32_SLEW_RATE_32_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_32_SLEW_RATE_32_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_32_SLEW_RATE_32_MASK, .index = PINMUX_DIO_PAD_ATTR_32_SLEW_RATE_32_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_32_DRIVE_STRENGTH_32_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_32_DRIVE_STRENGTH_32_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_32_DRIVE_STRENGTH_32_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_32_DRIVE_STRENGTH_32_MASK, .index = PINMUX_DIO_PAD_ATTR_32_DRIVE_STRENGTH_32_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_33_REG_OFFSET 0x28c

#define	PINMUX_DIO_PAD_ATTR_33_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_33_INVERT_33_BIT 0

#define	PINMUX_DIO_PAD_ATTR_33_VIRTUAL_OD_EN_33_BIT 1

#define	PINMUX_DIO_PAD_ATTR_33_PULL_EN_33_BIT 2

#define	PINMUX_DIO_PAD_ATTR_33_PULL_SELECT_33_BIT 3

#define	PINMUX_DIO_PAD_ATTR_33_KEEPER_EN_33_BIT 4

#define	PINMUX_DIO_PAD_ATTR_33_SCHMITT_EN_33_BIT 5

#define	PINMUX_DIO_PAD_ATTR_33_OD_EN_33_BIT 6

#define	PINMUX_DIO_PAD_ATTR_33_INPUT_DISABLE_33_BIT 7

#define	PINMUX_DIO_PAD_ATTR_33_SLEW_RATE_33_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_33_SLEW_RATE_33_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_33_SLEW_RATE_33_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_33_SLEW_RATE_33_MASK, .index = PINMUX_DIO_PAD_ATTR_33_SLEW_RATE_33_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_33_DRIVE_STRENGTH_33_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_33_DRIVE_STRENGTH_33_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_33_DRIVE_STRENGTH_33_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_33_DRIVE_STRENGTH_33_MASK, .index = PINMUX_DIO_PAD_ATTR_33_DRIVE_STRENGTH_33_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_34_REG_OFFSET 0x290

#define	PINMUX_DIO_PAD_ATTR_34_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_34_INVERT_34_BIT 0

#define	PINMUX_DIO_PAD_ATTR_34_VIRTUAL_OD_EN_34_BIT 1

#define	PINMUX_DIO_PAD_ATTR_34_PULL_EN_34_BIT 2

#define	PINMUX_DIO_PAD_ATTR_34_PULL_SELECT_34_BIT 3

#define	PINMUX_DIO_PAD_ATTR_34_KEEPER_EN_34_BIT 4

#define	PINMUX_DIO_PAD_ATTR_34_SCHMITT_EN_34_BIT 5

#define	PINMUX_DIO_PAD_ATTR_34_OD_EN_34_BIT 6

#define	PINMUX_DIO_PAD_ATTR_34_INPUT_DISABLE_34_BIT 7

#define	PINMUX_DIO_PAD_ATTR_34_SLEW_RATE_34_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_34_SLEW_RATE_34_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_34_SLEW_RATE_34_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_34_SLEW_RATE_34_MASK, .index = PINMUX_DIO_PAD_ATTR_34_SLEW_RATE_34_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_34_DRIVE_STRENGTH_34_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_34_DRIVE_STRENGTH_34_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_34_DRIVE_STRENGTH_34_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_34_DRIVE_STRENGTH_34_MASK, .index = PINMUX_DIO_PAD_ATTR_34_DRIVE_STRENGTH_34_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_35_REG_OFFSET 0x294

#define	PINMUX_DIO_PAD_ATTR_35_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_35_INVERT_35_BIT 0

#define	PINMUX_DIO_PAD_ATTR_35_VIRTUAL_OD_EN_35_BIT 1

#define	PINMUX_DIO_PAD_ATTR_35_PULL_EN_35_BIT 2

#define	PINMUX_DIO_PAD_ATTR_35_PULL_SELECT_35_BIT 3

#define	PINMUX_DIO_PAD_ATTR_35_KEEPER_EN_35_BIT 4

#define	PINMUX_DIO_PAD_ATTR_35_SCHMITT_EN_35_BIT 5

#define	PINMUX_DIO_PAD_ATTR_35_OD_EN_35_BIT 6

#define	PINMUX_DIO_PAD_ATTR_35_INPUT_DISABLE_35_BIT 7

#define	PINMUX_DIO_PAD_ATTR_35_SLEW_RATE_35_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_35_SLEW_RATE_35_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_35_SLEW_RATE_35_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_35_SLEW_RATE_35_MASK, .index = PINMUX_DIO_PAD_ATTR_35_SLEW_RATE_35_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_35_DRIVE_STRENGTH_35_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_35_DRIVE_STRENGTH_35_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_35_DRIVE_STRENGTH_35_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_35_DRIVE_STRENGTH_35_MASK, .index = PINMUX_DIO_PAD_ATTR_35_DRIVE_STRENGTH_35_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_36_REG_OFFSET 0x298

#define	PINMUX_DIO_PAD_ATTR_36_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_36_INVERT_36_BIT 0

#define	PINMUX_DIO_PAD_ATTR_36_VIRTUAL_OD_EN_36_BIT 1

#define	PINMUX_DIO_PAD_ATTR_36_PULL_EN_36_BIT 2

#define	PINMUX_DIO_PAD_ATTR_36_PULL_SELECT_36_BIT 3

#define	PINMUX_DIO_PAD_ATTR_36_KEEPER_EN_36_BIT 4

#define	PINMUX_DIO_PAD_ATTR_36_SCHMITT_EN_36_BIT 5

#define	PINMUX_DIO_PAD_ATTR_36_OD_EN_36_BIT 6

#define	PINMUX_DIO_PAD_ATTR_36_INPUT_DISABLE_36_BIT 7

#define	PINMUX_DIO_PAD_ATTR_36_SLEW_RATE_36_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_36_SLEW_RATE_36_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_36_SLEW_RATE_36_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_36_SLEW_RATE_36_MASK, .index = PINMUX_DIO_PAD_ATTR_36_SLEW_RATE_36_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_36_DRIVE_STRENGTH_36_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_36_DRIVE_STRENGTH_36_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_36_DRIVE_STRENGTH_36_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_36_DRIVE_STRENGTH_36_MASK, .index = PINMUX_DIO_PAD_ATTR_36_DRIVE_STRENGTH_36_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_37_REG_OFFSET 0x29c

#define	PINMUX_DIO_PAD_ATTR_37_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_37_INVERT_37_BIT 0

#define	PINMUX_DIO_PAD_ATTR_37_VIRTUAL_OD_EN_37_BIT 1

#define	PINMUX_DIO_PAD_ATTR_37_PULL_EN_37_BIT 2

#define	PINMUX_DIO_PAD_ATTR_37_PULL_SELECT_37_BIT 3

#define	PINMUX_DIO_PAD_ATTR_37_KEEPER_EN_37_BIT 4

#define	PINMUX_DIO_PAD_ATTR_37_SCHMITT_EN_37_BIT 5

#define	PINMUX_DIO_PAD_ATTR_37_OD_EN_37_BIT 6

#define	PINMUX_DIO_PAD_ATTR_37_INPUT_DISABLE_37_BIT 7

#define	PINMUX_DIO_PAD_ATTR_37_SLEW_RATE_37_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_37_SLEW_RATE_37_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_37_SLEW_RATE_37_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_37_SLEW_RATE_37_MASK, .index = PINMUX_DIO_PAD_ATTR_37_SLEW_RATE_37_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_37_DRIVE_STRENGTH_37_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_37_DRIVE_STRENGTH_37_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_37_DRIVE_STRENGTH_37_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_37_DRIVE_STRENGTH_37_MASK, .index = PINMUX_DIO_PAD_ATTR_37_DRIVE_STRENGTH_37_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_38_REG_OFFSET 0x2a0

#define	PINMUX_DIO_PAD_ATTR_38_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_38_INVERT_38_BIT 0

#define	PINMUX_DIO_PAD_ATTR_38_VIRTUAL_OD_EN_38_BIT 1

#define	PINMUX_DIO_PAD_ATTR_38_PULL_EN_38_BIT 2

#define	PINMUX_DIO_PAD_ATTR_38_PULL_SELECT_38_BIT 3

#define	PINMUX_DIO_PAD_ATTR_38_KEEPER_EN_38_BIT 4

#define	PINMUX_DIO_PAD_ATTR_38_SCHMITT_EN_38_BIT 5

#define	PINMUX_DIO_PAD_ATTR_38_OD_EN_38_BIT 6

#define	PINMUX_DIO_PAD_ATTR_38_INPUT_DISABLE_38_BIT 7

#define	PINMUX_DIO_PAD_ATTR_38_SLEW_RATE_38_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_38_SLEW_RATE_38_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_38_SLEW_RATE_38_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_38_SLEW_RATE_38_MASK, .index = PINMUX_DIO_PAD_ATTR_38_SLEW_RATE_38_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_38_DRIVE_STRENGTH_38_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_38_DRIVE_STRENGTH_38_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_38_DRIVE_STRENGTH_38_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_38_DRIVE_STRENGTH_38_MASK, .index = PINMUX_DIO_PAD_ATTR_38_DRIVE_STRENGTH_38_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_39_REG_OFFSET 0x2a4

#define	PINMUX_DIO_PAD_ATTR_39_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_39_INVERT_39_BIT 0

#define	PINMUX_DIO_PAD_ATTR_39_VIRTUAL_OD_EN_39_BIT 1

#define	PINMUX_DIO_PAD_ATTR_39_PULL_EN_39_BIT 2

#define	PINMUX_DIO_PAD_ATTR_39_PULL_SELECT_39_BIT 3

#define	PINMUX_DIO_PAD_ATTR_39_KEEPER_EN_39_BIT 4

#define	PINMUX_DIO_PAD_ATTR_39_SCHMITT_EN_39_BIT 5

#define	PINMUX_DIO_PAD_ATTR_39_OD_EN_39_BIT 6

#define	PINMUX_DIO_PAD_ATTR_39_INPUT_DISABLE_39_BIT 7

#define	PINMUX_DIO_PAD_ATTR_39_SLEW_RATE_39_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_39_SLEW_RATE_39_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_39_SLEW_RATE_39_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_39_SLEW_RATE_39_MASK, .index = PINMUX_DIO_PAD_ATTR_39_SLEW_RATE_39_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_39_DRIVE_STRENGTH_39_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_39_DRIVE_STRENGTH_39_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_39_DRIVE_STRENGTH_39_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_39_DRIVE_STRENGTH_39_MASK, .index = PINMUX_DIO_PAD_ATTR_39_DRIVE_STRENGTH_39_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_40_REG_OFFSET 0x2a8

#define	PINMUX_DIO_PAD_ATTR_40_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_40_INVERT_40_BIT 0

#define	PINMUX_DIO_PAD_ATTR_40_VIRTUAL_OD_EN_40_BIT 1

#define	PINMUX_DIO_PAD_ATTR_40_PULL_EN_40_BIT 2

#define	PINMUX_DIO_PAD_ATTR_40_PULL_SELECT_40_BIT 3

#define	PINMUX_DIO_PAD_ATTR_40_KEEPER_EN_40_BIT 4

#define	PINMUX_DIO_PAD_ATTR_40_SCHMITT_EN_40_BIT 5

#define	PINMUX_DIO_PAD_ATTR_40_OD_EN_40_BIT 6

#define	PINMUX_DIO_PAD_ATTR_40_INPUT_DISABLE_40_BIT 7

#define	PINMUX_DIO_PAD_ATTR_40_SLEW_RATE_40_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_40_SLEW_RATE_40_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_40_SLEW_RATE_40_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_40_SLEW_RATE_40_MASK, .index = PINMUX_DIO_PAD_ATTR_40_SLEW_RATE_40_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_40_DRIVE_STRENGTH_40_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_40_DRIVE_STRENGTH_40_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_40_DRIVE_STRENGTH_40_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_40_DRIVE_STRENGTH_40_MASK, .index = PINMUX_DIO_PAD_ATTR_40_DRIVE_STRENGTH_40_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_41_REG_OFFSET 0x2ac

#define	PINMUX_DIO_PAD_ATTR_41_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_41_INVERT_41_BIT 0

#define	PINMUX_DIO_PAD_ATTR_41_VIRTUAL_OD_EN_41_BIT 1

#define	PINMUX_DIO_PAD_ATTR_41_PULL_EN_41_BIT 2

#define	PINMUX_DIO_PAD_ATTR_41_PULL_SELECT_41_BIT 3

#define	PINMUX_DIO_PAD_ATTR_41_KEEPER_EN_41_BIT 4

#define	PINMUX_DIO_PAD_ATTR_41_SCHMITT_EN_41_BIT 5

#define	PINMUX_DIO_PAD_ATTR_41_OD_EN_41_BIT 6

#define	PINMUX_DIO_PAD_ATTR_41_INPUT_DISABLE_41_BIT 7

#define	PINMUX_DIO_PAD_ATTR_41_SLEW_RATE_41_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_41_SLEW_RATE_41_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_41_SLEW_RATE_41_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_41_SLEW_RATE_41_MASK, .index = PINMUX_DIO_PAD_ATTR_41_SLEW_RATE_41_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_41_DRIVE_STRENGTH_41_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_41_DRIVE_STRENGTH_41_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_41_DRIVE_STRENGTH_41_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_41_DRIVE_STRENGTH_41_MASK, .index = PINMUX_DIO_PAD_ATTR_41_DRIVE_STRENGTH_41_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_42_REG_OFFSET 0x2b0

#define	PINMUX_DIO_PAD_ATTR_42_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_42_INVERT_42_BIT 0

#define	PINMUX_DIO_PAD_ATTR_42_VIRTUAL_OD_EN_42_BIT 1

#define	PINMUX_DIO_PAD_ATTR_42_PULL_EN_42_BIT 2

#define	PINMUX_DIO_PAD_ATTR_42_PULL_SELECT_42_BIT 3

#define	PINMUX_DIO_PAD_ATTR_42_KEEPER_EN_42_BIT 4

#define	PINMUX_DIO_PAD_ATTR_42_SCHMITT_EN_42_BIT 5

#define	PINMUX_DIO_PAD_ATTR_42_OD_EN_42_BIT 6

#define	PINMUX_DIO_PAD_ATTR_42_INPUT_DISABLE_42_BIT 7

#define	PINMUX_DIO_PAD_ATTR_42_SLEW_RATE_42_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_42_SLEW_RATE_42_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_42_SLEW_RATE_42_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_42_SLEW_RATE_42_MASK, .index = PINMUX_DIO_PAD_ATTR_42_SLEW_RATE_42_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_42_DRIVE_STRENGTH_42_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_42_DRIVE_STRENGTH_42_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_42_DRIVE_STRENGTH_42_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_42_DRIVE_STRENGTH_42_MASK, .index = PINMUX_DIO_PAD_ATTR_42_DRIVE_STRENGTH_42_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_43_REG_OFFSET 0x2b4

#define	PINMUX_DIO_PAD_ATTR_43_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_43_INVERT_43_BIT 0

#define	PINMUX_DIO_PAD_ATTR_43_VIRTUAL_OD_EN_43_BIT 1

#define	PINMUX_DIO_PAD_ATTR_43_PULL_EN_43_BIT 2

#define	PINMUX_DIO_PAD_ATTR_43_PULL_SELECT_43_BIT 3

#define	PINMUX_DIO_PAD_ATTR_43_KEEPER_EN_43_BIT 4

#define	PINMUX_DIO_PAD_ATTR_43_SCHMITT_EN_43_BIT 5

#define	PINMUX_DIO_PAD_ATTR_43_OD_EN_43_BIT 6

#define	PINMUX_DIO_PAD_ATTR_43_INPUT_DISABLE_43_BIT 7

#define	PINMUX_DIO_PAD_ATTR_43_SLEW_RATE_43_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_43_SLEW_RATE_43_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_43_SLEW_RATE_43_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_43_SLEW_RATE_43_MASK, .index = PINMUX_DIO_PAD_ATTR_43_SLEW_RATE_43_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_43_DRIVE_STRENGTH_43_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_43_DRIVE_STRENGTH_43_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_43_DRIVE_STRENGTH_43_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_43_DRIVE_STRENGTH_43_MASK, .index = PINMUX_DIO_PAD_ATTR_43_DRIVE_STRENGTH_43_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_44_REG_OFFSET 0x2b8

#define	PINMUX_DIO_PAD_ATTR_44_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_44_INVERT_44_BIT 0

#define	PINMUX_DIO_PAD_ATTR_44_VIRTUAL_OD_EN_44_BIT 1

#define	PINMUX_DIO_PAD_ATTR_44_PULL_EN_44_BIT 2

#define	PINMUX_DIO_PAD_ATTR_44_PULL_SELECT_44_BIT 3

#define	PINMUX_DIO_PAD_ATTR_44_KEEPER_EN_44_BIT 4

#define	PINMUX_DIO_PAD_ATTR_44_SCHMITT_EN_44_BIT 5

#define	PINMUX_DIO_PAD_ATTR_44_OD_EN_44_BIT 6

#define	PINMUX_DIO_PAD_ATTR_44_INPUT_DISABLE_44_BIT 7

#define	PINMUX_DIO_PAD_ATTR_44_SLEW_RATE_44_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_44_SLEW_RATE_44_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_44_SLEW_RATE_44_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_44_SLEW_RATE_44_MASK, .index = PINMUX_DIO_PAD_ATTR_44_SLEW_RATE_44_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_44_DRIVE_STRENGTH_44_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_44_DRIVE_STRENGTH_44_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_44_DRIVE_STRENGTH_44_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_44_DRIVE_STRENGTH_44_MASK, .index = PINMUX_DIO_PAD_ATTR_44_DRIVE_STRENGTH_44_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_45_REG_OFFSET 0x2bc

#define	PINMUX_DIO_PAD_ATTR_45_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_45_INVERT_45_BIT 0

#define	PINMUX_DIO_PAD_ATTR_45_VIRTUAL_OD_EN_45_BIT 1

#define	PINMUX_DIO_PAD_ATTR_45_PULL_EN_45_BIT 2

#define	PINMUX_DIO_PAD_ATTR_45_PULL_SELECT_45_BIT 3

#define	PINMUX_DIO_PAD_ATTR_45_KEEPER_EN_45_BIT 4

#define	PINMUX_DIO_PAD_ATTR_45_SCHMITT_EN_45_BIT 5

#define	PINMUX_DIO_PAD_ATTR_45_OD_EN_45_BIT 6

#define	PINMUX_DIO_PAD_ATTR_45_INPUT_DISABLE_45_BIT 7

#define	PINMUX_DIO_PAD_ATTR_45_SLEW_RATE_45_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_45_SLEW_RATE_45_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_45_SLEW_RATE_45_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_45_SLEW_RATE_45_MASK, .index = PINMUX_DIO_PAD_ATTR_45_SLEW_RATE_45_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_45_DRIVE_STRENGTH_45_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_45_DRIVE_STRENGTH_45_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_45_DRIVE_STRENGTH_45_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_45_DRIVE_STRENGTH_45_MASK, .index = PINMUX_DIO_PAD_ATTR_45_DRIVE_STRENGTH_45_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_46_REG_OFFSET 0x2c0

#define	PINMUX_DIO_PAD_ATTR_46_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_46_INVERT_46_BIT 0

#define	PINMUX_DIO_PAD_ATTR_46_VIRTUAL_OD_EN_46_BIT 1

#define	PINMUX_DIO_PAD_ATTR_46_PULL_EN_46_BIT 2

#define	PINMUX_DIO_PAD_ATTR_46_PULL_SELECT_46_BIT 3

#define	PINMUX_DIO_PAD_ATTR_46_KEEPER_EN_46_BIT 4

#define	PINMUX_DIO_PAD_ATTR_46_SCHMITT_EN_46_BIT 5

#define	PINMUX_DIO_PAD_ATTR_46_OD_EN_46_BIT 6

#define	PINMUX_DIO_PAD_ATTR_46_INPUT_DISABLE_46_BIT 7

#define	PINMUX_DIO_PAD_ATTR_46_SLEW_RATE_46_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_46_SLEW_RATE_46_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_46_SLEW_RATE_46_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_46_SLEW_RATE_46_MASK, .index = PINMUX_DIO_PAD_ATTR_46_SLEW_RATE_46_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_46_DRIVE_STRENGTH_46_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_46_DRIVE_STRENGTH_46_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_46_DRIVE_STRENGTH_46_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_46_DRIVE_STRENGTH_46_MASK, .index = PINMUX_DIO_PAD_ATTR_46_DRIVE_STRENGTH_46_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_47_REG_OFFSET 0x2c4

#define	PINMUX_DIO_PAD_ATTR_47_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_47_INVERT_47_BIT 0

#define	PINMUX_DIO_PAD_ATTR_47_VIRTUAL_OD_EN_47_BIT 1

#define	PINMUX_DIO_PAD_ATTR_47_PULL_EN_47_BIT 2

#define	PINMUX_DIO_PAD_ATTR_47_PULL_SELECT_47_BIT 3

#define	PINMUX_DIO_PAD_ATTR_47_KEEPER_EN_47_BIT 4

#define	PINMUX_DIO_PAD_ATTR_47_SCHMITT_EN_47_BIT 5

#define	PINMUX_DIO_PAD_ATTR_47_OD_EN_47_BIT 6

#define	PINMUX_DIO_PAD_ATTR_47_INPUT_DISABLE_47_BIT 7

#define	PINMUX_DIO_PAD_ATTR_47_SLEW_RATE_47_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_47_SLEW_RATE_47_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_47_SLEW_RATE_47_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_47_SLEW_RATE_47_MASK, .index = PINMUX_DIO_PAD_ATTR_47_SLEW_RATE_47_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_47_DRIVE_STRENGTH_47_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_47_DRIVE_STRENGTH_47_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_47_DRIVE_STRENGTH_47_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_47_DRIVE_STRENGTH_47_MASK, .index = PINMUX_DIO_PAD_ATTR_47_DRIVE_STRENGTH_47_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_48_REG_OFFSET 0x2c8

#define	PINMUX_DIO_PAD_ATTR_48_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_48_INVERT_48_BIT 0

#define	PINMUX_DIO_PAD_ATTR_48_VIRTUAL_OD_EN_48_BIT 1

#define	PINMUX_DIO_PAD_ATTR_48_PULL_EN_48_BIT 2

#define	PINMUX_DIO_PAD_ATTR_48_PULL_SELECT_48_BIT 3

#define	PINMUX_DIO_PAD_ATTR_48_KEEPER_EN_48_BIT 4

#define	PINMUX_DIO_PAD_ATTR_48_SCHMITT_EN_48_BIT 5

#define	PINMUX_DIO_PAD_ATTR_48_OD_EN_48_BIT 6

#define	PINMUX_DIO_PAD_ATTR_48_INPUT_DISABLE_48_BIT 7

#define	PINMUX_DIO_PAD_ATTR_48_SLEW_RATE_48_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_48_SLEW_RATE_48_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_48_SLEW_RATE_48_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_48_SLEW_RATE_48_MASK, .index = PINMUX_DIO_PAD_ATTR_48_SLEW_RATE_48_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_48_DRIVE_STRENGTH_48_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_48_DRIVE_STRENGTH_48_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_48_DRIVE_STRENGTH_48_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_48_DRIVE_STRENGTH_48_MASK, .index = PINMUX_DIO_PAD_ATTR_48_DRIVE_STRENGTH_48_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_49_REG_OFFSET 0x2cc

#define	PINMUX_DIO_PAD_ATTR_49_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_49_INVERT_49_BIT 0

#define	PINMUX_DIO_PAD_ATTR_49_VIRTUAL_OD_EN_49_BIT 1

#define	PINMUX_DIO_PAD_ATTR_49_PULL_EN_49_BIT 2

#define	PINMUX_DIO_PAD_ATTR_49_PULL_SELECT_49_BIT 3

#define	PINMUX_DIO_PAD_ATTR_49_KEEPER_EN_49_BIT 4

#define	PINMUX_DIO_PAD_ATTR_49_SCHMITT_EN_49_BIT 5

#define	PINMUX_DIO_PAD_ATTR_49_OD_EN_49_BIT 6

#define	PINMUX_DIO_PAD_ATTR_49_INPUT_DISABLE_49_BIT 7

#define	PINMUX_DIO_PAD_ATTR_49_SLEW_RATE_49_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_49_SLEW_RATE_49_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_49_SLEW_RATE_49_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_49_SLEW_RATE_49_MASK, .index = PINMUX_DIO_PAD_ATTR_49_SLEW_RATE_49_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_49_DRIVE_STRENGTH_49_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_49_DRIVE_STRENGTH_49_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_49_DRIVE_STRENGTH_49_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_49_DRIVE_STRENGTH_49_MASK, .index = PINMUX_DIO_PAD_ATTR_49_DRIVE_STRENGTH_49_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_50_REG_OFFSET 0x2d0

#define	PINMUX_DIO_PAD_ATTR_50_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_50_INVERT_50_BIT 0

#define	PINMUX_DIO_PAD_ATTR_50_VIRTUAL_OD_EN_50_BIT 1

#define	PINMUX_DIO_PAD_ATTR_50_PULL_EN_50_BIT 2

#define	PINMUX_DIO_PAD_ATTR_50_PULL_SELECT_50_BIT 3

#define	PINMUX_DIO_PAD_ATTR_50_KEEPER_EN_50_BIT 4

#define	PINMUX_DIO_PAD_ATTR_50_SCHMITT_EN_50_BIT 5

#define	PINMUX_DIO_PAD_ATTR_50_OD_EN_50_BIT 6

#define	PINMUX_DIO_PAD_ATTR_50_INPUT_DISABLE_50_BIT 7

#define	PINMUX_DIO_PAD_ATTR_50_SLEW_RATE_50_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_50_SLEW_RATE_50_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_50_SLEW_RATE_50_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_50_SLEW_RATE_50_MASK, .index = PINMUX_DIO_PAD_ATTR_50_SLEW_RATE_50_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_50_DRIVE_STRENGTH_50_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_50_DRIVE_STRENGTH_50_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_50_DRIVE_STRENGTH_50_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_50_DRIVE_STRENGTH_50_MASK, .index = PINMUX_DIO_PAD_ATTR_50_DRIVE_STRENGTH_50_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_51_REG_OFFSET 0x2d4

#define	PINMUX_DIO_PAD_ATTR_51_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_51_INVERT_51_BIT 0

#define	PINMUX_DIO_PAD_ATTR_51_VIRTUAL_OD_EN_51_BIT 1

#define	PINMUX_DIO_PAD_ATTR_51_PULL_EN_51_BIT 2

#define	PINMUX_DIO_PAD_ATTR_51_PULL_SELECT_51_BIT 3

#define	PINMUX_DIO_PAD_ATTR_51_KEEPER_EN_51_BIT 4

#define	PINMUX_DIO_PAD_ATTR_51_SCHMITT_EN_51_BIT 5

#define	PINMUX_DIO_PAD_ATTR_51_OD_EN_51_BIT 6

#define	PINMUX_DIO_PAD_ATTR_51_INPUT_DISABLE_51_BIT 7

#define	PINMUX_DIO_PAD_ATTR_51_SLEW_RATE_51_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_51_SLEW_RATE_51_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_51_SLEW_RATE_51_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_51_SLEW_RATE_51_MASK, .index = PINMUX_DIO_PAD_ATTR_51_SLEW_RATE_51_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_51_DRIVE_STRENGTH_51_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_51_DRIVE_STRENGTH_51_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_51_DRIVE_STRENGTH_51_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_51_DRIVE_STRENGTH_51_MASK, .index = PINMUX_DIO_PAD_ATTR_51_DRIVE_STRENGTH_51_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_52_REG_OFFSET 0x2d8

#define	PINMUX_DIO_PAD_ATTR_52_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_52_INVERT_52_BIT 0

#define	PINMUX_DIO_PAD_ATTR_52_VIRTUAL_OD_EN_52_BIT 1

#define	PINMUX_DIO_PAD_ATTR_52_PULL_EN_52_BIT 2

#define	PINMUX_DIO_PAD_ATTR_52_PULL_SELECT_52_BIT 3

#define	PINMUX_DIO_PAD_ATTR_52_KEEPER_EN_52_BIT 4

#define	PINMUX_DIO_PAD_ATTR_52_SCHMITT_EN_52_BIT 5

#define	PINMUX_DIO_PAD_ATTR_52_OD_EN_52_BIT 6

#define	PINMUX_DIO_PAD_ATTR_52_INPUT_DISABLE_52_BIT 7

#define	PINMUX_DIO_PAD_ATTR_52_SLEW_RATE_52_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_52_SLEW_RATE_52_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_52_SLEW_RATE_52_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_52_SLEW_RATE_52_MASK, .index = PINMUX_DIO_PAD_ATTR_52_SLEW_RATE_52_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_52_DRIVE_STRENGTH_52_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_52_DRIVE_STRENGTH_52_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_52_DRIVE_STRENGTH_52_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_52_DRIVE_STRENGTH_52_MASK, .index = PINMUX_DIO_PAD_ATTR_52_DRIVE_STRENGTH_52_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_53_REG_OFFSET 0x2dc

#define	PINMUX_DIO_PAD_ATTR_53_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_53_INVERT_53_BIT 0

#define	PINMUX_DIO_PAD_ATTR_53_VIRTUAL_OD_EN_53_BIT 1

#define	PINMUX_DIO_PAD_ATTR_53_PULL_EN_53_BIT 2

#define	PINMUX_DIO_PAD_ATTR_53_PULL_SELECT_53_BIT 3

#define	PINMUX_DIO_PAD_ATTR_53_KEEPER_EN_53_BIT 4

#define	PINMUX_DIO_PAD_ATTR_53_SCHMITT_EN_53_BIT 5

#define	PINMUX_DIO_PAD_ATTR_53_OD_EN_53_BIT 6

#define	PINMUX_DIO_PAD_ATTR_53_INPUT_DISABLE_53_BIT 7

#define	PINMUX_DIO_PAD_ATTR_53_SLEW_RATE_53_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_53_SLEW_RATE_53_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_53_SLEW_RATE_53_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_53_SLEW_RATE_53_MASK, .index = PINMUX_DIO_PAD_ATTR_53_SLEW_RATE_53_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_53_DRIVE_STRENGTH_53_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_53_DRIVE_STRENGTH_53_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_53_DRIVE_STRENGTH_53_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_53_DRIVE_STRENGTH_53_MASK, .index = PINMUX_DIO_PAD_ATTR_53_DRIVE_STRENGTH_53_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_54_REG_OFFSET 0x2e0

#define	PINMUX_DIO_PAD_ATTR_54_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_54_INVERT_54_BIT 0

#define	PINMUX_DIO_PAD_ATTR_54_VIRTUAL_OD_EN_54_BIT 1

#define	PINMUX_DIO_PAD_ATTR_54_PULL_EN_54_BIT 2

#define	PINMUX_DIO_PAD_ATTR_54_PULL_SELECT_54_BIT 3

#define	PINMUX_DIO_PAD_ATTR_54_KEEPER_EN_54_BIT 4

#define	PINMUX_DIO_PAD_ATTR_54_SCHMITT_EN_54_BIT 5

#define	PINMUX_DIO_PAD_ATTR_54_OD_EN_54_BIT 6

#define	PINMUX_DIO_PAD_ATTR_54_INPUT_DISABLE_54_BIT 7

#define	PINMUX_DIO_PAD_ATTR_54_SLEW_RATE_54_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_54_SLEW_RATE_54_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_54_SLEW_RATE_54_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_54_SLEW_RATE_54_MASK, .index = PINMUX_DIO_PAD_ATTR_54_SLEW_RATE_54_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_54_DRIVE_STRENGTH_54_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_54_DRIVE_STRENGTH_54_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_54_DRIVE_STRENGTH_54_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_54_DRIVE_STRENGTH_54_MASK, .index = PINMUX_DIO_PAD_ATTR_54_DRIVE_STRENGTH_54_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_55_REG_OFFSET 0x2e4

#define	PINMUX_DIO_PAD_ATTR_55_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_55_INVERT_55_BIT 0

#define	PINMUX_DIO_PAD_ATTR_55_VIRTUAL_OD_EN_55_BIT 1

#define	PINMUX_DIO_PAD_ATTR_55_PULL_EN_55_BIT 2

#define	PINMUX_DIO_PAD_ATTR_55_PULL_SELECT_55_BIT 3

#define	PINMUX_DIO_PAD_ATTR_55_KEEPER_EN_55_BIT 4

#define	PINMUX_DIO_PAD_ATTR_55_SCHMITT_EN_55_BIT 5

#define	PINMUX_DIO_PAD_ATTR_55_OD_EN_55_BIT 6

#define	PINMUX_DIO_PAD_ATTR_55_INPUT_DISABLE_55_BIT 7

#define	PINMUX_DIO_PAD_ATTR_55_SLEW_RATE_55_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_55_SLEW_RATE_55_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_55_SLEW_RATE_55_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_55_SLEW_RATE_55_MASK, .index = PINMUX_DIO_PAD_ATTR_55_SLEW_RATE_55_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_55_DRIVE_STRENGTH_55_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_55_DRIVE_STRENGTH_55_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_55_DRIVE_STRENGTH_55_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_55_DRIVE_STRENGTH_55_MASK, .index = PINMUX_DIO_PAD_ATTR_55_DRIVE_STRENGTH_55_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_56_REG_OFFSET 0x2e8

#define	PINMUX_DIO_PAD_ATTR_56_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_56_INVERT_56_BIT 0

#define	PINMUX_DIO_PAD_ATTR_56_VIRTUAL_OD_EN_56_BIT 1

#define	PINMUX_DIO_PAD_ATTR_56_PULL_EN_56_BIT 2

#define	PINMUX_DIO_PAD_ATTR_56_PULL_SELECT_56_BIT 3

#define	PINMUX_DIO_PAD_ATTR_56_KEEPER_EN_56_BIT 4

#define	PINMUX_DIO_PAD_ATTR_56_SCHMITT_EN_56_BIT 5

#define	PINMUX_DIO_PAD_ATTR_56_OD_EN_56_BIT 6

#define	PINMUX_DIO_PAD_ATTR_56_INPUT_DISABLE_56_BIT 7

#define	PINMUX_DIO_PAD_ATTR_56_SLEW_RATE_56_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_56_SLEW_RATE_56_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_56_SLEW_RATE_56_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_56_SLEW_RATE_56_MASK, .index = PINMUX_DIO_PAD_ATTR_56_SLEW_RATE_56_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_56_DRIVE_STRENGTH_56_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_56_DRIVE_STRENGTH_56_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_56_DRIVE_STRENGTH_56_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_56_DRIVE_STRENGTH_56_MASK, .index = PINMUX_DIO_PAD_ATTR_56_DRIVE_STRENGTH_56_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_57_REG_OFFSET 0x2ec

#define	PINMUX_DIO_PAD_ATTR_57_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_57_INVERT_57_BIT 0

#define	PINMUX_DIO_PAD_ATTR_57_VIRTUAL_OD_EN_57_BIT 1

#define	PINMUX_DIO_PAD_ATTR_57_PULL_EN_57_BIT 2

#define	PINMUX_DIO_PAD_ATTR_57_PULL_SELECT_57_BIT 3

#define	PINMUX_DIO_PAD_ATTR_57_KEEPER_EN_57_BIT 4

#define	PINMUX_DIO_PAD_ATTR_57_SCHMITT_EN_57_BIT 5

#define	PINMUX_DIO_PAD_ATTR_57_OD_EN_57_BIT 6

#define	PINMUX_DIO_PAD_ATTR_57_INPUT_DISABLE_57_BIT 7

#define	PINMUX_DIO_PAD_ATTR_57_SLEW_RATE_57_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_57_SLEW_RATE_57_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_57_SLEW_RATE_57_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_57_SLEW_RATE_57_MASK, .index = PINMUX_DIO_PAD_ATTR_57_SLEW_RATE_57_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_57_DRIVE_STRENGTH_57_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_57_DRIVE_STRENGTH_57_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_57_DRIVE_STRENGTH_57_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_57_DRIVE_STRENGTH_57_MASK, .index = PINMUX_DIO_PAD_ATTR_57_DRIVE_STRENGTH_57_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_58_REG_OFFSET 0x2f0

#define	PINMUX_DIO_PAD_ATTR_58_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_58_INVERT_58_BIT 0

#define	PINMUX_DIO_PAD_ATTR_58_VIRTUAL_OD_EN_58_BIT 1

#define	PINMUX_DIO_PAD_ATTR_58_PULL_EN_58_BIT 2

#define	PINMUX_DIO_PAD_ATTR_58_PULL_SELECT_58_BIT 3

#define	PINMUX_DIO_PAD_ATTR_58_KEEPER_EN_58_BIT 4

#define	PINMUX_DIO_PAD_ATTR_58_SCHMITT_EN_58_BIT 5

#define	PINMUX_DIO_PAD_ATTR_58_OD_EN_58_BIT 6

#define	PINMUX_DIO_PAD_ATTR_58_INPUT_DISABLE_58_BIT 7

#define	PINMUX_DIO_PAD_ATTR_58_SLEW_RATE_58_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_58_SLEW_RATE_58_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_58_SLEW_RATE_58_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_58_SLEW_RATE_58_MASK, .index = PINMUX_DIO_PAD_ATTR_58_SLEW_RATE_58_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_58_DRIVE_STRENGTH_58_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_58_DRIVE_STRENGTH_58_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_58_DRIVE_STRENGTH_58_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_58_DRIVE_STRENGTH_58_MASK, .index = PINMUX_DIO_PAD_ATTR_58_DRIVE_STRENGTH_58_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_59_REG_OFFSET 0x2f4

#define	PINMUX_DIO_PAD_ATTR_59_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_59_INVERT_59_BIT 0

#define	PINMUX_DIO_PAD_ATTR_59_VIRTUAL_OD_EN_59_BIT 1

#define	PINMUX_DIO_PAD_ATTR_59_PULL_EN_59_BIT 2

#define	PINMUX_DIO_PAD_ATTR_59_PULL_SELECT_59_BIT 3

#define	PINMUX_DIO_PAD_ATTR_59_KEEPER_EN_59_BIT 4

#define	PINMUX_DIO_PAD_ATTR_59_SCHMITT_EN_59_BIT 5

#define	PINMUX_DIO_PAD_ATTR_59_OD_EN_59_BIT 6

#define	PINMUX_DIO_PAD_ATTR_59_INPUT_DISABLE_59_BIT 7

#define	PINMUX_DIO_PAD_ATTR_59_SLEW_RATE_59_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_59_SLEW_RATE_59_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_59_SLEW_RATE_59_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_59_SLEW_RATE_59_MASK, .index = PINMUX_DIO_PAD_ATTR_59_SLEW_RATE_59_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_59_DRIVE_STRENGTH_59_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_59_DRIVE_STRENGTH_59_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_59_DRIVE_STRENGTH_59_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_59_DRIVE_STRENGTH_59_MASK, .index = PINMUX_DIO_PAD_ATTR_59_DRIVE_STRENGTH_59_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_60_REG_OFFSET 0x2f8

#define	PINMUX_DIO_PAD_ATTR_60_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_60_INVERT_60_BIT 0

#define	PINMUX_DIO_PAD_ATTR_60_VIRTUAL_OD_EN_60_BIT 1

#define	PINMUX_DIO_PAD_ATTR_60_PULL_EN_60_BIT 2

#define	PINMUX_DIO_PAD_ATTR_60_PULL_SELECT_60_BIT 3

#define	PINMUX_DIO_PAD_ATTR_60_KEEPER_EN_60_BIT 4

#define	PINMUX_DIO_PAD_ATTR_60_SCHMITT_EN_60_BIT 5

#define	PINMUX_DIO_PAD_ATTR_60_OD_EN_60_BIT 6

#define	PINMUX_DIO_PAD_ATTR_60_INPUT_DISABLE_60_BIT 7

#define	PINMUX_DIO_PAD_ATTR_60_SLEW_RATE_60_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_60_SLEW_RATE_60_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_60_SLEW_RATE_60_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_60_SLEW_RATE_60_MASK, .index = PINMUX_DIO_PAD_ATTR_60_SLEW_RATE_60_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_60_DRIVE_STRENGTH_60_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_60_DRIVE_STRENGTH_60_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_60_DRIVE_STRENGTH_60_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_60_DRIVE_STRENGTH_60_MASK, .index = PINMUX_DIO_PAD_ATTR_60_DRIVE_STRENGTH_60_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_61_REG_OFFSET 0x2fc

#define	PINMUX_DIO_PAD_ATTR_61_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_61_INVERT_61_BIT 0

#define	PINMUX_DIO_PAD_ATTR_61_VIRTUAL_OD_EN_61_BIT 1

#define	PINMUX_DIO_PAD_ATTR_61_PULL_EN_61_BIT 2

#define	PINMUX_DIO_PAD_ATTR_61_PULL_SELECT_61_BIT 3

#define	PINMUX_DIO_PAD_ATTR_61_KEEPER_EN_61_BIT 4

#define	PINMUX_DIO_PAD_ATTR_61_SCHMITT_EN_61_BIT 5

#define	PINMUX_DIO_PAD_ATTR_61_OD_EN_61_BIT 6

#define	PINMUX_DIO_PAD_ATTR_61_INPUT_DISABLE_61_BIT 7

#define	PINMUX_DIO_PAD_ATTR_61_SLEW_RATE_61_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_61_SLEW_RATE_61_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_61_SLEW_RATE_61_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_61_SLEW_RATE_61_MASK, .index = PINMUX_DIO_PAD_ATTR_61_SLEW_RATE_61_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_61_DRIVE_STRENGTH_61_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_61_DRIVE_STRENGTH_61_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_61_DRIVE_STRENGTH_61_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_61_DRIVE_STRENGTH_61_MASK, .index = PINMUX_DIO_PAD_ATTR_61_DRIVE_STRENGTH_61_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_62_REG_OFFSET 0x300

#define	PINMUX_DIO_PAD_ATTR_62_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_62_INVERT_62_BIT 0

#define	PINMUX_DIO_PAD_ATTR_62_VIRTUAL_OD_EN_62_BIT 1

#define	PINMUX_DIO_PAD_ATTR_62_PULL_EN_62_BIT 2

#define	PINMUX_DIO_PAD_ATTR_62_PULL_SELECT_62_BIT 3

#define	PINMUX_DIO_PAD_ATTR_62_KEEPER_EN_62_BIT 4

#define	PINMUX_DIO_PAD_ATTR_62_SCHMITT_EN_62_BIT 5

#define	PINMUX_DIO_PAD_ATTR_62_OD_EN_62_BIT 6

#define	PINMUX_DIO_PAD_ATTR_62_INPUT_DISABLE_62_BIT 7

#define	PINMUX_DIO_PAD_ATTR_62_SLEW_RATE_62_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_62_SLEW_RATE_62_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_62_SLEW_RATE_62_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_62_SLEW_RATE_62_MASK, .index = PINMUX_DIO_PAD_ATTR_62_SLEW_RATE_62_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_62_DRIVE_STRENGTH_62_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_62_DRIVE_STRENGTH_62_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_62_DRIVE_STRENGTH_62_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_62_DRIVE_STRENGTH_62_MASK, .index = PINMUX_DIO_PAD_ATTR_62_DRIVE_STRENGTH_62_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_63_REG_OFFSET 0x304

#define	PINMUX_DIO_PAD_ATTR_63_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_63_INVERT_63_BIT 0

#define	PINMUX_DIO_PAD_ATTR_63_VIRTUAL_OD_EN_63_BIT 1

#define	PINMUX_DIO_PAD_ATTR_63_PULL_EN_63_BIT 2

#define	PINMUX_DIO_PAD_ATTR_63_PULL_SELECT_63_BIT 3

#define	PINMUX_DIO_PAD_ATTR_63_KEEPER_EN_63_BIT 4

#define	PINMUX_DIO_PAD_ATTR_63_SCHMITT_EN_63_BIT 5

#define	PINMUX_DIO_PAD_ATTR_63_OD_EN_63_BIT 6

#define	PINMUX_DIO_PAD_ATTR_63_INPUT_DISABLE_63_BIT 7

#define	PINMUX_DIO_PAD_ATTR_63_SLEW_RATE_63_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_63_SLEW_RATE_63_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_63_SLEW_RATE_63_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_63_SLEW_RATE_63_MASK, .index = PINMUX_DIO_PAD_ATTR_63_SLEW_RATE_63_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_63_DRIVE_STRENGTH_63_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_63_DRIVE_STRENGTH_63_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_63_DRIVE_STRENGTH_63_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_63_DRIVE_STRENGTH_63_MASK, .index = PINMUX_DIO_PAD_ATTR_63_DRIVE_STRENGTH_63_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_64_REG_OFFSET 0x308

#define	PINMUX_DIO_PAD_ATTR_64_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_64_INVERT_64_BIT 0

#define	PINMUX_DIO_PAD_ATTR_64_VIRTUAL_OD_EN_64_BIT 1

#define	PINMUX_DIO_PAD_ATTR_64_PULL_EN_64_BIT 2

#define	PINMUX_DIO_PAD_ATTR_64_PULL_SELECT_64_BIT 3

#define	PINMUX_DIO_PAD_ATTR_64_KEEPER_EN_64_BIT 4

#define	PINMUX_DIO_PAD_ATTR_64_SCHMITT_EN_64_BIT 5

#define	PINMUX_DIO_PAD_ATTR_64_OD_EN_64_BIT 6

#define	PINMUX_DIO_PAD_ATTR_64_INPUT_DISABLE_64_BIT 7

#define	PINMUX_DIO_PAD_ATTR_64_SLEW_RATE_64_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_64_SLEW_RATE_64_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_64_SLEW_RATE_64_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_64_SLEW_RATE_64_MASK, .index = PINMUX_DIO_PAD_ATTR_64_SLEW_RATE_64_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_64_DRIVE_STRENGTH_64_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_64_DRIVE_STRENGTH_64_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_64_DRIVE_STRENGTH_64_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_64_DRIVE_STRENGTH_64_MASK, .index = PINMUX_DIO_PAD_ATTR_64_DRIVE_STRENGTH_64_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_65_REG_OFFSET 0x30c

#define	PINMUX_DIO_PAD_ATTR_65_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_65_INVERT_65_BIT 0

#define	PINMUX_DIO_PAD_ATTR_65_VIRTUAL_OD_EN_65_BIT 1

#define	PINMUX_DIO_PAD_ATTR_65_PULL_EN_65_BIT 2

#define	PINMUX_DIO_PAD_ATTR_65_PULL_SELECT_65_BIT 3

#define	PINMUX_DIO_PAD_ATTR_65_KEEPER_EN_65_BIT 4

#define	PINMUX_DIO_PAD_ATTR_65_SCHMITT_EN_65_BIT 5

#define	PINMUX_DIO_PAD_ATTR_65_OD_EN_65_BIT 6

#define	PINMUX_DIO_PAD_ATTR_65_INPUT_DISABLE_65_BIT 7

#define	PINMUX_DIO_PAD_ATTR_65_SLEW_RATE_65_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_65_SLEW_RATE_65_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_65_SLEW_RATE_65_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_65_SLEW_RATE_65_MASK, .index = PINMUX_DIO_PAD_ATTR_65_SLEW_RATE_65_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_65_DRIVE_STRENGTH_65_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_65_DRIVE_STRENGTH_65_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_65_DRIVE_STRENGTH_65_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_65_DRIVE_STRENGTH_65_MASK, .index = PINMUX_DIO_PAD_ATTR_65_DRIVE_STRENGTH_65_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_66_REG_OFFSET 0x310

#define	PINMUX_DIO_PAD_ATTR_66_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_66_INVERT_66_BIT 0

#define	PINMUX_DIO_PAD_ATTR_66_VIRTUAL_OD_EN_66_BIT 1

#define	PINMUX_DIO_PAD_ATTR_66_PULL_EN_66_BIT 2

#define	PINMUX_DIO_PAD_ATTR_66_PULL_SELECT_66_BIT 3

#define	PINMUX_DIO_PAD_ATTR_66_KEEPER_EN_66_BIT 4

#define	PINMUX_DIO_PAD_ATTR_66_SCHMITT_EN_66_BIT 5

#define	PINMUX_DIO_PAD_ATTR_66_OD_EN_66_BIT 6

#define	PINMUX_DIO_PAD_ATTR_66_INPUT_DISABLE_66_BIT 7

#define	PINMUX_DIO_PAD_ATTR_66_SLEW_RATE_66_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_66_SLEW_RATE_66_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_66_SLEW_RATE_66_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_66_SLEW_RATE_66_MASK, .index = PINMUX_DIO_PAD_ATTR_66_SLEW_RATE_66_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_66_DRIVE_STRENGTH_66_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_66_DRIVE_STRENGTH_66_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_66_DRIVE_STRENGTH_66_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_66_DRIVE_STRENGTH_66_MASK, .index = PINMUX_DIO_PAD_ATTR_66_DRIVE_STRENGTH_66_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_67_REG_OFFSET 0x314

#define	PINMUX_DIO_PAD_ATTR_67_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_67_INVERT_67_BIT 0

#define	PINMUX_DIO_PAD_ATTR_67_VIRTUAL_OD_EN_67_BIT 1

#define	PINMUX_DIO_PAD_ATTR_67_PULL_EN_67_BIT 2

#define	PINMUX_DIO_PAD_ATTR_67_PULL_SELECT_67_BIT 3

#define	PINMUX_DIO_PAD_ATTR_67_KEEPER_EN_67_BIT 4

#define	PINMUX_DIO_PAD_ATTR_67_SCHMITT_EN_67_BIT 5

#define	PINMUX_DIO_PAD_ATTR_67_OD_EN_67_BIT 6

#define	PINMUX_DIO_PAD_ATTR_67_INPUT_DISABLE_67_BIT 7

#define	PINMUX_DIO_PAD_ATTR_67_SLEW_RATE_67_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_67_SLEW_RATE_67_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_67_SLEW_RATE_67_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_67_SLEW_RATE_67_MASK, .index = PINMUX_DIO_PAD_ATTR_67_SLEW_RATE_67_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_67_DRIVE_STRENGTH_67_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_67_DRIVE_STRENGTH_67_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_67_DRIVE_STRENGTH_67_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_67_DRIVE_STRENGTH_67_MASK, .index = PINMUX_DIO_PAD_ATTR_67_DRIVE_STRENGTH_67_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_68_REG_OFFSET 0x318

#define	PINMUX_DIO_PAD_ATTR_68_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_68_INVERT_68_BIT 0

#define	PINMUX_DIO_PAD_ATTR_68_VIRTUAL_OD_EN_68_BIT 1

#define	PINMUX_DIO_PAD_ATTR_68_PULL_EN_68_BIT 2

#define	PINMUX_DIO_PAD_ATTR_68_PULL_SELECT_68_BIT 3

#define	PINMUX_DIO_PAD_ATTR_68_KEEPER_EN_68_BIT 4

#define	PINMUX_DIO_PAD_ATTR_68_SCHMITT_EN_68_BIT 5

#define	PINMUX_DIO_PAD_ATTR_68_OD_EN_68_BIT 6

#define	PINMUX_DIO_PAD_ATTR_68_INPUT_DISABLE_68_BIT 7

#define	PINMUX_DIO_PAD_ATTR_68_SLEW_RATE_68_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_68_SLEW_RATE_68_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_68_SLEW_RATE_68_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_68_SLEW_RATE_68_MASK, .index = PINMUX_DIO_PAD_ATTR_68_SLEW_RATE_68_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_68_DRIVE_STRENGTH_68_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_68_DRIVE_STRENGTH_68_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_68_DRIVE_STRENGTH_68_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_68_DRIVE_STRENGTH_68_MASK, .index = PINMUX_DIO_PAD_ATTR_68_DRIVE_STRENGTH_68_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_69_REG_OFFSET 0x31c

#define	PINMUX_DIO_PAD_ATTR_69_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_69_INVERT_69_BIT 0

#define	PINMUX_DIO_PAD_ATTR_69_VIRTUAL_OD_EN_69_BIT 1

#define	PINMUX_DIO_PAD_ATTR_69_PULL_EN_69_BIT 2

#define	PINMUX_DIO_PAD_ATTR_69_PULL_SELECT_69_BIT 3

#define	PINMUX_DIO_PAD_ATTR_69_KEEPER_EN_69_BIT 4

#define	PINMUX_DIO_PAD_ATTR_69_SCHMITT_EN_69_BIT 5

#define	PINMUX_DIO_PAD_ATTR_69_OD_EN_69_BIT 6

#define	PINMUX_DIO_PAD_ATTR_69_INPUT_DISABLE_69_BIT 7

#define	PINMUX_DIO_PAD_ATTR_69_SLEW_RATE_69_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_69_SLEW_RATE_69_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_69_SLEW_RATE_69_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_69_SLEW_RATE_69_MASK, .index = PINMUX_DIO_PAD_ATTR_69_SLEW_RATE_69_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_69_DRIVE_STRENGTH_69_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_69_DRIVE_STRENGTH_69_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_69_DRIVE_STRENGTH_69_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_69_DRIVE_STRENGTH_69_MASK, .index = PINMUX_DIO_PAD_ATTR_69_DRIVE_STRENGTH_69_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_70_REG_OFFSET 0x320

#define	PINMUX_DIO_PAD_ATTR_70_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_70_INVERT_70_BIT 0

#define	PINMUX_DIO_PAD_ATTR_70_VIRTUAL_OD_EN_70_BIT 1

#define	PINMUX_DIO_PAD_ATTR_70_PULL_EN_70_BIT 2

#define	PINMUX_DIO_PAD_ATTR_70_PULL_SELECT_70_BIT 3

#define	PINMUX_DIO_PAD_ATTR_70_KEEPER_EN_70_BIT 4

#define	PINMUX_DIO_PAD_ATTR_70_SCHMITT_EN_70_BIT 5

#define	PINMUX_DIO_PAD_ATTR_70_OD_EN_70_BIT 6

#define	PINMUX_DIO_PAD_ATTR_70_INPUT_DISABLE_70_BIT 7

#define	PINMUX_DIO_PAD_ATTR_70_SLEW_RATE_70_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_70_SLEW_RATE_70_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_70_SLEW_RATE_70_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_70_SLEW_RATE_70_MASK, .index = PINMUX_DIO_PAD_ATTR_70_SLEW_RATE_70_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_70_DRIVE_STRENGTH_70_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_70_DRIVE_STRENGTH_70_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_70_DRIVE_STRENGTH_70_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_70_DRIVE_STRENGTH_70_MASK, .index = PINMUX_DIO_PAD_ATTR_70_DRIVE_STRENGTH_70_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_71_REG_OFFSET 0x324

#define	PINMUX_DIO_PAD_ATTR_71_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_71_INVERT_71_BIT 0

#define	PINMUX_DIO_PAD_ATTR_71_VIRTUAL_OD_EN_71_BIT 1

#define	PINMUX_DIO_PAD_ATTR_71_PULL_EN_71_BIT 2

#define	PINMUX_DIO_PAD_ATTR_71_PULL_SELECT_71_BIT 3

#define	PINMUX_DIO_PAD_ATTR_71_KEEPER_EN_71_BIT 4

#define	PINMUX_DIO_PAD_ATTR_71_SCHMITT_EN_71_BIT 5

#define	PINMUX_DIO_PAD_ATTR_71_OD_EN_71_BIT 6

#define	PINMUX_DIO_PAD_ATTR_71_INPUT_DISABLE_71_BIT 7

#define	PINMUX_DIO_PAD_ATTR_71_SLEW_RATE_71_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_71_SLEW_RATE_71_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_71_SLEW_RATE_71_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_71_SLEW_RATE_71_MASK, .index = PINMUX_DIO_PAD_ATTR_71_SLEW_RATE_71_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_71_DRIVE_STRENGTH_71_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_71_DRIVE_STRENGTH_71_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_71_DRIVE_STRENGTH_71_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_71_DRIVE_STRENGTH_71_MASK, .index = PINMUX_DIO_PAD_ATTR_71_DRIVE_STRENGTH_71_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_72_REG_OFFSET 0x328

#define	PINMUX_DIO_PAD_ATTR_72_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_ATTR_72_INVERT_72_BIT 0

#define	PINMUX_DIO_PAD_ATTR_72_VIRTUAL_OD_EN_72_BIT 1

#define	PINMUX_DIO_PAD_ATTR_72_PULL_EN_72_BIT 2

#define	PINMUX_DIO_PAD_ATTR_72_PULL_SELECT_72_BIT 3

#define	PINMUX_DIO_PAD_ATTR_72_KEEPER_EN_72_BIT 4

#define	PINMUX_DIO_PAD_ATTR_72_SCHMITT_EN_72_BIT 5

#define	PINMUX_DIO_PAD_ATTR_72_OD_EN_72_BIT 6

#define	PINMUX_DIO_PAD_ATTR_72_INPUT_DISABLE_72_BIT 7

#define	PINMUX_DIO_PAD_ATTR_72_SLEW_RATE_72_MASK 0x3u

#define	PINMUX_DIO_PAD_ATTR_72_SLEW_RATE_72_OFFSET 16

#define	PINMUX_DIO_PAD_ATTR_72_SLEW_RATE_72_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_72_SLEW_RATE_72_MASK, .index = PINMUX_DIO_PAD_ATTR_72_SLEW_RATE_72_OFFSET })

#define	PINMUX_DIO_PAD_ATTR_72_DRIVE_STRENGTH_72_MASK 0xfu

#define	PINMUX_DIO_PAD_ATTR_72_DRIVE_STRENGTH_72_OFFSET 20

#define	PINMUX_DIO_PAD_ATTR_72_DRIVE_STRENGTH_72_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_72_DRIVE_STRENGTH_72_MASK, .index = PINMUX_DIO_PAD_ATTR_72_DRIVE_STRENGTH_72_OFFSET })

#define	PINMUX_MIO_PAD_SLEEP_STATUS_EN_FIELD_WIDTH 1

#define	PINMUX_MIO_PAD_SLEEP_STATUS_MULTIREG_COUNT 1

#define	PINMUX_MIO_PAD_SLEEP_STATUS_REG_OFFSET 0x32c

#define	PINMUX_MIO_PAD_SLEEP_STATUS_REG_RESVAL 0x0u

#define	PINMUX_MIO_PAD_SLEEP_STATUS_EN_0_BIT 0

#define	PINMUX_MIO_PAD_SLEEP_STATUS_EN_1_BIT 1

#define	PINMUX_MIO_PAD_SLEEP_STATUS_EN_2_BIT 2

#define	PINMUX_MIO_PAD_SLEEP_STATUS_EN_3_BIT 3

#define	PINMUX_MIO_PAD_SLEEP_STATUS_EN_4_BIT 4

#define	PINMUX_MIO_PAD_SLEEP_STATUS_EN_5_BIT 5

#define	PINMUX_MIO_PAD_SLEEP_STATUS_EN_6_BIT 6

#define	PINMUX_MIO_PAD_SLEEP_STATUS_EN_7_BIT 7

#define	PINMUX_MIO_PAD_SLEEP_STATUS_EN_8_BIT 8

#define	PINMUX_MIO_PAD_SLEEP_STATUS_EN_9_BIT 9

#define	PINMUX_MIO_PAD_SLEEP_STATUS_EN_10_BIT 10

#define	PINMUX_MIO_PAD_SLEEP_STATUS_EN_11_BIT 11

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_EN_FIELD_WIDTH 1

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_MULTIREG_COUNT 12

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_0_REG_OFFSET 0x330

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_0_REG_RESVAL 0x1u

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_0_EN_0_BIT 0

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_1_REG_OFFSET 0x334

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_1_REG_RESVAL 0x1u

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_1_EN_1_BIT 0

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_2_REG_OFFSET 0x338

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_2_REG_RESVAL 0x1u

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_2_EN_2_BIT 0

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_3_REG_OFFSET 0x33c

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_3_REG_RESVAL 0x1u

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_3_EN_3_BIT 0

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_4_REG_OFFSET 0x340

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_4_REG_RESVAL 0x1u

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_4_EN_4_BIT 0

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_5_REG_OFFSET 0x344

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_5_REG_RESVAL 0x1u

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_5_EN_5_BIT 0

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_6_REG_OFFSET 0x348

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_6_REG_RESVAL 0x1u

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_6_EN_6_BIT 0

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_7_REG_OFFSET 0x34c

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_7_REG_RESVAL 0x1u

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_7_EN_7_BIT 0

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_8_REG_OFFSET 0x350

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_8_REG_RESVAL 0x1u

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_8_EN_8_BIT 0

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_9_REG_OFFSET 0x354

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_9_REG_RESVAL 0x1u

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_9_EN_9_BIT 0

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_10_REG_OFFSET 0x358

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_10_REG_RESVAL 0x1u

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_10_EN_10_BIT 0

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_11_REG_OFFSET 0x35c

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_11_REG_RESVAL 0x1u

#define	PINMUX_MIO_PAD_SLEEP_REGWEN_11_EN_11_BIT 0

#define	PINMUX_MIO_PAD_SLEEP_EN_EN_FIELD_WIDTH 1

#define	PINMUX_MIO_PAD_SLEEP_EN_MULTIREG_COUNT 12

#define	PINMUX_MIO_PAD_SLEEP_EN_0_REG_OFFSET 0x360

#define	PINMUX_MIO_PAD_SLEEP_EN_0_REG_RESVAL 0x0u

#define	PINMUX_MIO_PAD_SLEEP_EN_0_EN_0_BIT 0

#define	PINMUX_MIO_PAD_SLEEP_EN_1_REG_OFFSET 0x364

#define	PINMUX_MIO_PAD_SLEEP_EN_1_REG_RESVAL 0x0u

#define	PINMUX_MIO_PAD_SLEEP_EN_1_EN_1_BIT 0

#define	PINMUX_MIO_PAD_SLEEP_EN_2_REG_OFFSET 0x368

#define	PINMUX_MIO_PAD_SLEEP_EN_2_REG_RESVAL 0x0u

#define	PINMUX_MIO_PAD_SLEEP_EN_2_EN_2_BIT 0

#define	PINMUX_MIO_PAD_SLEEP_EN_3_REG_OFFSET 0x36c

#define	PINMUX_MIO_PAD_SLEEP_EN_3_REG_RESVAL 0x0u

#define	PINMUX_MIO_PAD_SLEEP_EN_3_EN_3_BIT 0

#define	PINMUX_MIO_PAD_SLEEP_EN_4_REG_OFFSET 0x370

#define	PINMUX_MIO_PAD_SLEEP_EN_4_REG_RESVAL 0x0u

#define	PINMUX_MIO_PAD_SLEEP_EN_4_EN_4_BIT 0

#define	PINMUX_MIO_PAD_SLEEP_EN_5_REG_OFFSET 0x374

#define	PINMUX_MIO_PAD_SLEEP_EN_5_REG_RESVAL 0x0u

#define	PINMUX_MIO_PAD_SLEEP_EN_5_EN_5_BIT 0

#define	PINMUX_MIO_PAD_SLEEP_EN_6_REG_OFFSET 0x378

#define	PINMUX_MIO_PAD_SLEEP_EN_6_REG_RESVAL 0x0u

#define	PINMUX_MIO_PAD_SLEEP_EN_6_EN_6_BIT 0

#define	PINMUX_MIO_PAD_SLEEP_EN_7_REG_OFFSET 0x37c

#define	PINMUX_MIO_PAD_SLEEP_EN_7_REG_RESVAL 0x0u

#define	PINMUX_MIO_PAD_SLEEP_EN_7_EN_7_BIT 0

#define	PINMUX_MIO_PAD_SLEEP_EN_8_REG_OFFSET 0x380

#define	PINMUX_MIO_PAD_SLEEP_EN_8_REG_RESVAL 0x0u

#define	PINMUX_MIO_PAD_SLEEP_EN_8_EN_8_BIT 0

#define	PINMUX_MIO_PAD_SLEEP_EN_9_REG_OFFSET 0x384

#define	PINMUX_MIO_PAD_SLEEP_EN_9_REG_RESVAL 0x0u

#define	PINMUX_MIO_PAD_SLEEP_EN_9_EN_9_BIT 0

#define	PINMUX_MIO_PAD_SLEEP_EN_10_REG_OFFSET 0x388

#define	PINMUX_MIO_PAD_SLEEP_EN_10_REG_RESVAL 0x0u

#define	PINMUX_MIO_PAD_SLEEP_EN_10_EN_10_BIT 0

#define	PINMUX_MIO_PAD_SLEEP_EN_11_REG_OFFSET 0x38c

#define	PINMUX_MIO_PAD_SLEEP_EN_11_REG_RESVAL 0x0u

#define	PINMUX_MIO_PAD_SLEEP_EN_11_EN_11_BIT 0

#define	PINMUX_MIO_PAD_SLEEP_MODE_OUT_FIELD_WIDTH 2

#define	PINMUX_MIO_PAD_SLEEP_MODE_MULTIREG_COUNT 12

#define	PINMUX_MIO_PAD_SLEEP_MODE_0_REG_OFFSET 0x390

#define	PINMUX_MIO_PAD_SLEEP_MODE_0_REG_RESVAL 0x2u

#define	PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_MASK 0x3u

#define	PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_OFFSET 0

#define	PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_OFFSET })

#define	PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_TIE_LOW 0x0

#define	PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_TIE_HIGH 0x1

#define	PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_HIGH_Z 0x2

#define	PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_KEEP 0x3

#define	PINMUX_MIO_PAD_SLEEP_MODE_1_REG_OFFSET 0x394

#define	PINMUX_MIO_PAD_SLEEP_MODE_1_REG_RESVAL 0x2u

#define	PINMUX_MIO_PAD_SLEEP_MODE_1_OUT_1_MASK 0x3u

#define	PINMUX_MIO_PAD_SLEEP_MODE_1_OUT_1_OFFSET 0

#define	PINMUX_MIO_PAD_SLEEP_MODE_1_OUT_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_1_OUT_1_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_1_OUT_1_OFFSET })

#define	PINMUX_MIO_PAD_SLEEP_MODE_2_REG_OFFSET 0x398

#define	PINMUX_MIO_PAD_SLEEP_MODE_2_REG_RESVAL 0x2u

#define	PINMUX_MIO_PAD_SLEEP_MODE_2_OUT_2_MASK 0x3u

#define	PINMUX_MIO_PAD_SLEEP_MODE_2_OUT_2_OFFSET 0

#define	PINMUX_MIO_PAD_SLEEP_MODE_2_OUT_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_2_OUT_2_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_2_OUT_2_OFFSET })

#define	PINMUX_MIO_PAD_SLEEP_MODE_3_REG_OFFSET 0x39c

#define	PINMUX_MIO_PAD_SLEEP_MODE_3_REG_RESVAL 0x2u

#define	PINMUX_MIO_PAD_SLEEP_MODE_3_OUT_3_MASK 0x3u

#define	PINMUX_MIO_PAD_SLEEP_MODE_3_OUT_3_OFFSET 0

#define	PINMUX_MIO_PAD_SLEEP_MODE_3_OUT_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_3_OUT_3_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_3_OUT_3_OFFSET })

#define	PINMUX_MIO_PAD_SLEEP_MODE_4_REG_OFFSET 0x3a0

#define	PINMUX_MIO_PAD_SLEEP_MODE_4_REG_RESVAL 0x2u

#define	PINMUX_MIO_PAD_SLEEP_MODE_4_OUT_4_MASK 0x3u

#define	PINMUX_MIO_PAD_SLEEP_MODE_4_OUT_4_OFFSET 0

#define	PINMUX_MIO_PAD_SLEEP_MODE_4_OUT_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_4_OUT_4_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_4_OUT_4_OFFSET })

#define	PINMUX_MIO_PAD_SLEEP_MODE_5_REG_OFFSET 0x3a4

#define	PINMUX_MIO_PAD_SLEEP_MODE_5_REG_RESVAL 0x2u

#define	PINMUX_MIO_PAD_SLEEP_MODE_5_OUT_5_MASK 0x3u

#define	PINMUX_MIO_PAD_SLEEP_MODE_5_OUT_5_OFFSET 0

#define	PINMUX_MIO_PAD_SLEEP_MODE_5_OUT_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_5_OUT_5_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_5_OUT_5_OFFSET })

#define	PINMUX_MIO_PAD_SLEEP_MODE_6_REG_OFFSET 0x3a8

#define	PINMUX_MIO_PAD_SLEEP_MODE_6_REG_RESVAL 0x2u

#define	PINMUX_MIO_PAD_SLEEP_MODE_6_OUT_6_MASK 0x3u

#define	PINMUX_MIO_PAD_SLEEP_MODE_6_OUT_6_OFFSET 0

#define	PINMUX_MIO_PAD_SLEEP_MODE_6_OUT_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_6_OUT_6_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_6_OUT_6_OFFSET })

#define	PINMUX_MIO_PAD_SLEEP_MODE_7_REG_OFFSET 0x3ac

#define	PINMUX_MIO_PAD_SLEEP_MODE_7_REG_RESVAL 0x2u

#define	PINMUX_MIO_PAD_SLEEP_MODE_7_OUT_7_MASK 0x3u

#define	PINMUX_MIO_PAD_SLEEP_MODE_7_OUT_7_OFFSET 0

#define	PINMUX_MIO_PAD_SLEEP_MODE_7_OUT_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_7_OUT_7_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_7_OUT_7_OFFSET })

#define	PINMUX_MIO_PAD_SLEEP_MODE_8_REG_OFFSET 0x3b0

#define	PINMUX_MIO_PAD_SLEEP_MODE_8_REG_RESVAL 0x2u

#define	PINMUX_MIO_PAD_SLEEP_MODE_8_OUT_8_MASK 0x3u

#define	PINMUX_MIO_PAD_SLEEP_MODE_8_OUT_8_OFFSET 0

#define	PINMUX_MIO_PAD_SLEEP_MODE_8_OUT_8_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_8_OUT_8_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_8_OUT_8_OFFSET })

#define	PINMUX_MIO_PAD_SLEEP_MODE_9_REG_OFFSET 0x3b4

#define	PINMUX_MIO_PAD_SLEEP_MODE_9_REG_RESVAL 0x2u

#define	PINMUX_MIO_PAD_SLEEP_MODE_9_OUT_9_MASK 0x3u

#define	PINMUX_MIO_PAD_SLEEP_MODE_9_OUT_9_OFFSET 0

#define	PINMUX_MIO_PAD_SLEEP_MODE_9_OUT_9_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_9_OUT_9_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_9_OUT_9_OFFSET })

#define	PINMUX_MIO_PAD_SLEEP_MODE_10_REG_OFFSET 0x3b8

#define	PINMUX_MIO_PAD_SLEEP_MODE_10_REG_RESVAL 0x2u

#define	PINMUX_MIO_PAD_SLEEP_MODE_10_OUT_10_MASK 0x3u

#define	PINMUX_MIO_PAD_SLEEP_MODE_10_OUT_10_OFFSET 0

#define	PINMUX_MIO_PAD_SLEEP_MODE_10_OUT_10_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_10_OUT_10_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_10_OUT_10_OFFSET })

#define	PINMUX_MIO_PAD_SLEEP_MODE_11_REG_OFFSET 0x3bc

#define	PINMUX_MIO_PAD_SLEEP_MODE_11_REG_RESVAL 0x2u

#define	PINMUX_MIO_PAD_SLEEP_MODE_11_OUT_11_MASK 0x3u

#define	PINMUX_MIO_PAD_SLEEP_MODE_11_OUT_11_OFFSET 0

#define	PINMUX_MIO_PAD_SLEEP_MODE_11_OUT_11_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_11_OUT_11_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_11_OUT_11_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_STATUS_EN_FIELD_WIDTH 1

#define	PINMUX_DIO_PAD_SLEEP_STATUS_MULTIREG_COUNT 3

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_REG_OFFSET 0x3c0

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_0_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_1_BIT 1

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_2_BIT 2

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_3_BIT 3

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_4_BIT 4

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_5_BIT 5

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_6_BIT 6

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_7_BIT 7

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_8_BIT 8

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_9_BIT 9

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_10_BIT 10

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_11_BIT 11

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_12_BIT 12

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_13_BIT 13

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_14_BIT 14

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_15_BIT 15

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_16_BIT 16

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_17_BIT 17

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_18_BIT 18

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_19_BIT 19

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_20_BIT 20

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_21_BIT 21

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_22_BIT 22

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_23_BIT 23

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_24_BIT 24

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_25_BIT 25

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_26_BIT 26

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_27_BIT 27

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_28_BIT 28

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_29_BIT 29

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_30_BIT 30

#define	PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_31_BIT 31

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_REG_OFFSET 0x3c4

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_32_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_33_BIT 1

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_34_BIT 2

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_35_BIT 3

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_36_BIT 4

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_37_BIT 5

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_38_BIT 6

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_39_BIT 7

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_40_BIT 8

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_41_BIT 9

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_42_BIT 10

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_43_BIT 11

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_44_BIT 12

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_45_BIT 13

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_46_BIT 14

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_47_BIT 15

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_48_BIT 16

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_49_BIT 17

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_50_BIT 18

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_51_BIT 19

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_52_BIT 20

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_53_BIT 21

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_54_BIT 22

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_55_BIT 23

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_56_BIT 24

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_57_BIT 25

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_58_BIT 26

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_59_BIT 27

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_60_BIT 28

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_61_BIT 29

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_62_BIT 30

#define	PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_63_BIT 31

#define	PINMUX_DIO_PAD_SLEEP_STATUS_2_REG_OFFSET 0x3c8

#define	PINMUX_DIO_PAD_SLEEP_STATUS_2_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_STATUS_2_EN_64_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_STATUS_2_EN_65_BIT 1

#define	PINMUX_DIO_PAD_SLEEP_STATUS_2_EN_66_BIT 2

#define	PINMUX_DIO_PAD_SLEEP_STATUS_2_EN_67_BIT 3

#define	PINMUX_DIO_PAD_SLEEP_STATUS_2_EN_68_BIT 4

#define	PINMUX_DIO_PAD_SLEEP_STATUS_2_EN_69_BIT 5

#define	PINMUX_DIO_PAD_SLEEP_STATUS_2_EN_70_BIT 6

#define	PINMUX_DIO_PAD_SLEEP_STATUS_2_EN_71_BIT 7

#define	PINMUX_DIO_PAD_SLEEP_STATUS_2_EN_72_BIT 8

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_EN_FIELD_WIDTH 1

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_MULTIREG_COUNT 73

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_0_REG_OFFSET 0x3cc

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_0_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_0_EN_0_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_1_REG_OFFSET 0x3d0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_1_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_1_EN_1_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_2_REG_OFFSET 0x3d4

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_2_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_2_EN_2_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_3_REG_OFFSET 0x3d8

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_3_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_3_EN_3_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_4_REG_OFFSET 0x3dc

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_4_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_4_EN_4_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_5_REG_OFFSET 0x3e0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_5_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_5_EN_5_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_6_REG_OFFSET 0x3e4

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_6_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_6_EN_6_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_7_REG_OFFSET 0x3e8

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_7_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_7_EN_7_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_8_REG_OFFSET 0x3ec

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_8_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_8_EN_8_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_9_REG_OFFSET 0x3f0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_9_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_9_EN_9_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_10_REG_OFFSET 0x3f4

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_10_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_10_EN_10_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_11_REG_OFFSET 0x3f8

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_11_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_11_EN_11_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_12_REG_OFFSET 0x3fc

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_12_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_12_EN_12_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_13_REG_OFFSET 0x400

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_13_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_13_EN_13_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_14_REG_OFFSET 0x404

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_14_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_14_EN_14_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_15_REG_OFFSET 0x408

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_15_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_15_EN_15_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_16_REG_OFFSET 0x40c

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_16_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_16_EN_16_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_17_REG_OFFSET 0x410

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_17_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_17_EN_17_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_18_REG_OFFSET 0x414

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_18_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_18_EN_18_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_19_REG_OFFSET 0x418

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_19_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_19_EN_19_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_20_REG_OFFSET 0x41c

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_20_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_20_EN_20_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_21_REG_OFFSET 0x420

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_21_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_21_EN_21_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_22_REG_OFFSET 0x424

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_22_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_22_EN_22_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_23_REG_OFFSET 0x428

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_23_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_23_EN_23_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_24_REG_OFFSET 0x42c

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_24_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_24_EN_24_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_25_REG_OFFSET 0x430

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_25_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_25_EN_25_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_26_REG_OFFSET 0x434

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_26_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_26_EN_26_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_27_REG_OFFSET 0x438

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_27_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_27_EN_27_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_28_REG_OFFSET 0x43c

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_28_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_28_EN_28_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_29_REG_OFFSET 0x440

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_29_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_29_EN_29_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_30_REG_OFFSET 0x444

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_30_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_30_EN_30_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_31_REG_OFFSET 0x448

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_31_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_31_EN_31_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_32_REG_OFFSET 0x44c

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_32_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_32_EN_32_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_33_REG_OFFSET 0x450

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_33_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_33_EN_33_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_34_REG_OFFSET 0x454

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_34_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_34_EN_34_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_35_REG_OFFSET 0x458

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_35_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_35_EN_35_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_36_REG_OFFSET 0x45c

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_36_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_36_EN_36_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_37_REG_OFFSET 0x460

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_37_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_37_EN_37_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_38_REG_OFFSET 0x464

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_38_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_38_EN_38_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_39_REG_OFFSET 0x468

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_39_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_39_EN_39_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_40_REG_OFFSET 0x46c

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_40_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_40_EN_40_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_41_REG_OFFSET 0x470

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_41_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_41_EN_41_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_42_REG_OFFSET 0x474

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_42_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_42_EN_42_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_43_REG_OFFSET 0x478

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_43_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_43_EN_43_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_44_REG_OFFSET 0x47c

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_44_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_44_EN_44_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_45_REG_OFFSET 0x480

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_45_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_45_EN_45_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_46_REG_OFFSET 0x484

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_46_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_46_EN_46_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_47_REG_OFFSET 0x488

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_47_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_47_EN_47_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_48_REG_OFFSET 0x48c

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_48_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_48_EN_48_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_49_REG_OFFSET 0x490

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_49_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_49_EN_49_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_50_REG_OFFSET 0x494

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_50_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_50_EN_50_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_51_REG_OFFSET 0x498

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_51_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_51_EN_51_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_52_REG_OFFSET 0x49c

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_52_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_52_EN_52_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_53_REG_OFFSET 0x4a0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_53_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_53_EN_53_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_54_REG_OFFSET 0x4a4

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_54_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_54_EN_54_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_55_REG_OFFSET 0x4a8

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_55_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_55_EN_55_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_56_REG_OFFSET 0x4ac

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_56_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_56_EN_56_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_57_REG_OFFSET 0x4b0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_57_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_57_EN_57_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_58_REG_OFFSET 0x4b4

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_58_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_58_EN_58_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_59_REG_OFFSET 0x4b8

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_59_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_59_EN_59_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_60_REG_OFFSET 0x4bc

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_60_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_60_EN_60_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_61_REG_OFFSET 0x4c0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_61_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_61_EN_61_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_62_REG_OFFSET 0x4c4

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_62_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_62_EN_62_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_63_REG_OFFSET 0x4c8

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_63_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_63_EN_63_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_64_REG_OFFSET 0x4cc

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_64_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_64_EN_64_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_65_REG_OFFSET 0x4d0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_65_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_65_EN_65_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_66_REG_OFFSET 0x4d4

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_66_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_66_EN_66_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_67_REG_OFFSET 0x4d8

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_67_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_67_EN_67_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_68_REG_OFFSET 0x4dc

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_68_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_68_EN_68_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_69_REG_OFFSET 0x4e0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_69_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_69_EN_69_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_70_REG_OFFSET 0x4e4

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_70_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_70_EN_70_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_71_REG_OFFSET 0x4e8

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_71_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_71_EN_71_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_72_REG_OFFSET 0x4ec

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_72_REG_RESVAL 0x1u

#define	PINMUX_DIO_PAD_SLEEP_REGWEN_72_EN_72_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_EN_FIELD_WIDTH 1

#define	PINMUX_DIO_PAD_SLEEP_EN_MULTIREG_COUNT 73

#define	PINMUX_DIO_PAD_SLEEP_EN_0_REG_OFFSET 0x4f0

#define	PINMUX_DIO_PAD_SLEEP_EN_0_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_0_EN_0_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_1_REG_OFFSET 0x4f4

#define	PINMUX_DIO_PAD_SLEEP_EN_1_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_1_EN_1_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_2_REG_OFFSET 0x4f8

#define	PINMUX_DIO_PAD_SLEEP_EN_2_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_2_EN_2_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_3_REG_OFFSET 0x4fc

#define	PINMUX_DIO_PAD_SLEEP_EN_3_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_3_EN_3_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_4_REG_OFFSET 0x500

#define	PINMUX_DIO_PAD_SLEEP_EN_4_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_4_EN_4_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_5_REG_OFFSET 0x504

#define	PINMUX_DIO_PAD_SLEEP_EN_5_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_5_EN_5_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_6_REG_OFFSET 0x508

#define	PINMUX_DIO_PAD_SLEEP_EN_6_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_6_EN_6_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_7_REG_OFFSET 0x50c

#define	PINMUX_DIO_PAD_SLEEP_EN_7_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_7_EN_7_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_8_REG_OFFSET 0x510

#define	PINMUX_DIO_PAD_SLEEP_EN_8_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_8_EN_8_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_9_REG_OFFSET 0x514

#define	PINMUX_DIO_PAD_SLEEP_EN_9_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_9_EN_9_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_10_REG_OFFSET 0x518

#define	PINMUX_DIO_PAD_SLEEP_EN_10_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_10_EN_10_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_11_REG_OFFSET 0x51c

#define	PINMUX_DIO_PAD_SLEEP_EN_11_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_11_EN_11_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_12_REG_OFFSET 0x520

#define	PINMUX_DIO_PAD_SLEEP_EN_12_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_12_EN_12_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_13_REG_OFFSET 0x524

#define	PINMUX_DIO_PAD_SLEEP_EN_13_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_13_EN_13_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_14_REG_OFFSET 0x528

#define	PINMUX_DIO_PAD_SLEEP_EN_14_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_14_EN_14_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_15_REG_OFFSET 0x52c

#define	PINMUX_DIO_PAD_SLEEP_EN_15_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_15_EN_15_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_16_REG_OFFSET 0x530

#define	PINMUX_DIO_PAD_SLEEP_EN_16_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_16_EN_16_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_17_REG_OFFSET 0x534

#define	PINMUX_DIO_PAD_SLEEP_EN_17_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_17_EN_17_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_18_REG_OFFSET 0x538

#define	PINMUX_DIO_PAD_SLEEP_EN_18_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_18_EN_18_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_19_REG_OFFSET 0x53c

#define	PINMUX_DIO_PAD_SLEEP_EN_19_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_19_EN_19_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_20_REG_OFFSET 0x540

#define	PINMUX_DIO_PAD_SLEEP_EN_20_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_20_EN_20_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_21_REG_OFFSET 0x544

#define	PINMUX_DIO_PAD_SLEEP_EN_21_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_21_EN_21_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_22_REG_OFFSET 0x548

#define	PINMUX_DIO_PAD_SLEEP_EN_22_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_22_EN_22_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_23_REG_OFFSET 0x54c

#define	PINMUX_DIO_PAD_SLEEP_EN_23_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_23_EN_23_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_24_REG_OFFSET 0x550

#define	PINMUX_DIO_PAD_SLEEP_EN_24_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_24_EN_24_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_25_REG_OFFSET 0x554

#define	PINMUX_DIO_PAD_SLEEP_EN_25_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_25_EN_25_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_26_REG_OFFSET 0x558

#define	PINMUX_DIO_PAD_SLEEP_EN_26_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_26_EN_26_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_27_REG_OFFSET 0x55c

#define	PINMUX_DIO_PAD_SLEEP_EN_27_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_27_EN_27_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_28_REG_OFFSET 0x560

#define	PINMUX_DIO_PAD_SLEEP_EN_28_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_28_EN_28_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_29_REG_OFFSET 0x564

#define	PINMUX_DIO_PAD_SLEEP_EN_29_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_29_EN_29_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_30_REG_OFFSET 0x568

#define	PINMUX_DIO_PAD_SLEEP_EN_30_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_30_EN_30_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_31_REG_OFFSET 0x56c

#define	PINMUX_DIO_PAD_SLEEP_EN_31_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_31_EN_31_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_32_REG_OFFSET 0x570

#define	PINMUX_DIO_PAD_SLEEP_EN_32_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_32_EN_32_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_33_REG_OFFSET 0x574

#define	PINMUX_DIO_PAD_SLEEP_EN_33_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_33_EN_33_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_34_REG_OFFSET 0x578

#define	PINMUX_DIO_PAD_SLEEP_EN_34_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_34_EN_34_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_35_REG_OFFSET 0x57c

#define	PINMUX_DIO_PAD_SLEEP_EN_35_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_35_EN_35_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_36_REG_OFFSET 0x580

#define	PINMUX_DIO_PAD_SLEEP_EN_36_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_36_EN_36_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_37_REG_OFFSET 0x584

#define	PINMUX_DIO_PAD_SLEEP_EN_37_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_37_EN_37_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_38_REG_OFFSET 0x588

#define	PINMUX_DIO_PAD_SLEEP_EN_38_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_38_EN_38_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_39_REG_OFFSET 0x58c

#define	PINMUX_DIO_PAD_SLEEP_EN_39_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_39_EN_39_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_40_REG_OFFSET 0x590

#define	PINMUX_DIO_PAD_SLEEP_EN_40_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_40_EN_40_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_41_REG_OFFSET 0x594

#define	PINMUX_DIO_PAD_SLEEP_EN_41_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_41_EN_41_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_42_REG_OFFSET 0x598

#define	PINMUX_DIO_PAD_SLEEP_EN_42_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_42_EN_42_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_43_REG_OFFSET 0x59c

#define	PINMUX_DIO_PAD_SLEEP_EN_43_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_43_EN_43_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_44_REG_OFFSET 0x5a0

#define	PINMUX_DIO_PAD_SLEEP_EN_44_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_44_EN_44_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_45_REG_OFFSET 0x5a4

#define	PINMUX_DIO_PAD_SLEEP_EN_45_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_45_EN_45_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_46_REG_OFFSET 0x5a8

#define	PINMUX_DIO_PAD_SLEEP_EN_46_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_46_EN_46_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_47_REG_OFFSET 0x5ac

#define	PINMUX_DIO_PAD_SLEEP_EN_47_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_47_EN_47_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_48_REG_OFFSET 0x5b0

#define	PINMUX_DIO_PAD_SLEEP_EN_48_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_48_EN_48_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_49_REG_OFFSET 0x5b4

#define	PINMUX_DIO_PAD_SLEEP_EN_49_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_49_EN_49_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_50_REG_OFFSET 0x5b8

#define	PINMUX_DIO_PAD_SLEEP_EN_50_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_50_EN_50_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_51_REG_OFFSET 0x5bc

#define	PINMUX_DIO_PAD_SLEEP_EN_51_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_51_EN_51_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_52_REG_OFFSET 0x5c0

#define	PINMUX_DIO_PAD_SLEEP_EN_52_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_52_EN_52_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_53_REG_OFFSET 0x5c4

#define	PINMUX_DIO_PAD_SLEEP_EN_53_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_53_EN_53_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_54_REG_OFFSET 0x5c8

#define	PINMUX_DIO_PAD_SLEEP_EN_54_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_54_EN_54_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_55_REG_OFFSET 0x5cc

#define	PINMUX_DIO_PAD_SLEEP_EN_55_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_55_EN_55_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_56_REG_OFFSET 0x5d0

#define	PINMUX_DIO_PAD_SLEEP_EN_56_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_56_EN_56_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_57_REG_OFFSET 0x5d4

#define	PINMUX_DIO_PAD_SLEEP_EN_57_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_57_EN_57_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_58_REG_OFFSET 0x5d8

#define	PINMUX_DIO_PAD_SLEEP_EN_58_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_58_EN_58_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_59_REG_OFFSET 0x5dc

#define	PINMUX_DIO_PAD_SLEEP_EN_59_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_59_EN_59_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_60_REG_OFFSET 0x5e0

#define	PINMUX_DIO_PAD_SLEEP_EN_60_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_60_EN_60_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_61_REG_OFFSET 0x5e4

#define	PINMUX_DIO_PAD_SLEEP_EN_61_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_61_EN_61_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_62_REG_OFFSET 0x5e8

#define	PINMUX_DIO_PAD_SLEEP_EN_62_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_62_EN_62_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_63_REG_OFFSET 0x5ec

#define	PINMUX_DIO_PAD_SLEEP_EN_63_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_63_EN_63_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_64_REG_OFFSET 0x5f0

#define	PINMUX_DIO_PAD_SLEEP_EN_64_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_64_EN_64_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_65_REG_OFFSET 0x5f4

#define	PINMUX_DIO_PAD_SLEEP_EN_65_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_65_EN_65_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_66_REG_OFFSET 0x5f8

#define	PINMUX_DIO_PAD_SLEEP_EN_66_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_66_EN_66_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_67_REG_OFFSET 0x5fc

#define	PINMUX_DIO_PAD_SLEEP_EN_67_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_67_EN_67_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_68_REG_OFFSET 0x600

#define	PINMUX_DIO_PAD_SLEEP_EN_68_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_68_EN_68_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_69_REG_OFFSET 0x604

#define	PINMUX_DIO_PAD_SLEEP_EN_69_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_69_EN_69_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_70_REG_OFFSET 0x608

#define	PINMUX_DIO_PAD_SLEEP_EN_70_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_70_EN_70_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_71_REG_OFFSET 0x60c

#define	PINMUX_DIO_PAD_SLEEP_EN_71_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_71_EN_71_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_EN_72_REG_OFFSET 0x610

#define	PINMUX_DIO_PAD_SLEEP_EN_72_REG_RESVAL 0x0u

#define	PINMUX_DIO_PAD_SLEEP_EN_72_EN_72_BIT 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_OUT_FIELD_WIDTH 2

#define	PINMUX_DIO_PAD_SLEEP_MODE_MULTIREG_COUNT 73

#define	PINMUX_DIO_PAD_SLEEP_MODE_0_REG_OFFSET 0x614

#define	PINMUX_DIO_PAD_SLEEP_MODE_0_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_TIE_LOW 0x0

#define	PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_TIE_HIGH 0x1

#define	PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_HIGH_Z 0x2

#define	PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_KEEP 0x3

#define	PINMUX_DIO_PAD_SLEEP_MODE_1_REG_OFFSET 0x618

#define	PINMUX_DIO_PAD_SLEEP_MODE_1_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_1_OUT_1_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_1_OUT_1_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_1_OUT_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_1_OUT_1_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_1_OUT_1_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_2_REG_OFFSET 0x61c

#define	PINMUX_DIO_PAD_SLEEP_MODE_2_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_2_OUT_2_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_2_OUT_2_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_2_OUT_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_2_OUT_2_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_2_OUT_2_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_3_REG_OFFSET 0x620

#define	PINMUX_DIO_PAD_SLEEP_MODE_3_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_3_OUT_3_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_3_OUT_3_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_3_OUT_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_3_OUT_3_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_3_OUT_3_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_4_REG_OFFSET 0x624

#define	PINMUX_DIO_PAD_SLEEP_MODE_4_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_4_OUT_4_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_4_OUT_4_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_4_OUT_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_4_OUT_4_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_4_OUT_4_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_5_REG_OFFSET 0x628

#define	PINMUX_DIO_PAD_SLEEP_MODE_5_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_5_OUT_5_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_5_OUT_5_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_5_OUT_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_5_OUT_5_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_5_OUT_5_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_6_REG_OFFSET 0x62c

#define	PINMUX_DIO_PAD_SLEEP_MODE_6_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_6_OUT_6_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_6_OUT_6_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_6_OUT_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_6_OUT_6_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_6_OUT_6_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_7_REG_OFFSET 0x630

#define	PINMUX_DIO_PAD_SLEEP_MODE_7_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_7_OUT_7_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_7_OUT_7_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_7_OUT_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_7_OUT_7_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_7_OUT_7_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_8_REG_OFFSET 0x634

#define	PINMUX_DIO_PAD_SLEEP_MODE_8_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_8_OUT_8_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_8_OUT_8_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_8_OUT_8_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_8_OUT_8_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_8_OUT_8_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_9_REG_OFFSET 0x638

#define	PINMUX_DIO_PAD_SLEEP_MODE_9_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_9_OUT_9_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_9_OUT_9_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_9_OUT_9_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_9_OUT_9_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_9_OUT_9_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_10_REG_OFFSET 0x63c

#define	PINMUX_DIO_PAD_SLEEP_MODE_10_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_10_OUT_10_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_10_OUT_10_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_10_OUT_10_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_10_OUT_10_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_10_OUT_10_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_11_REG_OFFSET 0x640

#define	PINMUX_DIO_PAD_SLEEP_MODE_11_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_11_OUT_11_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_11_OUT_11_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_11_OUT_11_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_11_OUT_11_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_11_OUT_11_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_12_REG_OFFSET 0x644

#define	PINMUX_DIO_PAD_SLEEP_MODE_12_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_12_OUT_12_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_12_OUT_12_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_12_OUT_12_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_12_OUT_12_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_12_OUT_12_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_13_REG_OFFSET 0x648

#define	PINMUX_DIO_PAD_SLEEP_MODE_13_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_13_OUT_13_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_13_OUT_13_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_13_OUT_13_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_13_OUT_13_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_13_OUT_13_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_14_REG_OFFSET 0x64c

#define	PINMUX_DIO_PAD_SLEEP_MODE_14_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_14_OUT_14_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_14_OUT_14_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_14_OUT_14_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_14_OUT_14_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_14_OUT_14_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_15_REG_OFFSET 0x650

#define	PINMUX_DIO_PAD_SLEEP_MODE_15_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_15_OUT_15_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_15_OUT_15_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_15_OUT_15_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_15_OUT_15_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_15_OUT_15_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_16_REG_OFFSET 0x654

#define	PINMUX_DIO_PAD_SLEEP_MODE_16_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_16_OUT_16_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_16_OUT_16_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_16_OUT_16_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_16_OUT_16_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_16_OUT_16_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_17_REG_OFFSET 0x658

#define	PINMUX_DIO_PAD_SLEEP_MODE_17_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_17_OUT_17_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_17_OUT_17_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_17_OUT_17_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_17_OUT_17_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_17_OUT_17_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_18_REG_OFFSET 0x65c

#define	PINMUX_DIO_PAD_SLEEP_MODE_18_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_18_OUT_18_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_18_OUT_18_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_18_OUT_18_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_18_OUT_18_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_18_OUT_18_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_19_REG_OFFSET 0x660

#define	PINMUX_DIO_PAD_SLEEP_MODE_19_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_19_OUT_19_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_19_OUT_19_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_19_OUT_19_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_19_OUT_19_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_19_OUT_19_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_20_REG_OFFSET 0x664

#define	PINMUX_DIO_PAD_SLEEP_MODE_20_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_20_OUT_20_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_20_OUT_20_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_20_OUT_20_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_20_OUT_20_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_20_OUT_20_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_21_REG_OFFSET 0x668

#define	PINMUX_DIO_PAD_SLEEP_MODE_21_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_21_OUT_21_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_21_OUT_21_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_21_OUT_21_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_21_OUT_21_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_21_OUT_21_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_22_REG_OFFSET 0x66c

#define	PINMUX_DIO_PAD_SLEEP_MODE_22_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_22_OUT_22_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_22_OUT_22_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_22_OUT_22_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_22_OUT_22_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_22_OUT_22_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_23_REG_OFFSET 0x670

#define	PINMUX_DIO_PAD_SLEEP_MODE_23_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_23_OUT_23_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_23_OUT_23_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_23_OUT_23_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_23_OUT_23_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_23_OUT_23_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_24_REG_OFFSET 0x674

#define	PINMUX_DIO_PAD_SLEEP_MODE_24_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_24_OUT_24_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_24_OUT_24_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_24_OUT_24_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_24_OUT_24_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_24_OUT_24_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_25_REG_OFFSET 0x678

#define	PINMUX_DIO_PAD_SLEEP_MODE_25_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_25_OUT_25_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_25_OUT_25_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_25_OUT_25_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_25_OUT_25_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_25_OUT_25_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_26_REG_OFFSET 0x67c

#define	PINMUX_DIO_PAD_SLEEP_MODE_26_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_26_OUT_26_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_26_OUT_26_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_26_OUT_26_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_26_OUT_26_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_26_OUT_26_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_27_REG_OFFSET 0x680

#define	PINMUX_DIO_PAD_SLEEP_MODE_27_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_27_OUT_27_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_27_OUT_27_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_27_OUT_27_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_27_OUT_27_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_27_OUT_27_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_28_REG_OFFSET 0x684

#define	PINMUX_DIO_PAD_SLEEP_MODE_28_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_28_OUT_28_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_28_OUT_28_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_28_OUT_28_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_28_OUT_28_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_28_OUT_28_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_29_REG_OFFSET 0x688

#define	PINMUX_DIO_PAD_SLEEP_MODE_29_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_29_OUT_29_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_29_OUT_29_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_29_OUT_29_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_29_OUT_29_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_29_OUT_29_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_30_REG_OFFSET 0x68c

#define	PINMUX_DIO_PAD_SLEEP_MODE_30_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_30_OUT_30_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_30_OUT_30_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_30_OUT_30_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_30_OUT_30_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_30_OUT_30_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_31_REG_OFFSET 0x690

#define	PINMUX_DIO_PAD_SLEEP_MODE_31_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_31_OUT_31_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_31_OUT_31_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_31_OUT_31_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_31_OUT_31_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_31_OUT_31_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_32_REG_OFFSET 0x694

#define	PINMUX_DIO_PAD_SLEEP_MODE_32_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_32_OUT_32_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_32_OUT_32_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_32_OUT_32_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_32_OUT_32_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_32_OUT_32_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_33_REG_OFFSET 0x698

#define	PINMUX_DIO_PAD_SLEEP_MODE_33_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_33_OUT_33_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_33_OUT_33_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_33_OUT_33_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_33_OUT_33_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_33_OUT_33_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_34_REG_OFFSET 0x69c

#define	PINMUX_DIO_PAD_SLEEP_MODE_34_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_34_OUT_34_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_34_OUT_34_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_34_OUT_34_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_34_OUT_34_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_34_OUT_34_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_35_REG_OFFSET 0x6a0

#define	PINMUX_DIO_PAD_SLEEP_MODE_35_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_35_OUT_35_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_35_OUT_35_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_35_OUT_35_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_35_OUT_35_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_35_OUT_35_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_36_REG_OFFSET 0x6a4

#define	PINMUX_DIO_PAD_SLEEP_MODE_36_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_36_OUT_36_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_36_OUT_36_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_36_OUT_36_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_36_OUT_36_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_36_OUT_36_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_37_REG_OFFSET 0x6a8

#define	PINMUX_DIO_PAD_SLEEP_MODE_37_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_37_OUT_37_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_37_OUT_37_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_37_OUT_37_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_37_OUT_37_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_37_OUT_37_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_38_REG_OFFSET 0x6ac

#define	PINMUX_DIO_PAD_SLEEP_MODE_38_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_38_OUT_38_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_38_OUT_38_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_38_OUT_38_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_38_OUT_38_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_38_OUT_38_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_39_REG_OFFSET 0x6b0

#define	PINMUX_DIO_PAD_SLEEP_MODE_39_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_39_OUT_39_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_39_OUT_39_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_39_OUT_39_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_39_OUT_39_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_39_OUT_39_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_40_REG_OFFSET 0x6b4

#define	PINMUX_DIO_PAD_SLEEP_MODE_40_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_40_OUT_40_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_40_OUT_40_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_40_OUT_40_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_40_OUT_40_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_40_OUT_40_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_41_REG_OFFSET 0x6b8

#define	PINMUX_DIO_PAD_SLEEP_MODE_41_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_41_OUT_41_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_41_OUT_41_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_41_OUT_41_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_41_OUT_41_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_41_OUT_41_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_42_REG_OFFSET 0x6bc

#define	PINMUX_DIO_PAD_SLEEP_MODE_42_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_42_OUT_42_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_42_OUT_42_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_42_OUT_42_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_42_OUT_42_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_42_OUT_42_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_43_REG_OFFSET 0x6c0

#define	PINMUX_DIO_PAD_SLEEP_MODE_43_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_43_OUT_43_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_43_OUT_43_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_43_OUT_43_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_43_OUT_43_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_43_OUT_43_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_44_REG_OFFSET 0x6c4

#define	PINMUX_DIO_PAD_SLEEP_MODE_44_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_44_OUT_44_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_44_OUT_44_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_44_OUT_44_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_44_OUT_44_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_44_OUT_44_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_45_REG_OFFSET 0x6c8

#define	PINMUX_DIO_PAD_SLEEP_MODE_45_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_45_OUT_45_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_45_OUT_45_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_45_OUT_45_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_45_OUT_45_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_45_OUT_45_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_46_REG_OFFSET 0x6cc

#define	PINMUX_DIO_PAD_SLEEP_MODE_46_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_46_OUT_46_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_46_OUT_46_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_46_OUT_46_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_46_OUT_46_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_46_OUT_46_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_47_REG_OFFSET 0x6d0

#define	PINMUX_DIO_PAD_SLEEP_MODE_47_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_47_OUT_47_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_47_OUT_47_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_47_OUT_47_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_47_OUT_47_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_47_OUT_47_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_48_REG_OFFSET 0x6d4

#define	PINMUX_DIO_PAD_SLEEP_MODE_48_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_48_OUT_48_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_48_OUT_48_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_48_OUT_48_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_48_OUT_48_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_48_OUT_48_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_49_REG_OFFSET 0x6d8

#define	PINMUX_DIO_PAD_SLEEP_MODE_49_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_49_OUT_49_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_49_OUT_49_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_49_OUT_49_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_49_OUT_49_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_49_OUT_49_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_50_REG_OFFSET 0x6dc

#define	PINMUX_DIO_PAD_SLEEP_MODE_50_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_50_OUT_50_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_50_OUT_50_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_50_OUT_50_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_50_OUT_50_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_50_OUT_50_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_51_REG_OFFSET 0x6e0

#define	PINMUX_DIO_PAD_SLEEP_MODE_51_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_51_OUT_51_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_51_OUT_51_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_51_OUT_51_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_51_OUT_51_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_51_OUT_51_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_52_REG_OFFSET 0x6e4

#define	PINMUX_DIO_PAD_SLEEP_MODE_52_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_52_OUT_52_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_52_OUT_52_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_52_OUT_52_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_52_OUT_52_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_52_OUT_52_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_53_REG_OFFSET 0x6e8

#define	PINMUX_DIO_PAD_SLEEP_MODE_53_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_53_OUT_53_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_53_OUT_53_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_53_OUT_53_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_53_OUT_53_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_53_OUT_53_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_54_REG_OFFSET 0x6ec

#define	PINMUX_DIO_PAD_SLEEP_MODE_54_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_54_OUT_54_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_54_OUT_54_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_54_OUT_54_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_54_OUT_54_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_54_OUT_54_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_55_REG_OFFSET 0x6f0

#define	PINMUX_DIO_PAD_SLEEP_MODE_55_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_55_OUT_55_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_55_OUT_55_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_55_OUT_55_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_55_OUT_55_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_55_OUT_55_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_56_REG_OFFSET 0x6f4

#define	PINMUX_DIO_PAD_SLEEP_MODE_56_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_56_OUT_56_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_56_OUT_56_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_56_OUT_56_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_56_OUT_56_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_56_OUT_56_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_57_REG_OFFSET 0x6f8

#define	PINMUX_DIO_PAD_SLEEP_MODE_57_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_57_OUT_57_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_57_OUT_57_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_57_OUT_57_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_57_OUT_57_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_57_OUT_57_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_58_REG_OFFSET 0x6fc

#define	PINMUX_DIO_PAD_SLEEP_MODE_58_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_58_OUT_58_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_58_OUT_58_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_58_OUT_58_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_58_OUT_58_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_58_OUT_58_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_59_REG_OFFSET 0x700

#define	PINMUX_DIO_PAD_SLEEP_MODE_59_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_59_OUT_59_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_59_OUT_59_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_59_OUT_59_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_59_OUT_59_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_59_OUT_59_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_60_REG_OFFSET 0x704

#define	PINMUX_DIO_PAD_SLEEP_MODE_60_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_60_OUT_60_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_60_OUT_60_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_60_OUT_60_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_60_OUT_60_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_60_OUT_60_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_61_REG_OFFSET 0x708

#define	PINMUX_DIO_PAD_SLEEP_MODE_61_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_61_OUT_61_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_61_OUT_61_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_61_OUT_61_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_61_OUT_61_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_61_OUT_61_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_62_REG_OFFSET 0x70c

#define	PINMUX_DIO_PAD_SLEEP_MODE_62_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_62_OUT_62_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_62_OUT_62_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_62_OUT_62_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_62_OUT_62_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_62_OUT_62_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_63_REG_OFFSET 0x710

#define	PINMUX_DIO_PAD_SLEEP_MODE_63_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_63_OUT_63_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_63_OUT_63_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_63_OUT_63_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_63_OUT_63_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_63_OUT_63_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_64_REG_OFFSET 0x714

#define	PINMUX_DIO_PAD_SLEEP_MODE_64_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_64_OUT_64_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_64_OUT_64_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_64_OUT_64_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_64_OUT_64_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_64_OUT_64_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_65_REG_OFFSET 0x718

#define	PINMUX_DIO_PAD_SLEEP_MODE_65_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_65_OUT_65_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_65_OUT_65_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_65_OUT_65_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_65_OUT_65_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_65_OUT_65_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_66_REG_OFFSET 0x71c

#define	PINMUX_DIO_PAD_SLEEP_MODE_66_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_66_OUT_66_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_66_OUT_66_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_66_OUT_66_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_66_OUT_66_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_66_OUT_66_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_67_REG_OFFSET 0x720

#define	PINMUX_DIO_PAD_SLEEP_MODE_67_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_67_OUT_67_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_67_OUT_67_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_67_OUT_67_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_67_OUT_67_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_67_OUT_67_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_68_REG_OFFSET 0x724

#define	PINMUX_DIO_PAD_SLEEP_MODE_68_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_68_OUT_68_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_68_OUT_68_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_68_OUT_68_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_68_OUT_68_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_68_OUT_68_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_69_REG_OFFSET 0x728

#define	PINMUX_DIO_PAD_SLEEP_MODE_69_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_69_OUT_69_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_69_OUT_69_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_69_OUT_69_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_69_OUT_69_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_69_OUT_69_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_70_REG_OFFSET 0x72c

#define	PINMUX_DIO_PAD_SLEEP_MODE_70_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_70_OUT_70_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_70_OUT_70_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_70_OUT_70_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_70_OUT_70_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_70_OUT_70_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_71_REG_OFFSET 0x730

#define	PINMUX_DIO_PAD_SLEEP_MODE_71_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_71_OUT_71_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_71_OUT_71_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_71_OUT_71_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_71_OUT_71_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_71_OUT_71_OFFSET })

#define	PINMUX_DIO_PAD_SLEEP_MODE_72_REG_OFFSET 0x734

#define	PINMUX_DIO_PAD_SLEEP_MODE_72_REG_RESVAL 0x2u

#define	PINMUX_DIO_PAD_SLEEP_MODE_72_OUT_72_MASK 0x3u

#define	PINMUX_DIO_PAD_SLEEP_MODE_72_OUT_72_OFFSET 0

#define	PINMUX_DIO_PAD_SLEEP_MODE_72_OUT_72_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_72_OUT_72_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_72_OUT_72_OFFSET })

#define	PINMUX_WKUP_DETECTOR_REGWEN_EN_FIELD_WIDTH 1

#define	PINMUX_WKUP_DETECTOR_REGWEN_MULTIREG_COUNT 8

#define	PINMUX_WKUP_DETECTOR_REGWEN_0_REG_OFFSET 0x738

#define	PINMUX_WKUP_DETECTOR_REGWEN_0_REG_RESVAL 0x1u

#define	PINMUX_WKUP_DETECTOR_REGWEN_0_EN_0_BIT 0

#define	PINMUX_WKUP_DETECTOR_REGWEN_1_REG_OFFSET 0x73c

#define	PINMUX_WKUP_DETECTOR_REGWEN_1_REG_RESVAL 0x1u

#define	PINMUX_WKUP_DETECTOR_REGWEN_1_EN_1_BIT 0

#define	PINMUX_WKUP_DETECTOR_REGWEN_2_REG_OFFSET 0x740

#define	PINMUX_WKUP_DETECTOR_REGWEN_2_REG_RESVAL 0x1u

#define	PINMUX_WKUP_DETECTOR_REGWEN_2_EN_2_BIT 0

#define	PINMUX_WKUP_DETECTOR_REGWEN_3_REG_OFFSET 0x744

#define	PINMUX_WKUP_DETECTOR_REGWEN_3_REG_RESVAL 0x1u

#define	PINMUX_WKUP_DETECTOR_REGWEN_3_EN_3_BIT 0

#define	PINMUX_WKUP_DETECTOR_REGWEN_4_REG_OFFSET 0x748

#define	PINMUX_WKUP_DETECTOR_REGWEN_4_REG_RESVAL 0x1u

#define	PINMUX_WKUP_DETECTOR_REGWEN_4_EN_4_BIT 0

#define	PINMUX_WKUP_DETECTOR_REGWEN_5_REG_OFFSET 0x74c

#define	PINMUX_WKUP_DETECTOR_REGWEN_5_REG_RESVAL 0x1u

#define	PINMUX_WKUP_DETECTOR_REGWEN_5_EN_5_BIT 0

#define	PINMUX_WKUP_DETECTOR_REGWEN_6_REG_OFFSET 0x750

#define	PINMUX_WKUP_DETECTOR_REGWEN_6_REG_RESVAL 0x1u

#define	PINMUX_WKUP_DETECTOR_REGWEN_6_EN_6_BIT 0

#define	PINMUX_WKUP_DETECTOR_REGWEN_7_REG_OFFSET 0x754

#define	PINMUX_WKUP_DETECTOR_REGWEN_7_REG_RESVAL 0x1u

#define	PINMUX_WKUP_DETECTOR_REGWEN_7_EN_7_BIT 0

#define	PINMUX_WKUP_DETECTOR_EN_EN_FIELD_WIDTH 1

#define	PINMUX_WKUP_DETECTOR_EN_MULTIREG_COUNT 8

#define	PINMUX_WKUP_DETECTOR_EN_0_REG_OFFSET 0x758

#define	PINMUX_WKUP_DETECTOR_EN_0_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_EN_0_EN_0_BIT 0

#define	PINMUX_WKUP_DETECTOR_EN_1_REG_OFFSET 0x75c

#define	PINMUX_WKUP_DETECTOR_EN_1_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_EN_1_EN_1_BIT 0

#define	PINMUX_WKUP_DETECTOR_EN_2_REG_OFFSET 0x760

#define	PINMUX_WKUP_DETECTOR_EN_2_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_EN_2_EN_2_BIT 0

#define	PINMUX_WKUP_DETECTOR_EN_3_REG_OFFSET 0x764

#define	PINMUX_WKUP_DETECTOR_EN_3_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_EN_3_EN_3_BIT 0

#define	PINMUX_WKUP_DETECTOR_EN_4_REG_OFFSET 0x768

#define	PINMUX_WKUP_DETECTOR_EN_4_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_EN_4_EN_4_BIT 0

#define	PINMUX_WKUP_DETECTOR_EN_5_REG_OFFSET 0x76c

#define	PINMUX_WKUP_DETECTOR_EN_5_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_EN_5_EN_5_BIT 0

#define	PINMUX_WKUP_DETECTOR_EN_6_REG_OFFSET 0x770

#define	PINMUX_WKUP_DETECTOR_EN_6_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_EN_6_EN_6_BIT 0

#define	PINMUX_WKUP_DETECTOR_EN_7_REG_OFFSET 0x774

#define	PINMUX_WKUP_DETECTOR_EN_7_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_EN_7_EN_7_BIT 0

#define	PINMUX_WKUP_DETECTOR_MODE_FIELD_WIDTH 3

#define	PINMUX_WKUP_DETECTOR_FILTER_FIELD_WIDTH 1

#define	PINMUX_WKUP_DETECTOR_MIODIO_FIELD_WIDTH 1

#define	PINMUX_WKUP_DETECTOR_MULTIREG_COUNT 8

#define	PINMUX_WKUP_DETECTOR_0_REG_OFFSET 0x778

#define	PINMUX_WKUP_DETECTOR_0_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_0_MODE_0_MASK 0x7u

#define	PINMUX_WKUP_DETECTOR_0_MODE_0_OFFSET 0

#define	PINMUX_WKUP_DETECTOR_0_MODE_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_0_MODE_0_MASK, .index = PINMUX_WKUP_DETECTOR_0_MODE_0_OFFSET })

#define	PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_POSEDGE 0x0

#define	PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_NEGEDGE 0x1

#define	PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_EDGE 0x2

#define	PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_TIMEDHIGH 0x3

#define	PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_TIMEDLOW 0x4

#define	PINMUX_WKUP_DETECTOR_0_FILTER_0_BIT 3

#define	PINMUX_WKUP_DETECTOR_0_MIODIO_0_BIT 4

#define	PINMUX_WKUP_DETECTOR_1_REG_OFFSET 0x77c

#define	PINMUX_WKUP_DETECTOR_1_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_1_MODE_1_MASK 0x7u

#define	PINMUX_WKUP_DETECTOR_1_MODE_1_OFFSET 0

#define	PINMUX_WKUP_DETECTOR_1_MODE_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_1_MODE_1_MASK, .index = PINMUX_WKUP_DETECTOR_1_MODE_1_OFFSET })

#define	PINMUX_WKUP_DETECTOR_1_FILTER_1_BIT 3

#define	PINMUX_WKUP_DETECTOR_1_MIODIO_1_BIT 4

#define	PINMUX_WKUP_DETECTOR_2_REG_OFFSET 0x780

#define	PINMUX_WKUP_DETECTOR_2_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_2_MODE_2_MASK 0x7u

#define	PINMUX_WKUP_DETECTOR_2_MODE_2_OFFSET 0

#define	PINMUX_WKUP_DETECTOR_2_MODE_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_2_MODE_2_MASK, .index = PINMUX_WKUP_DETECTOR_2_MODE_2_OFFSET })

#define	PINMUX_WKUP_DETECTOR_2_FILTER_2_BIT 3

#define	PINMUX_WKUP_DETECTOR_2_MIODIO_2_BIT 4

#define	PINMUX_WKUP_DETECTOR_3_REG_OFFSET 0x784

#define	PINMUX_WKUP_DETECTOR_3_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_3_MODE_3_MASK 0x7u

#define	PINMUX_WKUP_DETECTOR_3_MODE_3_OFFSET 0

#define	PINMUX_WKUP_DETECTOR_3_MODE_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_3_MODE_3_MASK, .index = PINMUX_WKUP_DETECTOR_3_MODE_3_OFFSET })

#define	PINMUX_WKUP_DETECTOR_3_FILTER_3_BIT 3

#define	PINMUX_WKUP_DETECTOR_3_MIODIO_3_BIT 4

#define	PINMUX_WKUP_DETECTOR_4_REG_OFFSET 0x788

#define	PINMUX_WKUP_DETECTOR_4_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_4_MODE_4_MASK 0x7u

#define	PINMUX_WKUP_DETECTOR_4_MODE_4_OFFSET 0

#define	PINMUX_WKUP_DETECTOR_4_MODE_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_4_MODE_4_MASK, .index = PINMUX_WKUP_DETECTOR_4_MODE_4_OFFSET })

#define	PINMUX_WKUP_DETECTOR_4_FILTER_4_BIT 3

#define	PINMUX_WKUP_DETECTOR_4_MIODIO_4_BIT 4

#define	PINMUX_WKUP_DETECTOR_5_REG_OFFSET 0x78c

#define	PINMUX_WKUP_DETECTOR_5_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_5_MODE_5_MASK 0x7u

#define	PINMUX_WKUP_DETECTOR_5_MODE_5_OFFSET 0

#define	PINMUX_WKUP_DETECTOR_5_MODE_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_5_MODE_5_MASK, .index = PINMUX_WKUP_DETECTOR_5_MODE_5_OFFSET })

#define	PINMUX_WKUP_DETECTOR_5_FILTER_5_BIT 3

#define	PINMUX_WKUP_DETECTOR_5_MIODIO_5_BIT 4

#define	PINMUX_WKUP_DETECTOR_6_REG_OFFSET 0x790

#define	PINMUX_WKUP_DETECTOR_6_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_6_MODE_6_MASK 0x7u

#define	PINMUX_WKUP_DETECTOR_6_MODE_6_OFFSET 0

#define	PINMUX_WKUP_DETECTOR_6_MODE_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_6_MODE_6_MASK, .index = PINMUX_WKUP_DETECTOR_6_MODE_6_OFFSET })

#define	PINMUX_WKUP_DETECTOR_6_FILTER_6_BIT 3

#define	PINMUX_WKUP_DETECTOR_6_MIODIO_6_BIT 4

#define	PINMUX_WKUP_DETECTOR_7_REG_OFFSET 0x794

#define	PINMUX_WKUP_DETECTOR_7_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_7_MODE_7_MASK 0x7u

#define	PINMUX_WKUP_DETECTOR_7_MODE_7_OFFSET 0

#define	PINMUX_WKUP_DETECTOR_7_MODE_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_7_MODE_7_MASK, .index = PINMUX_WKUP_DETECTOR_7_MODE_7_OFFSET })

#define	PINMUX_WKUP_DETECTOR_7_FILTER_7_BIT 3

#define	PINMUX_WKUP_DETECTOR_7_MIODIO_7_BIT 4

#define	PINMUX_WKUP_DETECTOR_CNT_TH_TH_FIELD_WIDTH 8

#define	PINMUX_WKUP_DETECTOR_CNT_TH_MULTIREG_COUNT 8

#define	PINMUX_WKUP_DETECTOR_CNT_TH_0_REG_OFFSET 0x798

#define	PINMUX_WKUP_DETECTOR_CNT_TH_0_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_CNT_TH_0_TH_0_MASK 0xffu

#define	PINMUX_WKUP_DETECTOR_CNT_TH_0_TH_0_OFFSET 0

#define	PINMUX_WKUP_DETECTOR_CNT_TH_0_TH_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_0_TH_0_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_0_TH_0_OFFSET })

#define	PINMUX_WKUP_DETECTOR_CNT_TH_1_REG_OFFSET 0x79c

#define	PINMUX_WKUP_DETECTOR_CNT_TH_1_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_CNT_TH_1_TH_1_MASK 0xffu

#define	PINMUX_WKUP_DETECTOR_CNT_TH_1_TH_1_OFFSET 0

#define	PINMUX_WKUP_DETECTOR_CNT_TH_1_TH_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_1_TH_1_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_1_TH_1_OFFSET })

#define	PINMUX_WKUP_DETECTOR_CNT_TH_2_REG_OFFSET 0x7a0

#define	PINMUX_WKUP_DETECTOR_CNT_TH_2_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_CNT_TH_2_TH_2_MASK 0xffu

#define	PINMUX_WKUP_DETECTOR_CNT_TH_2_TH_2_OFFSET 0

#define	PINMUX_WKUP_DETECTOR_CNT_TH_2_TH_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_2_TH_2_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_2_TH_2_OFFSET })

#define	PINMUX_WKUP_DETECTOR_CNT_TH_3_REG_OFFSET 0x7a4

#define	PINMUX_WKUP_DETECTOR_CNT_TH_3_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_CNT_TH_3_TH_3_MASK 0xffu

#define	PINMUX_WKUP_DETECTOR_CNT_TH_3_TH_3_OFFSET 0

#define	PINMUX_WKUP_DETECTOR_CNT_TH_3_TH_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_3_TH_3_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_3_TH_3_OFFSET })

#define	PINMUX_WKUP_DETECTOR_CNT_TH_4_REG_OFFSET 0x7a8

#define	PINMUX_WKUP_DETECTOR_CNT_TH_4_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_CNT_TH_4_TH_4_MASK 0xffu

#define	PINMUX_WKUP_DETECTOR_CNT_TH_4_TH_4_OFFSET 0

#define	PINMUX_WKUP_DETECTOR_CNT_TH_4_TH_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_4_TH_4_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_4_TH_4_OFFSET })

#define	PINMUX_WKUP_DETECTOR_CNT_TH_5_REG_OFFSET 0x7ac

#define	PINMUX_WKUP_DETECTOR_CNT_TH_5_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_CNT_TH_5_TH_5_MASK 0xffu

#define	PINMUX_WKUP_DETECTOR_CNT_TH_5_TH_5_OFFSET 0

#define	PINMUX_WKUP_DETECTOR_CNT_TH_5_TH_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_5_TH_5_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_5_TH_5_OFFSET })

#define	PINMUX_WKUP_DETECTOR_CNT_TH_6_REG_OFFSET 0x7b0

#define	PINMUX_WKUP_DETECTOR_CNT_TH_6_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_CNT_TH_6_TH_6_MASK 0xffu

#define	PINMUX_WKUP_DETECTOR_CNT_TH_6_TH_6_OFFSET 0

#define	PINMUX_WKUP_DETECTOR_CNT_TH_6_TH_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_6_TH_6_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_6_TH_6_OFFSET })

#define	PINMUX_WKUP_DETECTOR_CNT_TH_7_REG_OFFSET 0x7b4

#define	PINMUX_WKUP_DETECTOR_CNT_TH_7_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_CNT_TH_7_TH_7_MASK 0xffu

#define	PINMUX_WKUP_DETECTOR_CNT_TH_7_TH_7_OFFSET 0

#define	PINMUX_WKUP_DETECTOR_CNT_TH_7_TH_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_7_TH_7_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_7_TH_7_OFFSET })

#define	PINMUX_WKUP_DETECTOR_PADSEL_SEL_FIELD_WIDTH 7

#define	PINMUX_WKUP_DETECTOR_PADSEL_MULTIREG_COUNT 8

#define	PINMUX_WKUP_DETECTOR_PADSEL_0_REG_OFFSET 0x7b8

#define	PINMUX_WKUP_DETECTOR_PADSEL_0_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_PADSEL_0_SEL_0_MASK 0x7fu

#define	PINMUX_WKUP_DETECTOR_PADSEL_0_SEL_0_OFFSET 0

#define	PINMUX_WKUP_DETECTOR_PADSEL_0_SEL_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_0_SEL_0_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_0_SEL_0_OFFSET })

#define	PINMUX_WKUP_DETECTOR_PADSEL_1_REG_OFFSET 0x7bc

#define	PINMUX_WKUP_DETECTOR_PADSEL_1_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_PADSEL_1_SEL_1_MASK 0x7fu

#define	PINMUX_WKUP_DETECTOR_PADSEL_1_SEL_1_OFFSET 0

#define	PINMUX_WKUP_DETECTOR_PADSEL_1_SEL_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_1_SEL_1_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_1_SEL_1_OFFSET })

#define	PINMUX_WKUP_DETECTOR_PADSEL_2_REG_OFFSET 0x7c0

#define	PINMUX_WKUP_DETECTOR_PADSEL_2_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_PADSEL_2_SEL_2_MASK 0x7fu

#define	PINMUX_WKUP_DETECTOR_PADSEL_2_SEL_2_OFFSET 0

#define	PINMUX_WKUP_DETECTOR_PADSEL_2_SEL_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_2_SEL_2_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_2_SEL_2_OFFSET })

#define	PINMUX_WKUP_DETECTOR_PADSEL_3_REG_OFFSET 0x7c4

#define	PINMUX_WKUP_DETECTOR_PADSEL_3_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_PADSEL_3_SEL_3_MASK 0x7fu

#define	PINMUX_WKUP_DETECTOR_PADSEL_3_SEL_3_OFFSET 0

#define	PINMUX_WKUP_DETECTOR_PADSEL_3_SEL_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_3_SEL_3_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_3_SEL_3_OFFSET })

#define	PINMUX_WKUP_DETECTOR_PADSEL_4_REG_OFFSET 0x7c8

#define	PINMUX_WKUP_DETECTOR_PADSEL_4_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_PADSEL_4_SEL_4_MASK 0x7fu

#define	PINMUX_WKUP_DETECTOR_PADSEL_4_SEL_4_OFFSET 0

#define	PINMUX_WKUP_DETECTOR_PADSEL_4_SEL_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_4_SEL_4_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_4_SEL_4_OFFSET })

#define	PINMUX_WKUP_DETECTOR_PADSEL_5_REG_OFFSET 0x7cc

#define	PINMUX_WKUP_DETECTOR_PADSEL_5_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_PADSEL_5_SEL_5_MASK 0x7fu

#define	PINMUX_WKUP_DETECTOR_PADSEL_5_SEL_5_OFFSET 0

#define	PINMUX_WKUP_DETECTOR_PADSEL_5_SEL_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_5_SEL_5_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_5_SEL_5_OFFSET })

#define	PINMUX_WKUP_DETECTOR_PADSEL_6_REG_OFFSET 0x7d0

#define	PINMUX_WKUP_DETECTOR_PADSEL_6_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_PADSEL_6_SEL_6_MASK 0x7fu

#define	PINMUX_WKUP_DETECTOR_PADSEL_6_SEL_6_OFFSET 0

#define	PINMUX_WKUP_DETECTOR_PADSEL_6_SEL_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_6_SEL_6_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_6_SEL_6_OFFSET })

#define	PINMUX_WKUP_DETECTOR_PADSEL_7_REG_OFFSET 0x7d4

#define	PINMUX_WKUP_DETECTOR_PADSEL_7_REG_RESVAL 0x0u

#define	PINMUX_WKUP_DETECTOR_PADSEL_7_SEL_7_MASK 0x7fu

#define	PINMUX_WKUP_DETECTOR_PADSEL_7_SEL_7_OFFSET 0

#define	PINMUX_WKUP_DETECTOR_PADSEL_7_SEL_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_7_SEL_7_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_7_SEL_7_OFFSET })

#define	PINMUX_WKUP_CAUSE_CAUSE_FIELD_WIDTH 1

#define	PINMUX_WKUP_CAUSE_MULTIREG_COUNT 1

#define	PINMUX_WKUP_CAUSE_REG_OFFSET 0x7d8

#define	PINMUX_WKUP_CAUSE_REG_RESVAL 0x0u

#define	PINMUX_WKUP_CAUSE_CAUSE_0_BIT 0

#define	PINMUX_WKUP_CAUSE_CAUSE_1_BIT 1

#define	PINMUX_WKUP_CAUSE_CAUSE_2_BIT 2

#define	PINMUX_WKUP_CAUSE_CAUSE_3_BIT 3

#define	PINMUX_WKUP_CAUSE_CAUSE_4_BIT 4

#define	PINMUX_WKUP_CAUSE_CAUSE_5_BIT 5

#define	PINMUX_WKUP_CAUSE_CAUSE_6_BIT 6

#define	PINMUX_WKUP_CAUSE_CAUSE_7_BIT 7

Detailed Description

Generated register defines for pinmux.

Definition in file pinmux_regs.h.

Macro Definition Documentation

◆ PINMUX_ALERT_TEST_FATAL_FAULT_BIT

#define PINMUX_ALERT_TEST_FATAL_FAULT_BIT 0

Definition at line 46 of file pinmux_regs.h.

◆ PINMUX_ALERT_TEST_REG_OFFSET

#define PINMUX_ALERT_TEST_REG_OFFSET 0x0

Definition at line 44 of file pinmux_regs.h.

◆ PINMUX_ALERT_TEST_REG_RESVAL

#define PINMUX_ALERT_TEST_REG_RESVAL 0x0u

Definition at line 45 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_FIELD

#define PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_MASK, .index = PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_OFFSET })

Definition at line 995 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_MASK

#define PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_MASK 0xfu

Definition at line 993 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_OFFSET

#define PINMUX_DIO_PAD_ATTR_0_DRIVE_STRENGTH_0_OFFSET 20

Definition at line 994 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_0_INPUT_DISABLE_0_BIT

#define PINMUX_DIO_PAD_ATTR_0_INPUT_DISABLE_0_BIT 7

Definition at line 988 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_0_INVERT_0_BIT

#define PINMUX_DIO_PAD_ATTR_0_INVERT_0_BIT 0

Definition at line 979 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_0_KEEPER_EN_0_BIT

#define PINMUX_DIO_PAD_ATTR_0_KEEPER_EN_0_BIT 4

Definition at line 985 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_0_OD_EN_0_BIT

#define PINMUX_DIO_PAD_ATTR_0_OD_EN_0_BIT 6

Definition at line 987 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_0_PULL_EN_0_BIT

#define PINMUX_DIO_PAD_ATTR_0_PULL_EN_0_BIT 2

Definition at line 981 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_0_PULL_SELECT_0_BIT

#define PINMUX_DIO_PAD_ATTR_0_PULL_SELECT_0_BIT 3

Definition at line 982 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_0_PULL_SELECT_0_VALUE_PULL_DOWN

#define PINMUX_DIO_PAD_ATTR_0_PULL_SELECT_0_VALUE_PULL_DOWN 0x0

Definition at line 983 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_0_PULL_SELECT_0_VALUE_PULL_UP

#define PINMUX_DIO_PAD_ATTR_0_PULL_SELECT_0_VALUE_PULL_UP 0x1

Definition at line 984 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_0_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_0_REG_OFFSET 0x208

Definition at line 977 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_0_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_0_REG_RESVAL 0x0u

Definition at line 978 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_0_SCHMITT_EN_0_BIT

#define PINMUX_DIO_PAD_ATTR_0_SCHMITT_EN_0_BIT 5

Definition at line 986 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_FIELD

#define PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_MASK, .index = PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_OFFSET })

Definition at line 991 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_MASK

#define PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_MASK 0x3u

Definition at line 989 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_OFFSET

#define PINMUX_DIO_PAD_ATTR_0_SLEW_RATE_0_OFFSET 16

Definition at line 990 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_0_VIRTUAL_OD_EN_0_BIT

#define PINMUX_DIO_PAD_ATTR_0_VIRTUAL_OD_EN_0_BIT 1

Definition at line 980 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_FIELD

#define PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_MASK, .index = PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_OFFSET })

Definition at line 1195 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_MASK

#define PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_MASK 0xfu

Definition at line 1193 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_OFFSET

#define PINMUX_DIO_PAD_ATTR_10_DRIVE_STRENGTH_10_OFFSET 20

Definition at line 1194 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_10_INPUT_DISABLE_10_BIT

#define PINMUX_DIO_PAD_ATTR_10_INPUT_DISABLE_10_BIT 7

Definition at line 1188 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_10_INVERT_10_BIT

#define PINMUX_DIO_PAD_ATTR_10_INVERT_10_BIT 0

Definition at line 1181 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_10_KEEPER_EN_10_BIT

#define PINMUX_DIO_PAD_ATTR_10_KEEPER_EN_10_BIT 4

Definition at line 1185 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_10_OD_EN_10_BIT

#define PINMUX_DIO_PAD_ATTR_10_OD_EN_10_BIT 6

Definition at line 1187 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_10_PULL_EN_10_BIT

#define PINMUX_DIO_PAD_ATTR_10_PULL_EN_10_BIT 2

Definition at line 1183 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_10_PULL_SELECT_10_BIT

#define PINMUX_DIO_PAD_ATTR_10_PULL_SELECT_10_BIT 3

Definition at line 1184 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_10_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_10_REG_OFFSET 0x230

Definition at line 1179 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_10_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_10_REG_RESVAL 0x0u

Definition at line 1180 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_10_SCHMITT_EN_10_BIT

#define PINMUX_DIO_PAD_ATTR_10_SCHMITT_EN_10_BIT 5

Definition at line 1186 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_FIELD

#define PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_MASK, .index = PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_OFFSET })

Definition at line 1191 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_MASK

#define PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_MASK 0x3u

Definition at line 1189 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_OFFSET

#define PINMUX_DIO_PAD_ATTR_10_SLEW_RATE_10_OFFSET 16

Definition at line 1190 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_10_VIRTUAL_OD_EN_10_BIT

#define PINMUX_DIO_PAD_ATTR_10_VIRTUAL_OD_EN_10_BIT 1

Definition at line 1182 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_FIELD

#define PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_MASK, .index = PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_OFFSET })

Definition at line 1215 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_MASK

#define PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_MASK 0xfu

Definition at line 1213 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_OFFSET

#define PINMUX_DIO_PAD_ATTR_11_DRIVE_STRENGTH_11_OFFSET 20

Definition at line 1214 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_11_INPUT_DISABLE_11_BIT

#define PINMUX_DIO_PAD_ATTR_11_INPUT_DISABLE_11_BIT 7

Definition at line 1208 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_11_INVERT_11_BIT

#define PINMUX_DIO_PAD_ATTR_11_INVERT_11_BIT 0

Definition at line 1201 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_11_KEEPER_EN_11_BIT

#define PINMUX_DIO_PAD_ATTR_11_KEEPER_EN_11_BIT 4

Definition at line 1205 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_11_OD_EN_11_BIT

#define PINMUX_DIO_PAD_ATTR_11_OD_EN_11_BIT 6

Definition at line 1207 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_11_PULL_EN_11_BIT

#define PINMUX_DIO_PAD_ATTR_11_PULL_EN_11_BIT 2

Definition at line 1203 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_11_PULL_SELECT_11_BIT

#define PINMUX_DIO_PAD_ATTR_11_PULL_SELECT_11_BIT 3

Definition at line 1204 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_11_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_11_REG_OFFSET 0x234

Definition at line 1199 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_11_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_11_REG_RESVAL 0x0u

Definition at line 1200 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_11_SCHMITT_EN_11_BIT

#define PINMUX_DIO_PAD_ATTR_11_SCHMITT_EN_11_BIT 5

Definition at line 1206 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_FIELD

#define PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_MASK, .index = PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_OFFSET })

Definition at line 1211 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_MASK

#define PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_MASK 0x3u

Definition at line 1209 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_OFFSET

#define PINMUX_DIO_PAD_ATTR_11_SLEW_RATE_11_OFFSET 16

Definition at line 1210 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_11_VIRTUAL_OD_EN_11_BIT

#define PINMUX_DIO_PAD_ATTR_11_VIRTUAL_OD_EN_11_BIT 1

Definition at line 1202 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_FIELD

#define PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_MASK, .index = PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_OFFSET })

Definition at line 1235 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_MASK

#define PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_MASK 0xfu

Definition at line 1233 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_OFFSET

#define PINMUX_DIO_PAD_ATTR_12_DRIVE_STRENGTH_12_OFFSET 20

Definition at line 1234 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_12_INPUT_DISABLE_12_BIT

#define PINMUX_DIO_PAD_ATTR_12_INPUT_DISABLE_12_BIT 7

Definition at line 1228 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_12_INVERT_12_BIT

#define PINMUX_DIO_PAD_ATTR_12_INVERT_12_BIT 0

Definition at line 1221 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_12_KEEPER_EN_12_BIT

#define PINMUX_DIO_PAD_ATTR_12_KEEPER_EN_12_BIT 4

Definition at line 1225 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_12_OD_EN_12_BIT

#define PINMUX_DIO_PAD_ATTR_12_OD_EN_12_BIT 6

Definition at line 1227 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_12_PULL_EN_12_BIT

#define PINMUX_DIO_PAD_ATTR_12_PULL_EN_12_BIT 2

Definition at line 1223 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_12_PULL_SELECT_12_BIT

#define PINMUX_DIO_PAD_ATTR_12_PULL_SELECT_12_BIT 3

Definition at line 1224 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_12_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_12_REG_OFFSET 0x238

Definition at line 1219 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_12_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_12_REG_RESVAL 0x0u

Definition at line 1220 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_12_SCHMITT_EN_12_BIT

#define PINMUX_DIO_PAD_ATTR_12_SCHMITT_EN_12_BIT 5

Definition at line 1226 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_FIELD

#define PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_MASK, .index = PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_OFFSET })

Definition at line 1231 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_MASK

#define PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_MASK 0x3u

Definition at line 1229 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_OFFSET

#define PINMUX_DIO_PAD_ATTR_12_SLEW_RATE_12_OFFSET 16

Definition at line 1230 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_12_VIRTUAL_OD_EN_12_BIT

#define PINMUX_DIO_PAD_ATTR_12_VIRTUAL_OD_EN_12_BIT 1

Definition at line 1222 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_FIELD

#define PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_MASK, .index = PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_OFFSET })

Definition at line 1255 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_MASK

#define PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_MASK 0xfu

Definition at line 1253 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_OFFSET

#define PINMUX_DIO_PAD_ATTR_13_DRIVE_STRENGTH_13_OFFSET 20

Definition at line 1254 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_13_INPUT_DISABLE_13_BIT

#define PINMUX_DIO_PAD_ATTR_13_INPUT_DISABLE_13_BIT 7

Definition at line 1248 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_13_INVERT_13_BIT

#define PINMUX_DIO_PAD_ATTR_13_INVERT_13_BIT 0

Definition at line 1241 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_13_KEEPER_EN_13_BIT

#define PINMUX_DIO_PAD_ATTR_13_KEEPER_EN_13_BIT 4

Definition at line 1245 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_13_OD_EN_13_BIT

#define PINMUX_DIO_PAD_ATTR_13_OD_EN_13_BIT 6

Definition at line 1247 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_13_PULL_EN_13_BIT

#define PINMUX_DIO_PAD_ATTR_13_PULL_EN_13_BIT 2

Definition at line 1243 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_13_PULL_SELECT_13_BIT

#define PINMUX_DIO_PAD_ATTR_13_PULL_SELECT_13_BIT 3

Definition at line 1244 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_13_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_13_REG_OFFSET 0x23c

Definition at line 1239 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_13_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_13_REG_RESVAL 0x0u

Definition at line 1240 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_13_SCHMITT_EN_13_BIT

#define PINMUX_DIO_PAD_ATTR_13_SCHMITT_EN_13_BIT 5

Definition at line 1246 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_FIELD

#define PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_MASK, .index = PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_OFFSET })

Definition at line 1251 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_MASK

#define PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_MASK 0x3u

Definition at line 1249 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_OFFSET

#define PINMUX_DIO_PAD_ATTR_13_SLEW_RATE_13_OFFSET 16

Definition at line 1250 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_13_VIRTUAL_OD_EN_13_BIT

#define PINMUX_DIO_PAD_ATTR_13_VIRTUAL_OD_EN_13_BIT 1

Definition at line 1242 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_FIELD

#define PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_MASK, .index = PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_OFFSET })

Definition at line 1275 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_MASK

#define PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_MASK 0xfu

Definition at line 1273 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_OFFSET

#define PINMUX_DIO_PAD_ATTR_14_DRIVE_STRENGTH_14_OFFSET 20

Definition at line 1274 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_14_INPUT_DISABLE_14_BIT

#define PINMUX_DIO_PAD_ATTR_14_INPUT_DISABLE_14_BIT 7

Definition at line 1268 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_14_INVERT_14_BIT

#define PINMUX_DIO_PAD_ATTR_14_INVERT_14_BIT 0

Definition at line 1261 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_14_KEEPER_EN_14_BIT

#define PINMUX_DIO_PAD_ATTR_14_KEEPER_EN_14_BIT 4

Definition at line 1265 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_14_OD_EN_14_BIT

#define PINMUX_DIO_PAD_ATTR_14_OD_EN_14_BIT 6

Definition at line 1267 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_14_PULL_EN_14_BIT

#define PINMUX_DIO_PAD_ATTR_14_PULL_EN_14_BIT 2

Definition at line 1263 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_14_PULL_SELECT_14_BIT

#define PINMUX_DIO_PAD_ATTR_14_PULL_SELECT_14_BIT 3

Definition at line 1264 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_14_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_14_REG_OFFSET 0x240

Definition at line 1259 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_14_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_14_REG_RESVAL 0x0u

Definition at line 1260 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_14_SCHMITT_EN_14_BIT

#define PINMUX_DIO_PAD_ATTR_14_SCHMITT_EN_14_BIT 5

Definition at line 1266 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_FIELD

#define PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_MASK, .index = PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_OFFSET })

Definition at line 1271 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_MASK

#define PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_MASK 0x3u

Definition at line 1269 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_OFFSET

#define PINMUX_DIO_PAD_ATTR_14_SLEW_RATE_14_OFFSET 16

Definition at line 1270 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_14_VIRTUAL_OD_EN_14_BIT

#define PINMUX_DIO_PAD_ATTR_14_VIRTUAL_OD_EN_14_BIT 1

Definition at line 1262 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_FIELD

#define PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_MASK, .index = PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_OFFSET })

Definition at line 1295 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_MASK

#define PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_MASK 0xfu

Definition at line 1293 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_OFFSET

#define PINMUX_DIO_PAD_ATTR_15_DRIVE_STRENGTH_15_OFFSET 20

Definition at line 1294 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_15_INPUT_DISABLE_15_BIT

#define PINMUX_DIO_PAD_ATTR_15_INPUT_DISABLE_15_BIT 7

Definition at line 1288 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_15_INVERT_15_BIT

#define PINMUX_DIO_PAD_ATTR_15_INVERT_15_BIT 0

Definition at line 1281 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_15_KEEPER_EN_15_BIT

#define PINMUX_DIO_PAD_ATTR_15_KEEPER_EN_15_BIT 4

Definition at line 1285 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_15_OD_EN_15_BIT

#define PINMUX_DIO_PAD_ATTR_15_OD_EN_15_BIT 6

Definition at line 1287 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_15_PULL_EN_15_BIT

#define PINMUX_DIO_PAD_ATTR_15_PULL_EN_15_BIT 2

Definition at line 1283 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_15_PULL_SELECT_15_BIT

#define PINMUX_DIO_PAD_ATTR_15_PULL_SELECT_15_BIT 3

Definition at line 1284 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_15_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_15_REG_OFFSET 0x244

Definition at line 1279 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_15_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_15_REG_RESVAL 0x0u

Definition at line 1280 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_15_SCHMITT_EN_15_BIT

#define PINMUX_DIO_PAD_ATTR_15_SCHMITT_EN_15_BIT 5

Definition at line 1286 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_FIELD

#define PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_MASK, .index = PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_OFFSET })

Definition at line 1291 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_MASK

#define PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_MASK 0x3u

Definition at line 1289 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_OFFSET

#define PINMUX_DIO_PAD_ATTR_15_SLEW_RATE_15_OFFSET 16

Definition at line 1290 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_15_VIRTUAL_OD_EN_15_BIT

#define PINMUX_DIO_PAD_ATTR_15_VIRTUAL_OD_EN_15_BIT 1

Definition at line 1282 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_16_DRIVE_STRENGTH_16_FIELD

#define PINMUX_DIO_PAD_ATTR_16_DRIVE_STRENGTH_16_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_16_DRIVE_STRENGTH_16_MASK, .index = PINMUX_DIO_PAD_ATTR_16_DRIVE_STRENGTH_16_OFFSET })

Definition at line 1315 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_16_DRIVE_STRENGTH_16_MASK

#define PINMUX_DIO_PAD_ATTR_16_DRIVE_STRENGTH_16_MASK 0xfu

Definition at line 1313 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_16_DRIVE_STRENGTH_16_OFFSET

#define PINMUX_DIO_PAD_ATTR_16_DRIVE_STRENGTH_16_OFFSET 20

Definition at line 1314 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_16_INPUT_DISABLE_16_BIT

#define PINMUX_DIO_PAD_ATTR_16_INPUT_DISABLE_16_BIT 7

Definition at line 1308 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_16_INVERT_16_BIT

#define PINMUX_DIO_PAD_ATTR_16_INVERT_16_BIT 0

Definition at line 1301 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_16_KEEPER_EN_16_BIT

#define PINMUX_DIO_PAD_ATTR_16_KEEPER_EN_16_BIT 4

Definition at line 1305 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_16_OD_EN_16_BIT

#define PINMUX_DIO_PAD_ATTR_16_OD_EN_16_BIT 6

Definition at line 1307 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_16_PULL_EN_16_BIT

#define PINMUX_DIO_PAD_ATTR_16_PULL_EN_16_BIT 2

Definition at line 1303 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_16_PULL_SELECT_16_BIT

#define PINMUX_DIO_PAD_ATTR_16_PULL_SELECT_16_BIT 3

Definition at line 1304 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_16_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_16_REG_OFFSET 0x248

Definition at line 1299 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_16_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_16_REG_RESVAL 0x0u

Definition at line 1300 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_16_SCHMITT_EN_16_BIT

#define PINMUX_DIO_PAD_ATTR_16_SCHMITT_EN_16_BIT 5

Definition at line 1306 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_16_SLEW_RATE_16_FIELD

#define PINMUX_DIO_PAD_ATTR_16_SLEW_RATE_16_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_16_SLEW_RATE_16_MASK, .index = PINMUX_DIO_PAD_ATTR_16_SLEW_RATE_16_OFFSET })

Definition at line 1311 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_16_SLEW_RATE_16_MASK

#define PINMUX_DIO_PAD_ATTR_16_SLEW_RATE_16_MASK 0x3u

Definition at line 1309 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_16_SLEW_RATE_16_OFFSET

#define PINMUX_DIO_PAD_ATTR_16_SLEW_RATE_16_OFFSET 16

Definition at line 1310 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_16_VIRTUAL_OD_EN_16_BIT

#define PINMUX_DIO_PAD_ATTR_16_VIRTUAL_OD_EN_16_BIT 1

Definition at line 1302 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_17_DRIVE_STRENGTH_17_FIELD

#define PINMUX_DIO_PAD_ATTR_17_DRIVE_STRENGTH_17_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_17_DRIVE_STRENGTH_17_MASK, .index = PINMUX_DIO_PAD_ATTR_17_DRIVE_STRENGTH_17_OFFSET })

Definition at line 1335 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_17_DRIVE_STRENGTH_17_MASK

#define PINMUX_DIO_PAD_ATTR_17_DRIVE_STRENGTH_17_MASK 0xfu

Definition at line 1333 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_17_DRIVE_STRENGTH_17_OFFSET

#define PINMUX_DIO_PAD_ATTR_17_DRIVE_STRENGTH_17_OFFSET 20

Definition at line 1334 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_17_INPUT_DISABLE_17_BIT

#define PINMUX_DIO_PAD_ATTR_17_INPUT_DISABLE_17_BIT 7

Definition at line 1328 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_17_INVERT_17_BIT

#define PINMUX_DIO_PAD_ATTR_17_INVERT_17_BIT 0

Definition at line 1321 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_17_KEEPER_EN_17_BIT

#define PINMUX_DIO_PAD_ATTR_17_KEEPER_EN_17_BIT 4

Definition at line 1325 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_17_OD_EN_17_BIT

#define PINMUX_DIO_PAD_ATTR_17_OD_EN_17_BIT 6

Definition at line 1327 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_17_PULL_EN_17_BIT

#define PINMUX_DIO_PAD_ATTR_17_PULL_EN_17_BIT 2

Definition at line 1323 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_17_PULL_SELECT_17_BIT

#define PINMUX_DIO_PAD_ATTR_17_PULL_SELECT_17_BIT 3

Definition at line 1324 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_17_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_17_REG_OFFSET 0x24c

Definition at line 1319 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_17_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_17_REG_RESVAL 0x0u

Definition at line 1320 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_17_SCHMITT_EN_17_BIT

#define PINMUX_DIO_PAD_ATTR_17_SCHMITT_EN_17_BIT 5

Definition at line 1326 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_17_SLEW_RATE_17_FIELD

#define PINMUX_DIO_PAD_ATTR_17_SLEW_RATE_17_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_17_SLEW_RATE_17_MASK, .index = PINMUX_DIO_PAD_ATTR_17_SLEW_RATE_17_OFFSET })

Definition at line 1331 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_17_SLEW_RATE_17_MASK

#define PINMUX_DIO_PAD_ATTR_17_SLEW_RATE_17_MASK 0x3u

Definition at line 1329 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_17_SLEW_RATE_17_OFFSET

#define PINMUX_DIO_PAD_ATTR_17_SLEW_RATE_17_OFFSET 16

Definition at line 1330 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_17_VIRTUAL_OD_EN_17_BIT

#define PINMUX_DIO_PAD_ATTR_17_VIRTUAL_OD_EN_17_BIT 1

Definition at line 1322 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_18_DRIVE_STRENGTH_18_FIELD

#define PINMUX_DIO_PAD_ATTR_18_DRIVE_STRENGTH_18_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_18_DRIVE_STRENGTH_18_MASK, .index = PINMUX_DIO_PAD_ATTR_18_DRIVE_STRENGTH_18_OFFSET })

Definition at line 1355 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_18_DRIVE_STRENGTH_18_MASK

#define PINMUX_DIO_PAD_ATTR_18_DRIVE_STRENGTH_18_MASK 0xfu

Definition at line 1353 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_18_DRIVE_STRENGTH_18_OFFSET

#define PINMUX_DIO_PAD_ATTR_18_DRIVE_STRENGTH_18_OFFSET 20

Definition at line 1354 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_18_INPUT_DISABLE_18_BIT

#define PINMUX_DIO_PAD_ATTR_18_INPUT_DISABLE_18_BIT 7

Definition at line 1348 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_18_INVERT_18_BIT

#define PINMUX_DIO_PAD_ATTR_18_INVERT_18_BIT 0

Definition at line 1341 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_18_KEEPER_EN_18_BIT

#define PINMUX_DIO_PAD_ATTR_18_KEEPER_EN_18_BIT 4

Definition at line 1345 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_18_OD_EN_18_BIT

#define PINMUX_DIO_PAD_ATTR_18_OD_EN_18_BIT 6

Definition at line 1347 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_18_PULL_EN_18_BIT

#define PINMUX_DIO_PAD_ATTR_18_PULL_EN_18_BIT 2

Definition at line 1343 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_18_PULL_SELECT_18_BIT

#define PINMUX_DIO_PAD_ATTR_18_PULL_SELECT_18_BIT 3

Definition at line 1344 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_18_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_18_REG_OFFSET 0x250

Definition at line 1339 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_18_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_18_REG_RESVAL 0x0u

Definition at line 1340 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_18_SCHMITT_EN_18_BIT

#define PINMUX_DIO_PAD_ATTR_18_SCHMITT_EN_18_BIT 5

Definition at line 1346 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_18_SLEW_RATE_18_FIELD

#define PINMUX_DIO_PAD_ATTR_18_SLEW_RATE_18_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_18_SLEW_RATE_18_MASK, .index = PINMUX_DIO_PAD_ATTR_18_SLEW_RATE_18_OFFSET })

Definition at line 1351 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_18_SLEW_RATE_18_MASK

#define PINMUX_DIO_PAD_ATTR_18_SLEW_RATE_18_MASK 0x3u

Definition at line 1349 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_18_SLEW_RATE_18_OFFSET

#define PINMUX_DIO_PAD_ATTR_18_SLEW_RATE_18_OFFSET 16

Definition at line 1350 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_18_VIRTUAL_OD_EN_18_BIT

#define PINMUX_DIO_PAD_ATTR_18_VIRTUAL_OD_EN_18_BIT 1

Definition at line 1342 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_19_DRIVE_STRENGTH_19_FIELD

#define PINMUX_DIO_PAD_ATTR_19_DRIVE_STRENGTH_19_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_19_DRIVE_STRENGTH_19_MASK, .index = PINMUX_DIO_PAD_ATTR_19_DRIVE_STRENGTH_19_OFFSET })

Definition at line 1375 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_19_DRIVE_STRENGTH_19_MASK

#define PINMUX_DIO_PAD_ATTR_19_DRIVE_STRENGTH_19_MASK 0xfu

Definition at line 1373 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_19_DRIVE_STRENGTH_19_OFFSET

#define PINMUX_DIO_PAD_ATTR_19_DRIVE_STRENGTH_19_OFFSET 20

Definition at line 1374 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_19_INPUT_DISABLE_19_BIT

#define PINMUX_DIO_PAD_ATTR_19_INPUT_DISABLE_19_BIT 7

Definition at line 1368 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_19_INVERT_19_BIT

#define PINMUX_DIO_PAD_ATTR_19_INVERT_19_BIT 0

Definition at line 1361 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_19_KEEPER_EN_19_BIT

#define PINMUX_DIO_PAD_ATTR_19_KEEPER_EN_19_BIT 4

Definition at line 1365 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_19_OD_EN_19_BIT

#define PINMUX_DIO_PAD_ATTR_19_OD_EN_19_BIT 6

Definition at line 1367 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_19_PULL_EN_19_BIT

#define PINMUX_DIO_PAD_ATTR_19_PULL_EN_19_BIT 2

Definition at line 1363 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_19_PULL_SELECT_19_BIT

#define PINMUX_DIO_PAD_ATTR_19_PULL_SELECT_19_BIT 3

Definition at line 1364 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_19_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_19_REG_OFFSET 0x254

Definition at line 1359 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_19_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_19_REG_RESVAL 0x0u

Definition at line 1360 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_19_SCHMITT_EN_19_BIT

#define PINMUX_DIO_PAD_ATTR_19_SCHMITT_EN_19_BIT 5

Definition at line 1366 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_19_SLEW_RATE_19_FIELD

#define PINMUX_DIO_PAD_ATTR_19_SLEW_RATE_19_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_19_SLEW_RATE_19_MASK, .index = PINMUX_DIO_PAD_ATTR_19_SLEW_RATE_19_OFFSET })

Definition at line 1371 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_19_SLEW_RATE_19_MASK

#define PINMUX_DIO_PAD_ATTR_19_SLEW_RATE_19_MASK 0x3u

Definition at line 1369 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_19_SLEW_RATE_19_OFFSET

#define PINMUX_DIO_PAD_ATTR_19_SLEW_RATE_19_OFFSET 16

Definition at line 1370 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_19_VIRTUAL_OD_EN_19_BIT

#define PINMUX_DIO_PAD_ATTR_19_VIRTUAL_OD_EN_19_BIT 1

Definition at line 1362 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_FIELD

#define PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_MASK, .index = PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_OFFSET })

Definition at line 1015 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_MASK

#define PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_MASK 0xfu

Definition at line 1013 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_OFFSET

#define PINMUX_DIO_PAD_ATTR_1_DRIVE_STRENGTH_1_OFFSET 20

Definition at line 1014 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_1_INPUT_DISABLE_1_BIT

#define PINMUX_DIO_PAD_ATTR_1_INPUT_DISABLE_1_BIT 7

Definition at line 1008 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_1_INVERT_1_BIT

#define PINMUX_DIO_PAD_ATTR_1_INVERT_1_BIT 0

Definition at line 1001 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_1_KEEPER_EN_1_BIT

#define PINMUX_DIO_PAD_ATTR_1_KEEPER_EN_1_BIT 4

Definition at line 1005 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_1_OD_EN_1_BIT

#define PINMUX_DIO_PAD_ATTR_1_OD_EN_1_BIT 6

Definition at line 1007 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_1_PULL_EN_1_BIT

#define PINMUX_DIO_PAD_ATTR_1_PULL_EN_1_BIT 2

Definition at line 1003 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_1_PULL_SELECT_1_BIT

#define PINMUX_DIO_PAD_ATTR_1_PULL_SELECT_1_BIT 3

Definition at line 1004 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_1_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_1_REG_OFFSET 0x20c

Definition at line 999 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_1_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_1_REG_RESVAL 0x0u

Definition at line 1000 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_1_SCHMITT_EN_1_BIT

#define PINMUX_DIO_PAD_ATTR_1_SCHMITT_EN_1_BIT 5

Definition at line 1006 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_FIELD

#define PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_MASK, .index = PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_OFFSET })

Definition at line 1011 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_MASK

#define PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_MASK 0x3u

Definition at line 1009 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_OFFSET

#define PINMUX_DIO_PAD_ATTR_1_SLEW_RATE_1_OFFSET 16

Definition at line 1010 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_1_VIRTUAL_OD_EN_1_BIT

#define PINMUX_DIO_PAD_ATTR_1_VIRTUAL_OD_EN_1_BIT 1

Definition at line 1002 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_20_DRIVE_STRENGTH_20_FIELD

#define PINMUX_DIO_PAD_ATTR_20_DRIVE_STRENGTH_20_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_20_DRIVE_STRENGTH_20_MASK, .index = PINMUX_DIO_PAD_ATTR_20_DRIVE_STRENGTH_20_OFFSET })

Definition at line 1395 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_20_DRIVE_STRENGTH_20_MASK

#define PINMUX_DIO_PAD_ATTR_20_DRIVE_STRENGTH_20_MASK 0xfu

Definition at line 1393 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_20_DRIVE_STRENGTH_20_OFFSET

#define PINMUX_DIO_PAD_ATTR_20_DRIVE_STRENGTH_20_OFFSET 20

Definition at line 1394 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_20_INPUT_DISABLE_20_BIT

#define PINMUX_DIO_PAD_ATTR_20_INPUT_DISABLE_20_BIT 7

Definition at line 1388 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_20_INVERT_20_BIT

#define PINMUX_DIO_PAD_ATTR_20_INVERT_20_BIT 0

Definition at line 1381 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_20_KEEPER_EN_20_BIT

#define PINMUX_DIO_PAD_ATTR_20_KEEPER_EN_20_BIT 4

Definition at line 1385 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_20_OD_EN_20_BIT

#define PINMUX_DIO_PAD_ATTR_20_OD_EN_20_BIT 6

Definition at line 1387 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_20_PULL_EN_20_BIT

#define PINMUX_DIO_PAD_ATTR_20_PULL_EN_20_BIT 2

Definition at line 1383 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_20_PULL_SELECT_20_BIT

#define PINMUX_DIO_PAD_ATTR_20_PULL_SELECT_20_BIT 3

Definition at line 1384 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_20_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_20_REG_OFFSET 0x258

Definition at line 1379 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_20_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_20_REG_RESVAL 0x0u

Definition at line 1380 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_20_SCHMITT_EN_20_BIT

#define PINMUX_DIO_PAD_ATTR_20_SCHMITT_EN_20_BIT 5

Definition at line 1386 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_20_SLEW_RATE_20_FIELD

#define PINMUX_DIO_PAD_ATTR_20_SLEW_RATE_20_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_20_SLEW_RATE_20_MASK, .index = PINMUX_DIO_PAD_ATTR_20_SLEW_RATE_20_OFFSET })

Definition at line 1391 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_20_SLEW_RATE_20_MASK

#define PINMUX_DIO_PAD_ATTR_20_SLEW_RATE_20_MASK 0x3u

Definition at line 1389 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_20_SLEW_RATE_20_OFFSET

#define PINMUX_DIO_PAD_ATTR_20_SLEW_RATE_20_OFFSET 16

Definition at line 1390 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_20_VIRTUAL_OD_EN_20_BIT

#define PINMUX_DIO_PAD_ATTR_20_VIRTUAL_OD_EN_20_BIT 1

Definition at line 1382 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_21_DRIVE_STRENGTH_21_FIELD

#define PINMUX_DIO_PAD_ATTR_21_DRIVE_STRENGTH_21_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_21_DRIVE_STRENGTH_21_MASK, .index = PINMUX_DIO_PAD_ATTR_21_DRIVE_STRENGTH_21_OFFSET })

Definition at line 1415 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_21_DRIVE_STRENGTH_21_MASK

#define PINMUX_DIO_PAD_ATTR_21_DRIVE_STRENGTH_21_MASK 0xfu

Definition at line 1413 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_21_DRIVE_STRENGTH_21_OFFSET

#define PINMUX_DIO_PAD_ATTR_21_DRIVE_STRENGTH_21_OFFSET 20

Definition at line 1414 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_21_INPUT_DISABLE_21_BIT

#define PINMUX_DIO_PAD_ATTR_21_INPUT_DISABLE_21_BIT 7

Definition at line 1408 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_21_INVERT_21_BIT

#define PINMUX_DIO_PAD_ATTR_21_INVERT_21_BIT 0

Definition at line 1401 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_21_KEEPER_EN_21_BIT

#define PINMUX_DIO_PAD_ATTR_21_KEEPER_EN_21_BIT 4

Definition at line 1405 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_21_OD_EN_21_BIT

#define PINMUX_DIO_PAD_ATTR_21_OD_EN_21_BIT 6

Definition at line 1407 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_21_PULL_EN_21_BIT

#define PINMUX_DIO_PAD_ATTR_21_PULL_EN_21_BIT 2

Definition at line 1403 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_21_PULL_SELECT_21_BIT

#define PINMUX_DIO_PAD_ATTR_21_PULL_SELECT_21_BIT 3

Definition at line 1404 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_21_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_21_REG_OFFSET 0x25c

Definition at line 1399 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_21_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_21_REG_RESVAL 0x0u

Definition at line 1400 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_21_SCHMITT_EN_21_BIT

#define PINMUX_DIO_PAD_ATTR_21_SCHMITT_EN_21_BIT 5

Definition at line 1406 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_21_SLEW_RATE_21_FIELD

#define PINMUX_DIO_PAD_ATTR_21_SLEW_RATE_21_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_21_SLEW_RATE_21_MASK, .index = PINMUX_DIO_PAD_ATTR_21_SLEW_RATE_21_OFFSET })

Definition at line 1411 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_21_SLEW_RATE_21_MASK

#define PINMUX_DIO_PAD_ATTR_21_SLEW_RATE_21_MASK 0x3u

Definition at line 1409 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_21_SLEW_RATE_21_OFFSET

#define PINMUX_DIO_PAD_ATTR_21_SLEW_RATE_21_OFFSET 16

Definition at line 1410 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_21_VIRTUAL_OD_EN_21_BIT

#define PINMUX_DIO_PAD_ATTR_21_VIRTUAL_OD_EN_21_BIT 1

Definition at line 1402 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_22_DRIVE_STRENGTH_22_FIELD

#define PINMUX_DIO_PAD_ATTR_22_DRIVE_STRENGTH_22_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_22_DRIVE_STRENGTH_22_MASK, .index = PINMUX_DIO_PAD_ATTR_22_DRIVE_STRENGTH_22_OFFSET })

Definition at line 1435 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_22_DRIVE_STRENGTH_22_MASK

#define PINMUX_DIO_PAD_ATTR_22_DRIVE_STRENGTH_22_MASK 0xfu

Definition at line 1433 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_22_DRIVE_STRENGTH_22_OFFSET

#define PINMUX_DIO_PAD_ATTR_22_DRIVE_STRENGTH_22_OFFSET 20

Definition at line 1434 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_22_INPUT_DISABLE_22_BIT

#define PINMUX_DIO_PAD_ATTR_22_INPUT_DISABLE_22_BIT 7

Definition at line 1428 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_22_INVERT_22_BIT

#define PINMUX_DIO_PAD_ATTR_22_INVERT_22_BIT 0

Definition at line 1421 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_22_KEEPER_EN_22_BIT

#define PINMUX_DIO_PAD_ATTR_22_KEEPER_EN_22_BIT 4

Definition at line 1425 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_22_OD_EN_22_BIT

#define PINMUX_DIO_PAD_ATTR_22_OD_EN_22_BIT 6

Definition at line 1427 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_22_PULL_EN_22_BIT

#define PINMUX_DIO_PAD_ATTR_22_PULL_EN_22_BIT 2

Definition at line 1423 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_22_PULL_SELECT_22_BIT

#define PINMUX_DIO_PAD_ATTR_22_PULL_SELECT_22_BIT 3

Definition at line 1424 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_22_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_22_REG_OFFSET 0x260

Definition at line 1419 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_22_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_22_REG_RESVAL 0x0u

Definition at line 1420 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_22_SCHMITT_EN_22_BIT

#define PINMUX_DIO_PAD_ATTR_22_SCHMITT_EN_22_BIT 5

Definition at line 1426 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_22_SLEW_RATE_22_FIELD

#define PINMUX_DIO_PAD_ATTR_22_SLEW_RATE_22_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_22_SLEW_RATE_22_MASK, .index = PINMUX_DIO_PAD_ATTR_22_SLEW_RATE_22_OFFSET })

Definition at line 1431 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_22_SLEW_RATE_22_MASK

#define PINMUX_DIO_PAD_ATTR_22_SLEW_RATE_22_MASK 0x3u

Definition at line 1429 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_22_SLEW_RATE_22_OFFSET

#define PINMUX_DIO_PAD_ATTR_22_SLEW_RATE_22_OFFSET 16

Definition at line 1430 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_22_VIRTUAL_OD_EN_22_BIT

#define PINMUX_DIO_PAD_ATTR_22_VIRTUAL_OD_EN_22_BIT 1

Definition at line 1422 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_23_DRIVE_STRENGTH_23_FIELD

#define PINMUX_DIO_PAD_ATTR_23_DRIVE_STRENGTH_23_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_23_DRIVE_STRENGTH_23_MASK, .index = PINMUX_DIO_PAD_ATTR_23_DRIVE_STRENGTH_23_OFFSET })

Definition at line 1455 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_23_DRIVE_STRENGTH_23_MASK

#define PINMUX_DIO_PAD_ATTR_23_DRIVE_STRENGTH_23_MASK 0xfu

Definition at line 1453 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_23_DRIVE_STRENGTH_23_OFFSET

#define PINMUX_DIO_PAD_ATTR_23_DRIVE_STRENGTH_23_OFFSET 20

Definition at line 1454 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_23_INPUT_DISABLE_23_BIT

#define PINMUX_DIO_PAD_ATTR_23_INPUT_DISABLE_23_BIT 7

Definition at line 1448 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_23_INVERT_23_BIT

#define PINMUX_DIO_PAD_ATTR_23_INVERT_23_BIT 0

Definition at line 1441 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_23_KEEPER_EN_23_BIT

#define PINMUX_DIO_PAD_ATTR_23_KEEPER_EN_23_BIT 4

Definition at line 1445 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_23_OD_EN_23_BIT

#define PINMUX_DIO_PAD_ATTR_23_OD_EN_23_BIT 6

Definition at line 1447 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_23_PULL_EN_23_BIT

#define PINMUX_DIO_PAD_ATTR_23_PULL_EN_23_BIT 2

Definition at line 1443 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_23_PULL_SELECT_23_BIT

#define PINMUX_DIO_PAD_ATTR_23_PULL_SELECT_23_BIT 3

Definition at line 1444 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_23_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_23_REG_OFFSET 0x264

Definition at line 1439 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_23_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_23_REG_RESVAL 0x0u

Definition at line 1440 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_23_SCHMITT_EN_23_BIT

#define PINMUX_DIO_PAD_ATTR_23_SCHMITT_EN_23_BIT 5

Definition at line 1446 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_23_SLEW_RATE_23_FIELD

#define PINMUX_DIO_PAD_ATTR_23_SLEW_RATE_23_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_23_SLEW_RATE_23_MASK, .index = PINMUX_DIO_PAD_ATTR_23_SLEW_RATE_23_OFFSET })

Definition at line 1451 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_23_SLEW_RATE_23_MASK

#define PINMUX_DIO_PAD_ATTR_23_SLEW_RATE_23_MASK 0x3u

Definition at line 1449 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_23_SLEW_RATE_23_OFFSET

#define PINMUX_DIO_PAD_ATTR_23_SLEW_RATE_23_OFFSET 16

Definition at line 1450 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_23_VIRTUAL_OD_EN_23_BIT

#define PINMUX_DIO_PAD_ATTR_23_VIRTUAL_OD_EN_23_BIT 1

Definition at line 1442 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_24_DRIVE_STRENGTH_24_FIELD

#define PINMUX_DIO_PAD_ATTR_24_DRIVE_STRENGTH_24_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_24_DRIVE_STRENGTH_24_MASK, .index = PINMUX_DIO_PAD_ATTR_24_DRIVE_STRENGTH_24_OFFSET })

Definition at line 1475 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_24_DRIVE_STRENGTH_24_MASK

#define PINMUX_DIO_PAD_ATTR_24_DRIVE_STRENGTH_24_MASK 0xfu

Definition at line 1473 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_24_DRIVE_STRENGTH_24_OFFSET

#define PINMUX_DIO_PAD_ATTR_24_DRIVE_STRENGTH_24_OFFSET 20

Definition at line 1474 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_24_INPUT_DISABLE_24_BIT

#define PINMUX_DIO_PAD_ATTR_24_INPUT_DISABLE_24_BIT 7

Definition at line 1468 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_24_INVERT_24_BIT

#define PINMUX_DIO_PAD_ATTR_24_INVERT_24_BIT 0

Definition at line 1461 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_24_KEEPER_EN_24_BIT

#define PINMUX_DIO_PAD_ATTR_24_KEEPER_EN_24_BIT 4

Definition at line 1465 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_24_OD_EN_24_BIT

#define PINMUX_DIO_PAD_ATTR_24_OD_EN_24_BIT 6

Definition at line 1467 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_24_PULL_EN_24_BIT

#define PINMUX_DIO_PAD_ATTR_24_PULL_EN_24_BIT 2

Definition at line 1463 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_24_PULL_SELECT_24_BIT

#define PINMUX_DIO_PAD_ATTR_24_PULL_SELECT_24_BIT 3

Definition at line 1464 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_24_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_24_REG_OFFSET 0x268

Definition at line 1459 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_24_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_24_REG_RESVAL 0x0u

Definition at line 1460 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_24_SCHMITT_EN_24_BIT

#define PINMUX_DIO_PAD_ATTR_24_SCHMITT_EN_24_BIT 5

Definition at line 1466 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_24_SLEW_RATE_24_FIELD

#define PINMUX_DIO_PAD_ATTR_24_SLEW_RATE_24_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_24_SLEW_RATE_24_MASK, .index = PINMUX_DIO_PAD_ATTR_24_SLEW_RATE_24_OFFSET })

Definition at line 1471 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_24_SLEW_RATE_24_MASK

#define PINMUX_DIO_PAD_ATTR_24_SLEW_RATE_24_MASK 0x3u

Definition at line 1469 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_24_SLEW_RATE_24_OFFSET

#define PINMUX_DIO_PAD_ATTR_24_SLEW_RATE_24_OFFSET 16

Definition at line 1470 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_24_VIRTUAL_OD_EN_24_BIT

#define PINMUX_DIO_PAD_ATTR_24_VIRTUAL_OD_EN_24_BIT 1

Definition at line 1462 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_25_DRIVE_STRENGTH_25_FIELD

#define PINMUX_DIO_PAD_ATTR_25_DRIVE_STRENGTH_25_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_25_DRIVE_STRENGTH_25_MASK, .index = PINMUX_DIO_PAD_ATTR_25_DRIVE_STRENGTH_25_OFFSET })

Definition at line 1495 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_25_DRIVE_STRENGTH_25_MASK

#define PINMUX_DIO_PAD_ATTR_25_DRIVE_STRENGTH_25_MASK 0xfu

Definition at line 1493 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_25_DRIVE_STRENGTH_25_OFFSET

#define PINMUX_DIO_PAD_ATTR_25_DRIVE_STRENGTH_25_OFFSET 20

Definition at line 1494 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_25_INPUT_DISABLE_25_BIT

#define PINMUX_DIO_PAD_ATTR_25_INPUT_DISABLE_25_BIT 7

Definition at line 1488 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_25_INVERT_25_BIT

#define PINMUX_DIO_PAD_ATTR_25_INVERT_25_BIT 0

Definition at line 1481 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_25_KEEPER_EN_25_BIT

#define PINMUX_DIO_PAD_ATTR_25_KEEPER_EN_25_BIT 4

Definition at line 1485 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_25_OD_EN_25_BIT

#define PINMUX_DIO_PAD_ATTR_25_OD_EN_25_BIT 6

Definition at line 1487 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_25_PULL_EN_25_BIT

#define PINMUX_DIO_PAD_ATTR_25_PULL_EN_25_BIT 2

Definition at line 1483 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_25_PULL_SELECT_25_BIT

#define PINMUX_DIO_PAD_ATTR_25_PULL_SELECT_25_BIT 3

Definition at line 1484 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_25_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_25_REG_OFFSET 0x26c

Definition at line 1479 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_25_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_25_REG_RESVAL 0x0u

Definition at line 1480 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_25_SCHMITT_EN_25_BIT

#define PINMUX_DIO_PAD_ATTR_25_SCHMITT_EN_25_BIT 5

Definition at line 1486 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_25_SLEW_RATE_25_FIELD

#define PINMUX_DIO_PAD_ATTR_25_SLEW_RATE_25_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_25_SLEW_RATE_25_MASK, .index = PINMUX_DIO_PAD_ATTR_25_SLEW_RATE_25_OFFSET })

Definition at line 1491 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_25_SLEW_RATE_25_MASK

#define PINMUX_DIO_PAD_ATTR_25_SLEW_RATE_25_MASK 0x3u

Definition at line 1489 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_25_SLEW_RATE_25_OFFSET

#define PINMUX_DIO_PAD_ATTR_25_SLEW_RATE_25_OFFSET 16

Definition at line 1490 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_25_VIRTUAL_OD_EN_25_BIT

#define PINMUX_DIO_PAD_ATTR_25_VIRTUAL_OD_EN_25_BIT 1

Definition at line 1482 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_26_DRIVE_STRENGTH_26_FIELD

#define PINMUX_DIO_PAD_ATTR_26_DRIVE_STRENGTH_26_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_26_DRIVE_STRENGTH_26_MASK, .index = PINMUX_DIO_PAD_ATTR_26_DRIVE_STRENGTH_26_OFFSET })

Definition at line 1515 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_26_DRIVE_STRENGTH_26_MASK

#define PINMUX_DIO_PAD_ATTR_26_DRIVE_STRENGTH_26_MASK 0xfu

Definition at line 1513 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_26_DRIVE_STRENGTH_26_OFFSET

#define PINMUX_DIO_PAD_ATTR_26_DRIVE_STRENGTH_26_OFFSET 20

Definition at line 1514 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_26_INPUT_DISABLE_26_BIT

#define PINMUX_DIO_PAD_ATTR_26_INPUT_DISABLE_26_BIT 7

Definition at line 1508 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_26_INVERT_26_BIT

#define PINMUX_DIO_PAD_ATTR_26_INVERT_26_BIT 0

Definition at line 1501 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_26_KEEPER_EN_26_BIT

#define PINMUX_DIO_PAD_ATTR_26_KEEPER_EN_26_BIT 4

Definition at line 1505 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_26_OD_EN_26_BIT

#define PINMUX_DIO_PAD_ATTR_26_OD_EN_26_BIT 6

Definition at line 1507 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_26_PULL_EN_26_BIT

#define PINMUX_DIO_PAD_ATTR_26_PULL_EN_26_BIT 2

Definition at line 1503 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_26_PULL_SELECT_26_BIT

#define PINMUX_DIO_PAD_ATTR_26_PULL_SELECT_26_BIT 3

Definition at line 1504 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_26_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_26_REG_OFFSET 0x270

Definition at line 1499 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_26_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_26_REG_RESVAL 0x0u

Definition at line 1500 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_26_SCHMITT_EN_26_BIT

#define PINMUX_DIO_PAD_ATTR_26_SCHMITT_EN_26_BIT 5

Definition at line 1506 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_26_SLEW_RATE_26_FIELD

#define PINMUX_DIO_PAD_ATTR_26_SLEW_RATE_26_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_26_SLEW_RATE_26_MASK, .index = PINMUX_DIO_PAD_ATTR_26_SLEW_RATE_26_OFFSET })

Definition at line 1511 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_26_SLEW_RATE_26_MASK

#define PINMUX_DIO_PAD_ATTR_26_SLEW_RATE_26_MASK 0x3u

Definition at line 1509 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_26_SLEW_RATE_26_OFFSET

#define PINMUX_DIO_PAD_ATTR_26_SLEW_RATE_26_OFFSET 16

Definition at line 1510 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_26_VIRTUAL_OD_EN_26_BIT

#define PINMUX_DIO_PAD_ATTR_26_VIRTUAL_OD_EN_26_BIT 1

Definition at line 1502 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_27_DRIVE_STRENGTH_27_FIELD

#define PINMUX_DIO_PAD_ATTR_27_DRIVE_STRENGTH_27_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_27_DRIVE_STRENGTH_27_MASK, .index = PINMUX_DIO_PAD_ATTR_27_DRIVE_STRENGTH_27_OFFSET })

Definition at line 1535 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_27_DRIVE_STRENGTH_27_MASK

#define PINMUX_DIO_PAD_ATTR_27_DRIVE_STRENGTH_27_MASK 0xfu

Definition at line 1533 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_27_DRIVE_STRENGTH_27_OFFSET

#define PINMUX_DIO_PAD_ATTR_27_DRIVE_STRENGTH_27_OFFSET 20

Definition at line 1534 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_27_INPUT_DISABLE_27_BIT

#define PINMUX_DIO_PAD_ATTR_27_INPUT_DISABLE_27_BIT 7

Definition at line 1528 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_27_INVERT_27_BIT

#define PINMUX_DIO_PAD_ATTR_27_INVERT_27_BIT 0

Definition at line 1521 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_27_KEEPER_EN_27_BIT

#define PINMUX_DIO_PAD_ATTR_27_KEEPER_EN_27_BIT 4

Definition at line 1525 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_27_OD_EN_27_BIT

#define PINMUX_DIO_PAD_ATTR_27_OD_EN_27_BIT 6

Definition at line 1527 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_27_PULL_EN_27_BIT

#define PINMUX_DIO_PAD_ATTR_27_PULL_EN_27_BIT 2

Definition at line 1523 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_27_PULL_SELECT_27_BIT

#define PINMUX_DIO_PAD_ATTR_27_PULL_SELECT_27_BIT 3

Definition at line 1524 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_27_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_27_REG_OFFSET 0x274

Definition at line 1519 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_27_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_27_REG_RESVAL 0x0u

Definition at line 1520 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_27_SCHMITT_EN_27_BIT

#define PINMUX_DIO_PAD_ATTR_27_SCHMITT_EN_27_BIT 5

Definition at line 1526 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_27_SLEW_RATE_27_FIELD

#define PINMUX_DIO_PAD_ATTR_27_SLEW_RATE_27_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_27_SLEW_RATE_27_MASK, .index = PINMUX_DIO_PAD_ATTR_27_SLEW_RATE_27_OFFSET })

Definition at line 1531 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_27_SLEW_RATE_27_MASK

#define PINMUX_DIO_PAD_ATTR_27_SLEW_RATE_27_MASK 0x3u

Definition at line 1529 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_27_SLEW_RATE_27_OFFSET

#define PINMUX_DIO_PAD_ATTR_27_SLEW_RATE_27_OFFSET 16

Definition at line 1530 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_27_VIRTUAL_OD_EN_27_BIT

#define PINMUX_DIO_PAD_ATTR_27_VIRTUAL_OD_EN_27_BIT 1

Definition at line 1522 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_28_DRIVE_STRENGTH_28_FIELD

#define PINMUX_DIO_PAD_ATTR_28_DRIVE_STRENGTH_28_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_28_DRIVE_STRENGTH_28_MASK, .index = PINMUX_DIO_PAD_ATTR_28_DRIVE_STRENGTH_28_OFFSET })

Definition at line 1555 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_28_DRIVE_STRENGTH_28_MASK

#define PINMUX_DIO_PAD_ATTR_28_DRIVE_STRENGTH_28_MASK 0xfu

Definition at line 1553 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_28_DRIVE_STRENGTH_28_OFFSET

#define PINMUX_DIO_PAD_ATTR_28_DRIVE_STRENGTH_28_OFFSET 20

Definition at line 1554 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_28_INPUT_DISABLE_28_BIT

#define PINMUX_DIO_PAD_ATTR_28_INPUT_DISABLE_28_BIT 7

Definition at line 1548 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_28_INVERT_28_BIT

#define PINMUX_DIO_PAD_ATTR_28_INVERT_28_BIT 0

Definition at line 1541 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_28_KEEPER_EN_28_BIT

#define PINMUX_DIO_PAD_ATTR_28_KEEPER_EN_28_BIT 4

Definition at line 1545 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_28_OD_EN_28_BIT

#define PINMUX_DIO_PAD_ATTR_28_OD_EN_28_BIT 6

Definition at line 1547 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_28_PULL_EN_28_BIT

#define PINMUX_DIO_PAD_ATTR_28_PULL_EN_28_BIT 2

Definition at line 1543 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_28_PULL_SELECT_28_BIT

#define PINMUX_DIO_PAD_ATTR_28_PULL_SELECT_28_BIT 3

Definition at line 1544 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_28_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_28_REG_OFFSET 0x278

Definition at line 1539 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_28_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_28_REG_RESVAL 0x0u

Definition at line 1540 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_28_SCHMITT_EN_28_BIT

#define PINMUX_DIO_PAD_ATTR_28_SCHMITT_EN_28_BIT 5

Definition at line 1546 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_28_SLEW_RATE_28_FIELD

#define PINMUX_DIO_PAD_ATTR_28_SLEW_RATE_28_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_28_SLEW_RATE_28_MASK, .index = PINMUX_DIO_PAD_ATTR_28_SLEW_RATE_28_OFFSET })

Definition at line 1551 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_28_SLEW_RATE_28_MASK

#define PINMUX_DIO_PAD_ATTR_28_SLEW_RATE_28_MASK 0x3u

Definition at line 1549 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_28_SLEW_RATE_28_OFFSET

#define PINMUX_DIO_PAD_ATTR_28_SLEW_RATE_28_OFFSET 16

Definition at line 1550 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_28_VIRTUAL_OD_EN_28_BIT

#define PINMUX_DIO_PAD_ATTR_28_VIRTUAL_OD_EN_28_BIT 1

Definition at line 1542 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_29_DRIVE_STRENGTH_29_FIELD

#define PINMUX_DIO_PAD_ATTR_29_DRIVE_STRENGTH_29_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_29_DRIVE_STRENGTH_29_MASK, .index = PINMUX_DIO_PAD_ATTR_29_DRIVE_STRENGTH_29_OFFSET })

Definition at line 1575 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_29_DRIVE_STRENGTH_29_MASK

#define PINMUX_DIO_PAD_ATTR_29_DRIVE_STRENGTH_29_MASK 0xfu

Definition at line 1573 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_29_DRIVE_STRENGTH_29_OFFSET

#define PINMUX_DIO_PAD_ATTR_29_DRIVE_STRENGTH_29_OFFSET 20

Definition at line 1574 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_29_INPUT_DISABLE_29_BIT

#define PINMUX_DIO_PAD_ATTR_29_INPUT_DISABLE_29_BIT 7

Definition at line 1568 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_29_INVERT_29_BIT

#define PINMUX_DIO_PAD_ATTR_29_INVERT_29_BIT 0

Definition at line 1561 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_29_KEEPER_EN_29_BIT

#define PINMUX_DIO_PAD_ATTR_29_KEEPER_EN_29_BIT 4

Definition at line 1565 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_29_OD_EN_29_BIT

#define PINMUX_DIO_PAD_ATTR_29_OD_EN_29_BIT 6

Definition at line 1567 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_29_PULL_EN_29_BIT

#define PINMUX_DIO_PAD_ATTR_29_PULL_EN_29_BIT 2

Definition at line 1563 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_29_PULL_SELECT_29_BIT

#define PINMUX_DIO_PAD_ATTR_29_PULL_SELECT_29_BIT 3

Definition at line 1564 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_29_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_29_REG_OFFSET 0x27c

Definition at line 1559 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_29_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_29_REG_RESVAL 0x0u

Definition at line 1560 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_29_SCHMITT_EN_29_BIT

#define PINMUX_DIO_PAD_ATTR_29_SCHMITT_EN_29_BIT 5

Definition at line 1566 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_29_SLEW_RATE_29_FIELD

#define PINMUX_DIO_PAD_ATTR_29_SLEW_RATE_29_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_29_SLEW_RATE_29_MASK, .index = PINMUX_DIO_PAD_ATTR_29_SLEW_RATE_29_OFFSET })

Definition at line 1571 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_29_SLEW_RATE_29_MASK

#define PINMUX_DIO_PAD_ATTR_29_SLEW_RATE_29_MASK 0x3u

Definition at line 1569 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_29_SLEW_RATE_29_OFFSET

#define PINMUX_DIO_PAD_ATTR_29_SLEW_RATE_29_OFFSET 16

Definition at line 1570 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_29_VIRTUAL_OD_EN_29_BIT

#define PINMUX_DIO_PAD_ATTR_29_VIRTUAL_OD_EN_29_BIT 1

Definition at line 1562 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_FIELD

#define PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_MASK, .index = PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_OFFSET })

Definition at line 1035 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_MASK

#define PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_MASK 0xfu

Definition at line 1033 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_OFFSET

#define PINMUX_DIO_PAD_ATTR_2_DRIVE_STRENGTH_2_OFFSET 20

Definition at line 1034 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_2_INPUT_DISABLE_2_BIT

#define PINMUX_DIO_PAD_ATTR_2_INPUT_DISABLE_2_BIT 7

Definition at line 1028 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_2_INVERT_2_BIT

#define PINMUX_DIO_PAD_ATTR_2_INVERT_2_BIT 0

Definition at line 1021 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_2_KEEPER_EN_2_BIT

#define PINMUX_DIO_PAD_ATTR_2_KEEPER_EN_2_BIT 4

Definition at line 1025 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_2_OD_EN_2_BIT

#define PINMUX_DIO_PAD_ATTR_2_OD_EN_2_BIT 6

Definition at line 1027 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_2_PULL_EN_2_BIT

#define PINMUX_DIO_PAD_ATTR_2_PULL_EN_2_BIT 2

Definition at line 1023 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_2_PULL_SELECT_2_BIT

#define PINMUX_DIO_PAD_ATTR_2_PULL_SELECT_2_BIT 3

Definition at line 1024 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_2_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_2_REG_OFFSET 0x210

Definition at line 1019 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_2_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_2_REG_RESVAL 0x0u

Definition at line 1020 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_2_SCHMITT_EN_2_BIT

#define PINMUX_DIO_PAD_ATTR_2_SCHMITT_EN_2_BIT 5

Definition at line 1026 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_FIELD

#define PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_MASK, .index = PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_OFFSET })

Definition at line 1031 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_MASK

#define PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_MASK 0x3u

Definition at line 1029 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_OFFSET

#define PINMUX_DIO_PAD_ATTR_2_SLEW_RATE_2_OFFSET 16

Definition at line 1030 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_2_VIRTUAL_OD_EN_2_BIT

#define PINMUX_DIO_PAD_ATTR_2_VIRTUAL_OD_EN_2_BIT 1

Definition at line 1022 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_30_DRIVE_STRENGTH_30_FIELD

#define PINMUX_DIO_PAD_ATTR_30_DRIVE_STRENGTH_30_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_30_DRIVE_STRENGTH_30_MASK, .index = PINMUX_DIO_PAD_ATTR_30_DRIVE_STRENGTH_30_OFFSET })

Definition at line 1595 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_30_DRIVE_STRENGTH_30_MASK

#define PINMUX_DIO_PAD_ATTR_30_DRIVE_STRENGTH_30_MASK 0xfu

Definition at line 1593 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_30_DRIVE_STRENGTH_30_OFFSET

#define PINMUX_DIO_PAD_ATTR_30_DRIVE_STRENGTH_30_OFFSET 20

Definition at line 1594 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_30_INPUT_DISABLE_30_BIT

#define PINMUX_DIO_PAD_ATTR_30_INPUT_DISABLE_30_BIT 7

Definition at line 1588 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_30_INVERT_30_BIT

#define PINMUX_DIO_PAD_ATTR_30_INVERT_30_BIT 0

Definition at line 1581 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_30_KEEPER_EN_30_BIT

#define PINMUX_DIO_PAD_ATTR_30_KEEPER_EN_30_BIT 4

Definition at line 1585 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_30_OD_EN_30_BIT

#define PINMUX_DIO_PAD_ATTR_30_OD_EN_30_BIT 6

Definition at line 1587 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_30_PULL_EN_30_BIT

#define PINMUX_DIO_PAD_ATTR_30_PULL_EN_30_BIT 2

Definition at line 1583 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_30_PULL_SELECT_30_BIT

#define PINMUX_DIO_PAD_ATTR_30_PULL_SELECT_30_BIT 3

Definition at line 1584 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_30_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_30_REG_OFFSET 0x280

Definition at line 1579 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_30_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_30_REG_RESVAL 0x0u

Definition at line 1580 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_30_SCHMITT_EN_30_BIT

#define PINMUX_DIO_PAD_ATTR_30_SCHMITT_EN_30_BIT 5

Definition at line 1586 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_30_SLEW_RATE_30_FIELD

#define PINMUX_DIO_PAD_ATTR_30_SLEW_RATE_30_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_30_SLEW_RATE_30_MASK, .index = PINMUX_DIO_PAD_ATTR_30_SLEW_RATE_30_OFFSET })

Definition at line 1591 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_30_SLEW_RATE_30_MASK

#define PINMUX_DIO_PAD_ATTR_30_SLEW_RATE_30_MASK 0x3u

Definition at line 1589 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_30_SLEW_RATE_30_OFFSET

#define PINMUX_DIO_PAD_ATTR_30_SLEW_RATE_30_OFFSET 16

Definition at line 1590 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_30_VIRTUAL_OD_EN_30_BIT

#define PINMUX_DIO_PAD_ATTR_30_VIRTUAL_OD_EN_30_BIT 1

Definition at line 1582 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_31_DRIVE_STRENGTH_31_FIELD

#define PINMUX_DIO_PAD_ATTR_31_DRIVE_STRENGTH_31_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_31_DRIVE_STRENGTH_31_MASK, .index = PINMUX_DIO_PAD_ATTR_31_DRIVE_STRENGTH_31_OFFSET })

Definition at line 1615 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_31_DRIVE_STRENGTH_31_MASK

#define PINMUX_DIO_PAD_ATTR_31_DRIVE_STRENGTH_31_MASK 0xfu

Definition at line 1613 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_31_DRIVE_STRENGTH_31_OFFSET

#define PINMUX_DIO_PAD_ATTR_31_DRIVE_STRENGTH_31_OFFSET 20

Definition at line 1614 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_31_INPUT_DISABLE_31_BIT

#define PINMUX_DIO_PAD_ATTR_31_INPUT_DISABLE_31_BIT 7

Definition at line 1608 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_31_INVERT_31_BIT

#define PINMUX_DIO_PAD_ATTR_31_INVERT_31_BIT 0

Definition at line 1601 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_31_KEEPER_EN_31_BIT

#define PINMUX_DIO_PAD_ATTR_31_KEEPER_EN_31_BIT 4

Definition at line 1605 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_31_OD_EN_31_BIT

#define PINMUX_DIO_PAD_ATTR_31_OD_EN_31_BIT 6

Definition at line 1607 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_31_PULL_EN_31_BIT

#define PINMUX_DIO_PAD_ATTR_31_PULL_EN_31_BIT 2

Definition at line 1603 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_31_PULL_SELECT_31_BIT

#define PINMUX_DIO_PAD_ATTR_31_PULL_SELECT_31_BIT 3

Definition at line 1604 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_31_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_31_REG_OFFSET 0x284

Definition at line 1599 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_31_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_31_REG_RESVAL 0x0u

Definition at line 1600 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_31_SCHMITT_EN_31_BIT

#define PINMUX_DIO_PAD_ATTR_31_SCHMITT_EN_31_BIT 5

Definition at line 1606 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_31_SLEW_RATE_31_FIELD

#define PINMUX_DIO_PAD_ATTR_31_SLEW_RATE_31_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_31_SLEW_RATE_31_MASK, .index = PINMUX_DIO_PAD_ATTR_31_SLEW_RATE_31_OFFSET })

Definition at line 1611 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_31_SLEW_RATE_31_MASK

#define PINMUX_DIO_PAD_ATTR_31_SLEW_RATE_31_MASK 0x3u

Definition at line 1609 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_31_SLEW_RATE_31_OFFSET

#define PINMUX_DIO_PAD_ATTR_31_SLEW_RATE_31_OFFSET 16

Definition at line 1610 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_31_VIRTUAL_OD_EN_31_BIT

#define PINMUX_DIO_PAD_ATTR_31_VIRTUAL_OD_EN_31_BIT 1

Definition at line 1602 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_32_DRIVE_STRENGTH_32_FIELD

#define PINMUX_DIO_PAD_ATTR_32_DRIVE_STRENGTH_32_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_32_DRIVE_STRENGTH_32_MASK, .index = PINMUX_DIO_PAD_ATTR_32_DRIVE_STRENGTH_32_OFFSET })

Definition at line 1635 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_32_DRIVE_STRENGTH_32_MASK

#define PINMUX_DIO_PAD_ATTR_32_DRIVE_STRENGTH_32_MASK 0xfu

Definition at line 1633 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_32_DRIVE_STRENGTH_32_OFFSET

#define PINMUX_DIO_PAD_ATTR_32_DRIVE_STRENGTH_32_OFFSET 20

Definition at line 1634 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_32_INPUT_DISABLE_32_BIT

#define PINMUX_DIO_PAD_ATTR_32_INPUT_DISABLE_32_BIT 7

Definition at line 1628 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_32_INVERT_32_BIT

#define PINMUX_DIO_PAD_ATTR_32_INVERT_32_BIT 0

Definition at line 1621 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_32_KEEPER_EN_32_BIT

#define PINMUX_DIO_PAD_ATTR_32_KEEPER_EN_32_BIT 4

Definition at line 1625 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_32_OD_EN_32_BIT

#define PINMUX_DIO_PAD_ATTR_32_OD_EN_32_BIT 6

Definition at line 1627 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_32_PULL_EN_32_BIT

#define PINMUX_DIO_PAD_ATTR_32_PULL_EN_32_BIT 2

Definition at line 1623 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_32_PULL_SELECT_32_BIT

#define PINMUX_DIO_PAD_ATTR_32_PULL_SELECT_32_BIT 3

Definition at line 1624 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_32_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_32_REG_OFFSET 0x288

Definition at line 1619 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_32_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_32_REG_RESVAL 0x0u

Definition at line 1620 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_32_SCHMITT_EN_32_BIT

#define PINMUX_DIO_PAD_ATTR_32_SCHMITT_EN_32_BIT 5

Definition at line 1626 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_32_SLEW_RATE_32_FIELD

#define PINMUX_DIO_PAD_ATTR_32_SLEW_RATE_32_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_32_SLEW_RATE_32_MASK, .index = PINMUX_DIO_PAD_ATTR_32_SLEW_RATE_32_OFFSET })

Definition at line 1631 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_32_SLEW_RATE_32_MASK

#define PINMUX_DIO_PAD_ATTR_32_SLEW_RATE_32_MASK 0x3u

Definition at line 1629 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_32_SLEW_RATE_32_OFFSET

#define PINMUX_DIO_PAD_ATTR_32_SLEW_RATE_32_OFFSET 16

Definition at line 1630 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_32_VIRTUAL_OD_EN_32_BIT

#define PINMUX_DIO_PAD_ATTR_32_VIRTUAL_OD_EN_32_BIT 1

Definition at line 1622 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_33_DRIVE_STRENGTH_33_FIELD

#define PINMUX_DIO_PAD_ATTR_33_DRIVE_STRENGTH_33_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_33_DRIVE_STRENGTH_33_MASK, .index = PINMUX_DIO_PAD_ATTR_33_DRIVE_STRENGTH_33_OFFSET })

Definition at line 1655 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_33_DRIVE_STRENGTH_33_MASK

#define PINMUX_DIO_PAD_ATTR_33_DRIVE_STRENGTH_33_MASK 0xfu

Definition at line 1653 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_33_DRIVE_STRENGTH_33_OFFSET

#define PINMUX_DIO_PAD_ATTR_33_DRIVE_STRENGTH_33_OFFSET 20

Definition at line 1654 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_33_INPUT_DISABLE_33_BIT

#define PINMUX_DIO_PAD_ATTR_33_INPUT_DISABLE_33_BIT 7

Definition at line 1648 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_33_INVERT_33_BIT

#define PINMUX_DIO_PAD_ATTR_33_INVERT_33_BIT 0

Definition at line 1641 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_33_KEEPER_EN_33_BIT

#define PINMUX_DIO_PAD_ATTR_33_KEEPER_EN_33_BIT 4

Definition at line 1645 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_33_OD_EN_33_BIT

#define PINMUX_DIO_PAD_ATTR_33_OD_EN_33_BIT 6

Definition at line 1647 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_33_PULL_EN_33_BIT

#define PINMUX_DIO_PAD_ATTR_33_PULL_EN_33_BIT 2

Definition at line 1643 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_33_PULL_SELECT_33_BIT

#define PINMUX_DIO_PAD_ATTR_33_PULL_SELECT_33_BIT 3

Definition at line 1644 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_33_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_33_REG_OFFSET 0x28c

Definition at line 1639 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_33_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_33_REG_RESVAL 0x0u

Definition at line 1640 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_33_SCHMITT_EN_33_BIT

#define PINMUX_DIO_PAD_ATTR_33_SCHMITT_EN_33_BIT 5

Definition at line 1646 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_33_SLEW_RATE_33_FIELD

#define PINMUX_DIO_PAD_ATTR_33_SLEW_RATE_33_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_33_SLEW_RATE_33_MASK, .index = PINMUX_DIO_PAD_ATTR_33_SLEW_RATE_33_OFFSET })

Definition at line 1651 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_33_SLEW_RATE_33_MASK

#define PINMUX_DIO_PAD_ATTR_33_SLEW_RATE_33_MASK 0x3u

Definition at line 1649 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_33_SLEW_RATE_33_OFFSET

#define PINMUX_DIO_PAD_ATTR_33_SLEW_RATE_33_OFFSET 16

Definition at line 1650 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_33_VIRTUAL_OD_EN_33_BIT

#define PINMUX_DIO_PAD_ATTR_33_VIRTUAL_OD_EN_33_BIT 1

Definition at line 1642 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_34_DRIVE_STRENGTH_34_FIELD

#define PINMUX_DIO_PAD_ATTR_34_DRIVE_STRENGTH_34_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_34_DRIVE_STRENGTH_34_MASK, .index = PINMUX_DIO_PAD_ATTR_34_DRIVE_STRENGTH_34_OFFSET })

Definition at line 1675 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_34_DRIVE_STRENGTH_34_MASK

#define PINMUX_DIO_PAD_ATTR_34_DRIVE_STRENGTH_34_MASK 0xfu

Definition at line 1673 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_34_DRIVE_STRENGTH_34_OFFSET

#define PINMUX_DIO_PAD_ATTR_34_DRIVE_STRENGTH_34_OFFSET 20

Definition at line 1674 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_34_INPUT_DISABLE_34_BIT

#define PINMUX_DIO_PAD_ATTR_34_INPUT_DISABLE_34_BIT 7

Definition at line 1668 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_34_INVERT_34_BIT

#define PINMUX_DIO_PAD_ATTR_34_INVERT_34_BIT 0

Definition at line 1661 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_34_KEEPER_EN_34_BIT

#define PINMUX_DIO_PAD_ATTR_34_KEEPER_EN_34_BIT 4

Definition at line 1665 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_34_OD_EN_34_BIT

#define PINMUX_DIO_PAD_ATTR_34_OD_EN_34_BIT 6

Definition at line 1667 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_34_PULL_EN_34_BIT

#define PINMUX_DIO_PAD_ATTR_34_PULL_EN_34_BIT 2

Definition at line 1663 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_34_PULL_SELECT_34_BIT

#define PINMUX_DIO_PAD_ATTR_34_PULL_SELECT_34_BIT 3

Definition at line 1664 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_34_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_34_REG_OFFSET 0x290

Definition at line 1659 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_34_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_34_REG_RESVAL 0x0u

Definition at line 1660 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_34_SCHMITT_EN_34_BIT

#define PINMUX_DIO_PAD_ATTR_34_SCHMITT_EN_34_BIT 5

Definition at line 1666 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_34_SLEW_RATE_34_FIELD

#define PINMUX_DIO_PAD_ATTR_34_SLEW_RATE_34_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_34_SLEW_RATE_34_MASK, .index = PINMUX_DIO_PAD_ATTR_34_SLEW_RATE_34_OFFSET })

Definition at line 1671 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_34_SLEW_RATE_34_MASK

#define PINMUX_DIO_PAD_ATTR_34_SLEW_RATE_34_MASK 0x3u

Definition at line 1669 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_34_SLEW_RATE_34_OFFSET

#define PINMUX_DIO_PAD_ATTR_34_SLEW_RATE_34_OFFSET 16

Definition at line 1670 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_34_VIRTUAL_OD_EN_34_BIT

#define PINMUX_DIO_PAD_ATTR_34_VIRTUAL_OD_EN_34_BIT 1

Definition at line 1662 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_35_DRIVE_STRENGTH_35_FIELD

#define PINMUX_DIO_PAD_ATTR_35_DRIVE_STRENGTH_35_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_35_DRIVE_STRENGTH_35_MASK, .index = PINMUX_DIO_PAD_ATTR_35_DRIVE_STRENGTH_35_OFFSET })

Definition at line 1695 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_35_DRIVE_STRENGTH_35_MASK

#define PINMUX_DIO_PAD_ATTR_35_DRIVE_STRENGTH_35_MASK 0xfu

Definition at line 1693 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_35_DRIVE_STRENGTH_35_OFFSET

#define PINMUX_DIO_PAD_ATTR_35_DRIVE_STRENGTH_35_OFFSET 20

Definition at line 1694 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_35_INPUT_DISABLE_35_BIT

#define PINMUX_DIO_PAD_ATTR_35_INPUT_DISABLE_35_BIT 7

Definition at line 1688 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_35_INVERT_35_BIT

#define PINMUX_DIO_PAD_ATTR_35_INVERT_35_BIT 0

Definition at line 1681 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_35_KEEPER_EN_35_BIT

#define PINMUX_DIO_PAD_ATTR_35_KEEPER_EN_35_BIT 4

Definition at line 1685 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_35_OD_EN_35_BIT

#define PINMUX_DIO_PAD_ATTR_35_OD_EN_35_BIT 6

Definition at line 1687 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_35_PULL_EN_35_BIT

#define PINMUX_DIO_PAD_ATTR_35_PULL_EN_35_BIT 2

Definition at line 1683 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_35_PULL_SELECT_35_BIT

#define PINMUX_DIO_PAD_ATTR_35_PULL_SELECT_35_BIT 3

Definition at line 1684 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_35_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_35_REG_OFFSET 0x294

Definition at line 1679 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_35_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_35_REG_RESVAL 0x0u

Definition at line 1680 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_35_SCHMITT_EN_35_BIT

#define PINMUX_DIO_PAD_ATTR_35_SCHMITT_EN_35_BIT 5

Definition at line 1686 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_35_SLEW_RATE_35_FIELD

#define PINMUX_DIO_PAD_ATTR_35_SLEW_RATE_35_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_35_SLEW_RATE_35_MASK, .index = PINMUX_DIO_PAD_ATTR_35_SLEW_RATE_35_OFFSET })

Definition at line 1691 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_35_SLEW_RATE_35_MASK

#define PINMUX_DIO_PAD_ATTR_35_SLEW_RATE_35_MASK 0x3u

Definition at line 1689 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_35_SLEW_RATE_35_OFFSET

#define PINMUX_DIO_PAD_ATTR_35_SLEW_RATE_35_OFFSET 16

Definition at line 1690 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_35_VIRTUAL_OD_EN_35_BIT

#define PINMUX_DIO_PAD_ATTR_35_VIRTUAL_OD_EN_35_BIT 1

Definition at line 1682 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_36_DRIVE_STRENGTH_36_FIELD

#define PINMUX_DIO_PAD_ATTR_36_DRIVE_STRENGTH_36_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_36_DRIVE_STRENGTH_36_MASK, .index = PINMUX_DIO_PAD_ATTR_36_DRIVE_STRENGTH_36_OFFSET })

Definition at line 1715 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_36_DRIVE_STRENGTH_36_MASK

#define PINMUX_DIO_PAD_ATTR_36_DRIVE_STRENGTH_36_MASK 0xfu

Definition at line 1713 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_36_DRIVE_STRENGTH_36_OFFSET

#define PINMUX_DIO_PAD_ATTR_36_DRIVE_STRENGTH_36_OFFSET 20

Definition at line 1714 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_36_INPUT_DISABLE_36_BIT

#define PINMUX_DIO_PAD_ATTR_36_INPUT_DISABLE_36_BIT 7

Definition at line 1708 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_36_INVERT_36_BIT

#define PINMUX_DIO_PAD_ATTR_36_INVERT_36_BIT 0

Definition at line 1701 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_36_KEEPER_EN_36_BIT

#define PINMUX_DIO_PAD_ATTR_36_KEEPER_EN_36_BIT 4

Definition at line 1705 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_36_OD_EN_36_BIT

#define PINMUX_DIO_PAD_ATTR_36_OD_EN_36_BIT 6

Definition at line 1707 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_36_PULL_EN_36_BIT

#define PINMUX_DIO_PAD_ATTR_36_PULL_EN_36_BIT 2

Definition at line 1703 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_36_PULL_SELECT_36_BIT

#define PINMUX_DIO_PAD_ATTR_36_PULL_SELECT_36_BIT 3

Definition at line 1704 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_36_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_36_REG_OFFSET 0x298

Definition at line 1699 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_36_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_36_REG_RESVAL 0x0u

Definition at line 1700 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_36_SCHMITT_EN_36_BIT

#define PINMUX_DIO_PAD_ATTR_36_SCHMITT_EN_36_BIT 5

Definition at line 1706 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_36_SLEW_RATE_36_FIELD

#define PINMUX_DIO_PAD_ATTR_36_SLEW_RATE_36_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_36_SLEW_RATE_36_MASK, .index = PINMUX_DIO_PAD_ATTR_36_SLEW_RATE_36_OFFSET })

Definition at line 1711 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_36_SLEW_RATE_36_MASK

#define PINMUX_DIO_PAD_ATTR_36_SLEW_RATE_36_MASK 0x3u

Definition at line 1709 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_36_SLEW_RATE_36_OFFSET

#define PINMUX_DIO_PAD_ATTR_36_SLEW_RATE_36_OFFSET 16

Definition at line 1710 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_36_VIRTUAL_OD_EN_36_BIT

#define PINMUX_DIO_PAD_ATTR_36_VIRTUAL_OD_EN_36_BIT 1

Definition at line 1702 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_37_DRIVE_STRENGTH_37_FIELD

#define PINMUX_DIO_PAD_ATTR_37_DRIVE_STRENGTH_37_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_37_DRIVE_STRENGTH_37_MASK, .index = PINMUX_DIO_PAD_ATTR_37_DRIVE_STRENGTH_37_OFFSET })

Definition at line 1735 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_37_DRIVE_STRENGTH_37_MASK

#define PINMUX_DIO_PAD_ATTR_37_DRIVE_STRENGTH_37_MASK 0xfu

Definition at line 1733 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_37_DRIVE_STRENGTH_37_OFFSET

#define PINMUX_DIO_PAD_ATTR_37_DRIVE_STRENGTH_37_OFFSET 20

Definition at line 1734 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_37_INPUT_DISABLE_37_BIT

#define PINMUX_DIO_PAD_ATTR_37_INPUT_DISABLE_37_BIT 7

Definition at line 1728 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_37_INVERT_37_BIT

#define PINMUX_DIO_PAD_ATTR_37_INVERT_37_BIT 0

Definition at line 1721 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_37_KEEPER_EN_37_BIT

#define PINMUX_DIO_PAD_ATTR_37_KEEPER_EN_37_BIT 4

Definition at line 1725 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_37_OD_EN_37_BIT

#define PINMUX_DIO_PAD_ATTR_37_OD_EN_37_BIT 6

Definition at line 1727 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_37_PULL_EN_37_BIT

#define PINMUX_DIO_PAD_ATTR_37_PULL_EN_37_BIT 2

Definition at line 1723 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_37_PULL_SELECT_37_BIT

#define PINMUX_DIO_PAD_ATTR_37_PULL_SELECT_37_BIT 3

Definition at line 1724 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_37_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_37_REG_OFFSET 0x29c

Definition at line 1719 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_37_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_37_REG_RESVAL 0x0u

Definition at line 1720 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_37_SCHMITT_EN_37_BIT

#define PINMUX_DIO_PAD_ATTR_37_SCHMITT_EN_37_BIT 5

Definition at line 1726 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_37_SLEW_RATE_37_FIELD

#define PINMUX_DIO_PAD_ATTR_37_SLEW_RATE_37_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_37_SLEW_RATE_37_MASK, .index = PINMUX_DIO_PAD_ATTR_37_SLEW_RATE_37_OFFSET })

Definition at line 1731 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_37_SLEW_RATE_37_MASK

#define PINMUX_DIO_PAD_ATTR_37_SLEW_RATE_37_MASK 0x3u

Definition at line 1729 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_37_SLEW_RATE_37_OFFSET

#define PINMUX_DIO_PAD_ATTR_37_SLEW_RATE_37_OFFSET 16

Definition at line 1730 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_37_VIRTUAL_OD_EN_37_BIT

#define PINMUX_DIO_PAD_ATTR_37_VIRTUAL_OD_EN_37_BIT 1

Definition at line 1722 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_38_DRIVE_STRENGTH_38_FIELD

#define PINMUX_DIO_PAD_ATTR_38_DRIVE_STRENGTH_38_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_38_DRIVE_STRENGTH_38_MASK, .index = PINMUX_DIO_PAD_ATTR_38_DRIVE_STRENGTH_38_OFFSET })

Definition at line 1755 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_38_DRIVE_STRENGTH_38_MASK

#define PINMUX_DIO_PAD_ATTR_38_DRIVE_STRENGTH_38_MASK 0xfu

Definition at line 1753 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_38_DRIVE_STRENGTH_38_OFFSET

#define PINMUX_DIO_PAD_ATTR_38_DRIVE_STRENGTH_38_OFFSET 20

Definition at line 1754 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_38_INPUT_DISABLE_38_BIT

#define PINMUX_DIO_PAD_ATTR_38_INPUT_DISABLE_38_BIT 7

Definition at line 1748 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_38_INVERT_38_BIT

#define PINMUX_DIO_PAD_ATTR_38_INVERT_38_BIT 0

Definition at line 1741 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_38_KEEPER_EN_38_BIT

#define PINMUX_DIO_PAD_ATTR_38_KEEPER_EN_38_BIT 4

Definition at line 1745 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_38_OD_EN_38_BIT

#define PINMUX_DIO_PAD_ATTR_38_OD_EN_38_BIT 6

Definition at line 1747 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_38_PULL_EN_38_BIT

#define PINMUX_DIO_PAD_ATTR_38_PULL_EN_38_BIT 2

Definition at line 1743 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_38_PULL_SELECT_38_BIT

#define PINMUX_DIO_PAD_ATTR_38_PULL_SELECT_38_BIT 3

Definition at line 1744 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_38_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_38_REG_OFFSET 0x2a0

Definition at line 1739 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_38_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_38_REG_RESVAL 0x0u

Definition at line 1740 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_38_SCHMITT_EN_38_BIT

#define PINMUX_DIO_PAD_ATTR_38_SCHMITT_EN_38_BIT 5

Definition at line 1746 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_38_SLEW_RATE_38_FIELD

#define PINMUX_DIO_PAD_ATTR_38_SLEW_RATE_38_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_38_SLEW_RATE_38_MASK, .index = PINMUX_DIO_PAD_ATTR_38_SLEW_RATE_38_OFFSET })

Definition at line 1751 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_38_SLEW_RATE_38_MASK

#define PINMUX_DIO_PAD_ATTR_38_SLEW_RATE_38_MASK 0x3u

Definition at line 1749 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_38_SLEW_RATE_38_OFFSET

#define PINMUX_DIO_PAD_ATTR_38_SLEW_RATE_38_OFFSET 16

Definition at line 1750 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_38_VIRTUAL_OD_EN_38_BIT

#define PINMUX_DIO_PAD_ATTR_38_VIRTUAL_OD_EN_38_BIT 1

Definition at line 1742 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_39_DRIVE_STRENGTH_39_FIELD

#define PINMUX_DIO_PAD_ATTR_39_DRIVE_STRENGTH_39_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_39_DRIVE_STRENGTH_39_MASK, .index = PINMUX_DIO_PAD_ATTR_39_DRIVE_STRENGTH_39_OFFSET })

Definition at line 1775 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_39_DRIVE_STRENGTH_39_MASK

#define PINMUX_DIO_PAD_ATTR_39_DRIVE_STRENGTH_39_MASK 0xfu

Definition at line 1773 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_39_DRIVE_STRENGTH_39_OFFSET

#define PINMUX_DIO_PAD_ATTR_39_DRIVE_STRENGTH_39_OFFSET 20

Definition at line 1774 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_39_INPUT_DISABLE_39_BIT

#define PINMUX_DIO_PAD_ATTR_39_INPUT_DISABLE_39_BIT 7

Definition at line 1768 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_39_INVERT_39_BIT

#define PINMUX_DIO_PAD_ATTR_39_INVERT_39_BIT 0

Definition at line 1761 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_39_KEEPER_EN_39_BIT

#define PINMUX_DIO_PAD_ATTR_39_KEEPER_EN_39_BIT 4

Definition at line 1765 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_39_OD_EN_39_BIT

#define PINMUX_DIO_PAD_ATTR_39_OD_EN_39_BIT 6

Definition at line 1767 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_39_PULL_EN_39_BIT

#define PINMUX_DIO_PAD_ATTR_39_PULL_EN_39_BIT 2

Definition at line 1763 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_39_PULL_SELECT_39_BIT

#define PINMUX_DIO_PAD_ATTR_39_PULL_SELECT_39_BIT 3

Definition at line 1764 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_39_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_39_REG_OFFSET 0x2a4

Definition at line 1759 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_39_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_39_REG_RESVAL 0x0u

Definition at line 1760 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_39_SCHMITT_EN_39_BIT

#define PINMUX_DIO_PAD_ATTR_39_SCHMITT_EN_39_BIT 5

Definition at line 1766 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_39_SLEW_RATE_39_FIELD

#define PINMUX_DIO_PAD_ATTR_39_SLEW_RATE_39_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_39_SLEW_RATE_39_MASK, .index = PINMUX_DIO_PAD_ATTR_39_SLEW_RATE_39_OFFSET })

Definition at line 1771 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_39_SLEW_RATE_39_MASK

#define PINMUX_DIO_PAD_ATTR_39_SLEW_RATE_39_MASK 0x3u

Definition at line 1769 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_39_SLEW_RATE_39_OFFSET

#define PINMUX_DIO_PAD_ATTR_39_SLEW_RATE_39_OFFSET 16

Definition at line 1770 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_39_VIRTUAL_OD_EN_39_BIT

#define PINMUX_DIO_PAD_ATTR_39_VIRTUAL_OD_EN_39_BIT 1

Definition at line 1762 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_FIELD

#define PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_MASK, .index = PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_OFFSET })

Definition at line 1055 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_MASK

#define PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_MASK 0xfu

Definition at line 1053 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_OFFSET

#define PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_OFFSET 20

Definition at line 1054 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_3_INPUT_DISABLE_3_BIT

#define PINMUX_DIO_PAD_ATTR_3_INPUT_DISABLE_3_BIT 7

Definition at line 1048 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_3_INVERT_3_BIT

#define PINMUX_DIO_PAD_ATTR_3_INVERT_3_BIT 0

Definition at line 1041 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_3_KEEPER_EN_3_BIT

#define PINMUX_DIO_PAD_ATTR_3_KEEPER_EN_3_BIT 4

Definition at line 1045 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_3_OD_EN_3_BIT

#define PINMUX_DIO_PAD_ATTR_3_OD_EN_3_BIT 6

Definition at line 1047 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_3_PULL_EN_3_BIT

#define PINMUX_DIO_PAD_ATTR_3_PULL_EN_3_BIT 2

Definition at line 1043 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_3_PULL_SELECT_3_BIT

#define PINMUX_DIO_PAD_ATTR_3_PULL_SELECT_3_BIT 3

Definition at line 1044 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_3_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_3_REG_OFFSET 0x214

Definition at line 1039 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_3_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_3_REG_RESVAL 0x0u

Definition at line 1040 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_3_SCHMITT_EN_3_BIT

#define PINMUX_DIO_PAD_ATTR_3_SCHMITT_EN_3_BIT 5

Definition at line 1046 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_FIELD

#define PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_MASK, .index = PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_OFFSET })

Definition at line 1051 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_MASK

#define PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_MASK 0x3u

Definition at line 1049 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_OFFSET

#define PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_OFFSET 16

Definition at line 1050 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_3_VIRTUAL_OD_EN_3_BIT

#define PINMUX_DIO_PAD_ATTR_3_VIRTUAL_OD_EN_3_BIT 1

Definition at line 1042 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_40_DRIVE_STRENGTH_40_FIELD

#define PINMUX_DIO_PAD_ATTR_40_DRIVE_STRENGTH_40_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_40_DRIVE_STRENGTH_40_MASK, .index = PINMUX_DIO_PAD_ATTR_40_DRIVE_STRENGTH_40_OFFSET })

Definition at line 1795 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_40_DRIVE_STRENGTH_40_MASK

#define PINMUX_DIO_PAD_ATTR_40_DRIVE_STRENGTH_40_MASK 0xfu

Definition at line 1793 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_40_DRIVE_STRENGTH_40_OFFSET

#define PINMUX_DIO_PAD_ATTR_40_DRIVE_STRENGTH_40_OFFSET 20

Definition at line 1794 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_40_INPUT_DISABLE_40_BIT

#define PINMUX_DIO_PAD_ATTR_40_INPUT_DISABLE_40_BIT 7

Definition at line 1788 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_40_INVERT_40_BIT

#define PINMUX_DIO_PAD_ATTR_40_INVERT_40_BIT 0

Definition at line 1781 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_40_KEEPER_EN_40_BIT

#define PINMUX_DIO_PAD_ATTR_40_KEEPER_EN_40_BIT 4

Definition at line 1785 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_40_OD_EN_40_BIT

#define PINMUX_DIO_PAD_ATTR_40_OD_EN_40_BIT 6

Definition at line 1787 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_40_PULL_EN_40_BIT

#define PINMUX_DIO_PAD_ATTR_40_PULL_EN_40_BIT 2

Definition at line 1783 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_40_PULL_SELECT_40_BIT

#define PINMUX_DIO_PAD_ATTR_40_PULL_SELECT_40_BIT 3

Definition at line 1784 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_40_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_40_REG_OFFSET 0x2a8

Definition at line 1779 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_40_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_40_REG_RESVAL 0x0u

Definition at line 1780 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_40_SCHMITT_EN_40_BIT

#define PINMUX_DIO_PAD_ATTR_40_SCHMITT_EN_40_BIT 5

Definition at line 1786 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_40_SLEW_RATE_40_FIELD

#define PINMUX_DIO_PAD_ATTR_40_SLEW_RATE_40_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_40_SLEW_RATE_40_MASK, .index = PINMUX_DIO_PAD_ATTR_40_SLEW_RATE_40_OFFSET })

Definition at line 1791 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_40_SLEW_RATE_40_MASK

#define PINMUX_DIO_PAD_ATTR_40_SLEW_RATE_40_MASK 0x3u

Definition at line 1789 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_40_SLEW_RATE_40_OFFSET

#define PINMUX_DIO_PAD_ATTR_40_SLEW_RATE_40_OFFSET 16

Definition at line 1790 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_40_VIRTUAL_OD_EN_40_BIT

#define PINMUX_DIO_PAD_ATTR_40_VIRTUAL_OD_EN_40_BIT 1

Definition at line 1782 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_41_DRIVE_STRENGTH_41_FIELD

#define PINMUX_DIO_PAD_ATTR_41_DRIVE_STRENGTH_41_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_41_DRIVE_STRENGTH_41_MASK, .index = PINMUX_DIO_PAD_ATTR_41_DRIVE_STRENGTH_41_OFFSET })

Definition at line 1815 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_41_DRIVE_STRENGTH_41_MASK

#define PINMUX_DIO_PAD_ATTR_41_DRIVE_STRENGTH_41_MASK 0xfu

Definition at line 1813 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_41_DRIVE_STRENGTH_41_OFFSET

#define PINMUX_DIO_PAD_ATTR_41_DRIVE_STRENGTH_41_OFFSET 20

Definition at line 1814 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_41_INPUT_DISABLE_41_BIT

#define PINMUX_DIO_PAD_ATTR_41_INPUT_DISABLE_41_BIT 7

Definition at line 1808 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_41_INVERT_41_BIT

#define PINMUX_DIO_PAD_ATTR_41_INVERT_41_BIT 0

Definition at line 1801 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_41_KEEPER_EN_41_BIT

#define PINMUX_DIO_PAD_ATTR_41_KEEPER_EN_41_BIT 4

Definition at line 1805 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_41_OD_EN_41_BIT

#define PINMUX_DIO_PAD_ATTR_41_OD_EN_41_BIT 6

Definition at line 1807 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_41_PULL_EN_41_BIT

#define PINMUX_DIO_PAD_ATTR_41_PULL_EN_41_BIT 2

Definition at line 1803 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_41_PULL_SELECT_41_BIT

#define PINMUX_DIO_PAD_ATTR_41_PULL_SELECT_41_BIT 3

Definition at line 1804 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_41_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_41_REG_OFFSET 0x2ac

Definition at line 1799 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_41_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_41_REG_RESVAL 0x0u

Definition at line 1800 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_41_SCHMITT_EN_41_BIT

#define PINMUX_DIO_PAD_ATTR_41_SCHMITT_EN_41_BIT 5

Definition at line 1806 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_41_SLEW_RATE_41_FIELD

#define PINMUX_DIO_PAD_ATTR_41_SLEW_RATE_41_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_41_SLEW_RATE_41_MASK, .index = PINMUX_DIO_PAD_ATTR_41_SLEW_RATE_41_OFFSET })

Definition at line 1811 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_41_SLEW_RATE_41_MASK

#define PINMUX_DIO_PAD_ATTR_41_SLEW_RATE_41_MASK 0x3u

Definition at line 1809 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_41_SLEW_RATE_41_OFFSET

#define PINMUX_DIO_PAD_ATTR_41_SLEW_RATE_41_OFFSET 16

Definition at line 1810 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_41_VIRTUAL_OD_EN_41_BIT

#define PINMUX_DIO_PAD_ATTR_41_VIRTUAL_OD_EN_41_BIT 1

Definition at line 1802 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_42_DRIVE_STRENGTH_42_FIELD

#define PINMUX_DIO_PAD_ATTR_42_DRIVE_STRENGTH_42_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_42_DRIVE_STRENGTH_42_MASK, .index = PINMUX_DIO_PAD_ATTR_42_DRIVE_STRENGTH_42_OFFSET })

Definition at line 1835 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_42_DRIVE_STRENGTH_42_MASK

#define PINMUX_DIO_PAD_ATTR_42_DRIVE_STRENGTH_42_MASK 0xfu

Definition at line 1833 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_42_DRIVE_STRENGTH_42_OFFSET

#define PINMUX_DIO_PAD_ATTR_42_DRIVE_STRENGTH_42_OFFSET 20

Definition at line 1834 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_42_INPUT_DISABLE_42_BIT

#define PINMUX_DIO_PAD_ATTR_42_INPUT_DISABLE_42_BIT 7

Definition at line 1828 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_42_INVERT_42_BIT

#define PINMUX_DIO_PAD_ATTR_42_INVERT_42_BIT 0

Definition at line 1821 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_42_KEEPER_EN_42_BIT

#define PINMUX_DIO_PAD_ATTR_42_KEEPER_EN_42_BIT 4

Definition at line 1825 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_42_OD_EN_42_BIT

#define PINMUX_DIO_PAD_ATTR_42_OD_EN_42_BIT 6

Definition at line 1827 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_42_PULL_EN_42_BIT

#define PINMUX_DIO_PAD_ATTR_42_PULL_EN_42_BIT 2

Definition at line 1823 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_42_PULL_SELECT_42_BIT

#define PINMUX_DIO_PAD_ATTR_42_PULL_SELECT_42_BIT 3

Definition at line 1824 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_42_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_42_REG_OFFSET 0x2b0

Definition at line 1819 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_42_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_42_REG_RESVAL 0x0u

Definition at line 1820 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_42_SCHMITT_EN_42_BIT

#define PINMUX_DIO_PAD_ATTR_42_SCHMITT_EN_42_BIT 5

Definition at line 1826 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_42_SLEW_RATE_42_FIELD

#define PINMUX_DIO_PAD_ATTR_42_SLEW_RATE_42_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_42_SLEW_RATE_42_MASK, .index = PINMUX_DIO_PAD_ATTR_42_SLEW_RATE_42_OFFSET })

Definition at line 1831 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_42_SLEW_RATE_42_MASK

#define PINMUX_DIO_PAD_ATTR_42_SLEW_RATE_42_MASK 0x3u

Definition at line 1829 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_42_SLEW_RATE_42_OFFSET

#define PINMUX_DIO_PAD_ATTR_42_SLEW_RATE_42_OFFSET 16

Definition at line 1830 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_42_VIRTUAL_OD_EN_42_BIT

#define PINMUX_DIO_PAD_ATTR_42_VIRTUAL_OD_EN_42_BIT 1

Definition at line 1822 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_43_DRIVE_STRENGTH_43_FIELD

#define PINMUX_DIO_PAD_ATTR_43_DRIVE_STRENGTH_43_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_43_DRIVE_STRENGTH_43_MASK, .index = PINMUX_DIO_PAD_ATTR_43_DRIVE_STRENGTH_43_OFFSET })

Definition at line 1855 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_43_DRIVE_STRENGTH_43_MASK

#define PINMUX_DIO_PAD_ATTR_43_DRIVE_STRENGTH_43_MASK 0xfu

Definition at line 1853 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_43_DRIVE_STRENGTH_43_OFFSET

#define PINMUX_DIO_PAD_ATTR_43_DRIVE_STRENGTH_43_OFFSET 20

Definition at line 1854 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_43_INPUT_DISABLE_43_BIT

#define PINMUX_DIO_PAD_ATTR_43_INPUT_DISABLE_43_BIT 7

Definition at line 1848 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_43_INVERT_43_BIT

#define PINMUX_DIO_PAD_ATTR_43_INVERT_43_BIT 0

Definition at line 1841 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_43_KEEPER_EN_43_BIT

#define PINMUX_DIO_PAD_ATTR_43_KEEPER_EN_43_BIT 4

Definition at line 1845 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_43_OD_EN_43_BIT

#define PINMUX_DIO_PAD_ATTR_43_OD_EN_43_BIT 6

Definition at line 1847 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_43_PULL_EN_43_BIT

#define PINMUX_DIO_PAD_ATTR_43_PULL_EN_43_BIT 2

Definition at line 1843 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_43_PULL_SELECT_43_BIT

#define PINMUX_DIO_PAD_ATTR_43_PULL_SELECT_43_BIT 3

Definition at line 1844 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_43_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_43_REG_OFFSET 0x2b4

Definition at line 1839 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_43_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_43_REG_RESVAL 0x0u

Definition at line 1840 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_43_SCHMITT_EN_43_BIT

#define PINMUX_DIO_PAD_ATTR_43_SCHMITT_EN_43_BIT 5

Definition at line 1846 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_43_SLEW_RATE_43_FIELD

#define PINMUX_DIO_PAD_ATTR_43_SLEW_RATE_43_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_43_SLEW_RATE_43_MASK, .index = PINMUX_DIO_PAD_ATTR_43_SLEW_RATE_43_OFFSET })

Definition at line 1851 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_43_SLEW_RATE_43_MASK

#define PINMUX_DIO_PAD_ATTR_43_SLEW_RATE_43_MASK 0x3u

Definition at line 1849 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_43_SLEW_RATE_43_OFFSET

#define PINMUX_DIO_PAD_ATTR_43_SLEW_RATE_43_OFFSET 16

Definition at line 1850 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_43_VIRTUAL_OD_EN_43_BIT

#define PINMUX_DIO_PAD_ATTR_43_VIRTUAL_OD_EN_43_BIT 1

Definition at line 1842 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_44_DRIVE_STRENGTH_44_FIELD

#define PINMUX_DIO_PAD_ATTR_44_DRIVE_STRENGTH_44_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_44_DRIVE_STRENGTH_44_MASK, .index = PINMUX_DIO_PAD_ATTR_44_DRIVE_STRENGTH_44_OFFSET })

Definition at line 1875 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_44_DRIVE_STRENGTH_44_MASK

#define PINMUX_DIO_PAD_ATTR_44_DRIVE_STRENGTH_44_MASK 0xfu

Definition at line 1873 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_44_DRIVE_STRENGTH_44_OFFSET

#define PINMUX_DIO_PAD_ATTR_44_DRIVE_STRENGTH_44_OFFSET 20

Definition at line 1874 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_44_INPUT_DISABLE_44_BIT

#define PINMUX_DIO_PAD_ATTR_44_INPUT_DISABLE_44_BIT 7

Definition at line 1868 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_44_INVERT_44_BIT

#define PINMUX_DIO_PAD_ATTR_44_INVERT_44_BIT 0

Definition at line 1861 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_44_KEEPER_EN_44_BIT

#define PINMUX_DIO_PAD_ATTR_44_KEEPER_EN_44_BIT 4

Definition at line 1865 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_44_OD_EN_44_BIT

#define PINMUX_DIO_PAD_ATTR_44_OD_EN_44_BIT 6

Definition at line 1867 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_44_PULL_EN_44_BIT

#define PINMUX_DIO_PAD_ATTR_44_PULL_EN_44_BIT 2

Definition at line 1863 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_44_PULL_SELECT_44_BIT

#define PINMUX_DIO_PAD_ATTR_44_PULL_SELECT_44_BIT 3

Definition at line 1864 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_44_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_44_REG_OFFSET 0x2b8

Definition at line 1859 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_44_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_44_REG_RESVAL 0x0u

Definition at line 1860 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_44_SCHMITT_EN_44_BIT

#define PINMUX_DIO_PAD_ATTR_44_SCHMITT_EN_44_BIT 5

Definition at line 1866 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_44_SLEW_RATE_44_FIELD

#define PINMUX_DIO_PAD_ATTR_44_SLEW_RATE_44_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_44_SLEW_RATE_44_MASK, .index = PINMUX_DIO_PAD_ATTR_44_SLEW_RATE_44_OFFSET })

Definition at line 1871 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_44_SLEW_RATE_44_MASK

#define PINMUX_DIO_PAD_ATTR_44_SLEW_RATE_44_MASK 0x3u

Definition at line 1869 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_44_SLEW_RATE_44_OFFSET

#define PINMUX_DIO_PAD_ATTR_44_SLEW_RATE_44_OFFSET 16

Definition at line 1870 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_44_VIRTUAL_OD_EN_44_BIT

#define PINMUX_DIO_PAD_ATTR_44_VIRTUAL_OD_EN_44_BIT 1

Definition at line 1862 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_45_DRIVE_STRENGTH_45_FIELD

#define PINMUX_DIO_PAD_ATTR_45_DRIVE_STRENGTH_45_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_45_DRIVE_STRENGTH_45_MASK, .index = PINMUX_DIO_PAD_ATTR_45_DRIVE_STRENGTH_45_OFFSET })

Definition at line 1895 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_45_DRIVE_STRENGTH_45_MASK

#define PINMUX_DIO_PAD_ATTR_45_DRIVE_STRENGTH_45_MASK 0xfu

Definition at line 1893 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_45_DRIVE_STRENGTH_45_OFFSET

#define PINMUX_DIO_PAD_ATTR_45_DRIVE_STRENGTH_45_OFFSET 20

Definition at line 1894 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_45_INPUT_DISABLE_45_BIT

#define PINMUX_DIO_PAD_ATTR_45_INPUT_DISABLE_45_BIT 7

Definition at line 1888 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_45_INVERT_45_BIT

#define PINMUX_DIO_PAD_ATTR_45_INVERT_45_BIT 0

Definition at line 1881 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_45_KEEPER_EN_45_BIT

#define PINMUX_DIO_PAD_ATTR_45_KEEPER_EN_45_BIT 4

Definition at line 1885 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_45_OD_EN_45_BIT

#define PINMUX_DIO_PAD_ATTR_45_OD_EN_45_BIT 6

Definition at line 1887 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_45_PULL_EN_45_BIT

#define PINMUX_DIO_PAD_ATTR_45_PULL_EN_45_BIT 2

Definition at line 1883 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_45_PULL_SELECT_45_BIT

#define PINMUX_DIO_PAD_ATTR_45_PULL_SELECT_45_BIT 3

Definition at line 1884 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_45_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_45_REG_OFFSET 0x2bc

Definition at line 1879 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_45_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_45_REG_RESVAL 0x0u

Definition at line 1880 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_45_SCHMITT_EN_45_BIT

#define PINMUX_DIO_PAD_ATTR_45_SCHMITT_EN_45_BIT 5

Definition at line 1886 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_45_SLEW_RATE_45_FIELD

#define PINMUX_DIO_PAD_ATTR_45_SLEW_RATE_45_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_45_SLEW_RATE_45_MASK, .index = PINMUX_DIO_PAD_ATTR_45_SLEW_RATE_45_OFFSET })

Definition at line 1891 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_45_SLEW_RATE_45_MASK

#define PINMUX_DIO_PAD_ATTR_45_SLEW_RATE_45_MASK 0x3u

Definition at line 1889 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_45_SLEW_RATE_45_OFFSET

#define PINMUX_DIO_PAD_ATTR_45_SLEW_RATE_45_OFFSET 16

Definition at line 1890 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_45_VIRTUAL_OD_EN_45_BIT

#define PINMUX_DIO_PAD_ATTR_45_VIRTUAL_OD_EN_45_BIT 1

Definition at line 1882 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_46_DRIVE_STRENGTH_46_FIELD

#define PINMUX_DIO_PAD_ATTR_46_DRIVE_STRENGTH_46_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_46_DRIVE_STRENGTH_46_MASK, .index = PINMUX_DIO_PAD_ATTR_46_DRIVE_STRENGTH_46_OFFSET })

Definition at line 1915 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_46_DRIVE_STRENGTH_46_MASK

#define PINMUX_DIO_PAD_ATTR_46_DRIVE_STRENGTH_46_MASK 0xfu

Definition at line 1913 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_46_DRIVE_STRENGTH_46_OFFSET

#define PINMUX_DIO_PAD_ATTR_46_DRIVE_STRENGTH_46_OFFSET 20

Definition at line 1914 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_46_INPUT_DISABLE_46_BIT

#define PINMUX_DIO_PAD_ATTR_46_INPUT_DISABLE_46_BIT 7

Definition at line 1908 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_46_INVERT_46_BIT

#define PINMUX_DIO_PAD_ATTR_46_INVERT_46_BIT 0

Definition at line 1901 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_46_KEEPER_EN_46_BIT

#define PINMUX_DIO_PAD_ATTR_46_KEEPER_EN_46_BIT 4

Definition at line 1905 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_46_OD_EN_46_BIT

#define PINMUX_DIO_PAD_ATTR_46_OD_EN_46_BIT 6

Definition at line 1907 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_46_PULL_EN_46_BIT

#define PINMUX_DIO_PAD_ATTR_46_PULL_EN_46_BIT 2

Definition at line 1903 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_46_PULL_SELECT_46_BIT

#define PINMUX_DIO_PAD_ATTR_46_PULL_SELECT_46_BIT 3

Definition at line 1904 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_46_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_46_REG_OFFSET 0x2c0

Definition at line 1899 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_46_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_46_REG_RESVAL 0x0u

Definition at line 1900 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_46_SCHMITT_EN_46_BIT

#define PINMUX_DIO_PAD_ATTR_46_SCHMITT_EN_46_BIT 5

Definition at line 1906 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_46_SLEW_RATE_46_FIELD

#define PINMUX_DIO_PAD_ATTR_46_SLEW_RATE_46_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_46_SLEW_RATE_46_MASK, .index = PINMUX_DIO_PAD_ATTR_46_SLEW_RATE_46_OFFSET })

Definition at line 1911 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_46_SLEW_RATE_46_MASK

#define PINMUX_DIO_PAD_ATTR_46_SLEW_RATE_46_MASK 0x3u

Definition at line 1909 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_46_SLEW_RATE_46_OFFSET

#define PINMUX_DIO_PAD_ATTR_46_SLEW_RATE_46_OFFSET 16

Definition at line 1910 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_46_VIRTUAL_OD_EN_46_BIT

#define PINMUX_DIO_PAD_ATTR_46_VIRTUAL_OD_EN_46_BIT 1

Definition at line 1902 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_47_DRIVE_STRENGTH_47_FIELD

#define PINMUX_DIO_PAD_ATTR_47_DRIVE_STRENGTH_47_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_47_DRIVE_STRENGTH_47_MASK, .index = PINMUX_DIO_PAD_ATTR_47_DRIVE_STRENGTH_47_OFFSET })

Definition at line 1935 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_47_DRIVE_STRENGTH_47_MASK

#define PINMUX_DIO_PAD_ATTR_47_DRIVE_STRENGTH_47_MASK 0xfu

Definition at line 1933 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_47_DRIVE_STRENGTH_47_OFFSET

#define PINMUX_DIO_PAD_ATTR_47_DRIVE_STRENGTH_47_OFFSET 20

Definition at line 1934 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_47_INPUT_DISABLE_47_BIT

#define PINMUX_DIO_PAD_ATTR_47_INPUT_DISABLE_47_BIT 7

Definition at line 1928 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_47_INVERT_47_BIT

#define PINMUX_DIO_PAD_ATTR_47_INVERT_47_BIT 0

Definition at line 1921 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_47_KEEPER_EN_47_BIT

#define PINMUX_DIO_PAD_ATTR_47_KEEPER_EN_47_BIT 4

Definition at line 1925 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_47_OD_EN_47_BIT

#define PINMUX_DIO_PAD_ATTR_47_OD_EN_47_BIT 6

Definition at line 1927 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_47_PULL_EN_47_BIT

#define PINMUX_DIO_PAD_ATTR_47_PULL_EN_47_BIT 2

Definition at line 1923 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_47_PULL_SELECT_47_BIT

#define PINMUX_DIO_PAD_ATTR_47_PULL_SELECT_47_BIT 3

Definition at line 1924 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_47_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_47_REG_OFFSET 0x2c4

Definition at line 1919 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_47_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_47_REG_RESVAL 0x0u

Definition at line 1920 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_47_SCHMITT_EN_47_BIT

#define PINMUX_DIO_PAD_ATTR_47_SCHMITT_EN_47_BIT 5

Definition at line 1926 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_47_SLEW_RATE_47_FIELD

#define PINMUX_DIO_PAD_ATTR_47_SLEW_RATE_47_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_47_SLEW_RATE_47_MASK, .index = PINMUX_DIO_PAD_ATTR_47_SLEW_RATE_47_OFFSET })

Definition at line 1931 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_47_SLEW_RATE_47_MASK

#define PINMUX_DIO_PAD_ATTR_47_SLEW_RATE_47_MASK 0x3u

Definition at line 1929 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_47_SLEW_RATE_47_OFFSET

#define PINMUX_DIO_PAD_ATTR_47_SLEW_RATE_47_OFFSET 16

Definition at line 1930 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_47_VIRTUAL_OD_EN_47_BIT

#define PINMUX_DIO_PAD_ATTR_47_VIRTUAL_OD_EN_47_BIT 1

Definition at line 1922 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_48_DRIVE_STRENGTH_48_FIELD

#define PINMUX_DIO_PAD_ATTR_48_DRIVE_STRENGTH_48_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_48_DRIVE_STRENGTH_48_MASK, .index = PINMUX_DIO_PAD_ATTR_48_DRIVE_STRENGTH_48_OFFSET })

Definition at line 1955 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_48_DRIVE_STRENGTH_48_MASK

#define PINMUX_DIO_PAD_ATTR_48_DRIVE_STRENGTH_48_MASK 0xfu

Definition at line 1953 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_48_DRIVE_STRENGTH_48_OFFSET

#define PINMUX_DIO_PAD_ATTR_48_DRIVE_STRENGTH_48_OFFSET 20

Definition at line 1954 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_48_INPUT_DISABLE_48_BIT

#define PINMUX_DIO_PAD_ATTR_48_INPUT_DISABLE_48_BIT 7

Definition at line 1948 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_48_INVERT_48_BIT

#define PINMUX_DIO_PAD_ATTR_48_INVERT_48_BIT 0

Definition at line 1941 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_48_KEEPER_EN_48_BIT

#define PINMUX_DIO_PAD_ATTR_48_KEEPER_EN_48_BIT 4

Definition at line 1945 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_48_OD_EN_48_BIT

#define PINMUX_DIO_PAD_ATTR_48_OD_EN_48_BIT 6

Definition at line 1947 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_48_PULL_EN_48_BIT

#define PINMUX_DIO_PAD_ATTR_48_PULL_EN_48_BIT 2

Definition at line 1943 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_48_PULL_SELECT_48_BIT

#define PINMUX_DIO_PAD_ATTR_48_PULL_SELECT_48_BIT 3

Definition at line 1944 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_48_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_48_REG_OFFSET 0x2c8

Definition at line 1939 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_48_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_48_REG_RESVAL 0x0u

Definition at line 1940 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_48_SCHMITT_EN_48_BIT

#define PINMUX_DIO_PAD_ATTR_48_SCHMITT_EN_48_BIT 5

Definition at line 1946 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_48_SLEW_RATE_48_FIELD

#define PINMUX_DIO_PAD_ATTR_48_SLEW_RATE_48_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_48_SLEW_RATE_48_MASK, .index = PINMUX_DIO_PAD_ATTR_48_SLEW_RATE_48_OFFSET })

Definition at line 1951 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_48_SLEW_RATE_48_MASK

#define PINMUX_DIO_PAD_ATTR_48_SLEW_RATE_48_MASK 0x3u

Definition at line 1949 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_48_SLEW_RATE_48_OFFSET

#define PINMUX_DIO_PAD_ATTR_48_SLEW_RATE_48_OFFSET 16

Definition at line 1950 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_48_VIRTUAL_OD_EN_48_BIT

#define PINMUX_DIO_PAD_ATTR_48_VIRTUAL_OD_EN_48_BIT 1

Definition at line 1942 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_49_DRIVE_STRENGTH_49_FIELD

#define PINMUX_DIO_PAD_ATTR_49_DRIVE_STRENGTH_49_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_49_DRIVE_STRENGTH_49_MASK, .index = PINMUX_DIO_PAD_ATTR_49_DRIVE_STRENGTH_49_OFFSET })

Definition at line 1975 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_49_DRIVE_STRENGTH_49_MASK

#define PINMUX_DIO_PAD_ATTR_49_DRIVE_STRENGTH_49_MASK 0xfu

Definition at line 1973 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_49_DRIVE_STRENGTH_49_OFFSET

#define PINMUX_DIO_PAD_ATTR_49_DRIVE_STRENGTH_49_OFFSET 20

Definition at line 1974 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_49_INPUT_DISABLE_49_BIT

#define PINMUX_DIO_PAD_ATTR_49_INPUT_DISABLE_49_BIT 7

Definition at line 1968 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_49_INVERT_49_BIT

#define PINMUX_DIO_PAD_ATTR_49_INVERT_49_BIT 0

Definition at line 1961 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_49_KEEPER_EN_49_BIT

#define PINMUX_DIO_PAD_ATTR_49_KEEPER_EN_49_BIT 4

Definition at line 1965 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_49_OD_EN_49_BIT

#define PINMUX_DIO_PAD_ATTR_49_OD_EN_49_BIT 6

Definition at line 1967 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_49_PULL_EN_49_BIT

#define PINMUX_DIO_PAD_ATTR_49_PULL_EN_49_BIT 2

Definition at line 1963 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_49_PULL_SELECT_49_BIT

#define PINMUX_DIO_PAD_ATTR_49_PULL_SELECT_49_BIT 3

Definition at line 1964 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_49_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_49_REG_OFFSET 0x2cc

Definition at line 1959 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_49_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_49_REG_RESVAL 0x0u

Definition at line 1960 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_49_SCHMITT_EN_49_BIT

#define PINMUX_DIO_PAD_ATTR_49_SCHMITT_EN_49_BIT 5

Definition at line 1966 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_49_SLEW_RATE_49_FIELD

#define PINMUX_DIO_PAD_ATTR_49_SLEW_RATE_49_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_49_SLEW_RATE_49_MASK, .index = PINMUX_DIO_PAD_ATTR_49_SLEW_RATE_49_OFFSET })

Definition at line 1971 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_49_SLEW_RATE_49_MASK

#define PINMUX_DIO_PAD_ATTR_49_SLEW_RATE_49_MASK 0x3u

Definition at line 1969 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_49_SLEW_RATE_49_OFFSET

#define PINMUX_DIO_PAD_ATTR_49_SLEW_RATE_49_OFFSET 16

Definition at line 1970 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_49_VIRTUAL_OD_EN_49_BIT

#define PINMUX_DIO_PAD_ATTR_49_VIRTUAL_OD_EN_49_BIT 1

Definition at line 1962 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_FIELD

#define PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_MASK, .index = PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_OFFSET })

Definition at line 1075 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_MASK

#define PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_MASK 0xfu

Definition at line 1073 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_OFFSET

#define PINMUX_DIO_PAD_ATTR_4_DRIVE_STRENGTH_4_OFFSET 20

Definition at line 1074 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_4_INPUT_DISABLE_4_BIT

#define PINMUX_DIO_PAD_ATTR_4_INPUT_DISABLE_4_BIT 7

Definition at line 1068 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_4_INVERT_4_BIT

#define PINMUX_DIO_PAD_ATTR_4_INVERT_4_BIT 0

Definition at line 1061 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_4_KEEPER_EN_4_BIT

#define PINMUX_DIO_PAD_ATTR_4_KEEPER_EN_4_BIT 4

Definition at line 1065 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_4_OD_EN_4_BIT

#define PINMUX_DIO_PAD_ATTR_4_OD_EN_4_BIT 6

Definition at line 1067 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_4_PULL_EN_4_BIT

#define PINMUX_DIO_PAD_ATTR_4_PULL_EN_4_BIT 2

Definition at line 1063 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_4_PULL_SELECT_4_BIT

#define PINMUX_DIO_PAD_ATTR_4_PULL_SELECT_4_BIT 3

Definition at line 1064 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_4_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_4_REG_OFFSET 0x218

Definition at line 1059 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_4_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_4_REG_RESVAL 0x0u

Definition at line 1060 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_4_SCHMITT_EN_4_BIT

#define PINMUX_DIO_PAD_ATTR_4_SCHMITT_EN_4_BIT 5

Definition at line 1066 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_FIELD

#define PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_MASK, .index = PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_OFFSET })

Definition at line 1071 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_MASK

#define PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_MASK 0x3u

Definition at line 1069 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_OFFSET

#define PINMUX_DIO_PAD_ATTR_4_SLEW_RATE_4_OFFSET 16

Definition at line 1070 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_4_VIRTUAL_OD_EN_4_BIT

#define PINMUX_DIO_PAD_ATTR_4_VIRTUAL_OD_EN_4_BIT 1

Definition at line 1062 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_50_DRIVE_STRENGTH_50_FIELD

#define PINMUX_DIO_PAD_ATTR_50_DRIVE_STRENGTH_50_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_50_DRIVE_STRENGTH_50_MASK, .index = PINMUX_DIO_PAD_ATTR_50_DRIVE_STRENGTH_50_OFFSET })

Definition at line 1995 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_50_DRIVE_STRENGTH_50_MASK

#define PINMUX_DIO_PAD_ATTR_50_DRIVE_STRENGTH_50_MASK 0xfu

Definition at line 1993 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_50_DRIVE_STRENGTH_50_OFFSET

#define PINMUX_DIO_PAD_ATTR_50_DRIVE_STRENGTH_50_OFFSET 20

Definition at line 1994 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_50_INPUT_DISABLE_50_BIT

#define PINMUX_DIO_PAD_ATTR_50_INPUT_DISABLE_50_BIT 7

Definition at line 1988 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_50_INVERT_50_BIT

#define PINMUX_DIO_PAD_ATTR_50_INVERT_50_BIT 0

Definition at line 1981 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_50_KEEPER_EN_50_BIT

#define PINMUX_DIO_PAD_ATTR_50_KEEPER_EN_50_BIT 4

Definition at line 1985 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_50_OD_EN_50_BIT

#define PINMUX_DIO_PAD_ATTR_50_OD_EN_50_BIT 6

Definition at line 1987 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_50_PULL_EN_50_BIT

#define PINMUX_DIO_PAD_ATTR_50_PULL_EN_50_BIT 2

Definition at line 1983 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_50_PULL_SELECT_50_BIT

#define PINMUX_DIO_PAD_ATTR_50_PULL_SELECT_50_BIT 3

Definition at line 1984 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_50_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_50_REG_OFFSET 0x2d0

Definition at line 1979 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_50_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_50_REG_RESVAL 0x0u

Definition at line 1980 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_50_SCHMITT_EN_50_BIT

#define PINMUX_DIO_PAD_ATTR_50_SCHMITT_EN_50_BIT 5

Definition at line 1986 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_50_SLEW_RATE_50_FIELD

#define PINMUX_DIO_PAD_ATTR_50_SLEW_RATE_50_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_50_SLEW_RATE_50_MASK, .index = PINMUX_DIO_PAD_ATTR_50_SLEW_RATE_50_OFFSET })

Definition at line 1991 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_50_SLEW_RATE_50_MASK

#define PINMUX_DIO_PAD_ATTR_50_SLEW_RATE_50_MASK 0x3u

Definition at line 1989 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_50_SLEW_RATE_50_OFFSET

#define PINMUX_DIO_PAD_ATTR_50_SLEW_RATE_50_OFFSET 16

Definition at line 1990 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_50_VIRTUAL_OD_EN_50_BIT

#define PINMUX_DIO_PAD_ATTR_50_VIRTUAL_OD_EN_50_BIT 1

Definition at line 1982 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_51_DRIVE_STRENGTH_51_FIELD

#define PINMUX_DIO_PAD_ATTR_51_DRIVE_STRENGTH_51_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_51_DRIVE_STRENGTH_51_MASK, .index = PINMUX_DIO_PAD_ATTR_51_DRIVE_STRENGTH_51_OFFSET })

Definition at line 2015 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_51_DRIVE_STRENGTH_51_MASK

#define PINMUX_DIO_PAD_ATTR_51_DRIVE_STRENGTH_51_MASK 0xfu

Definition at line 2013 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_51_DRIVE_STRENGTH_51_OFFSET

#define PINMUX_DIO_PAD_ATTR_51_DRIVE_STRENGTH_51_OFFSET 20

Definition at line 2014 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_51_INPUT_DISABLE_51_BIT

#define PINMUX_DIO_PAD_ATTR_51_INPUT_DISABLE_51_BIT 7

Definition at line 2008 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_51_INVERT_51_BIT

#define PINMUX_DIO_PAD_ATTR_51_INVERT_51_BIT 0

Definition at line 2001 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_51_KEEPER_EN_51_BIT

#define PINMUX_DIO_PAD_ATTR_51_KEEPER_EN_51_BIT 4

Definition at line 2005 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_51_OD_EN_51_BIT

#define PINMUX_DIO_PAD_ATTR_51_OD_EN_51_BIT 6

Definition at line 2007 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_51_PULL_EN_51_BIT

#define PINMUX_DIO_PAD_ATTR_51_PULL_EN_51_BIT 2

Definition at line 2003 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_51_PULL_SELECT_51_BIT

#define PINMUX_DIO_PAD_ATTR_51_PULL_SELECT_51_BIT 3

Definition at line 2004 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_51_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_51_REG_OFFSET 0x2d4

Definition at line 1999 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_51_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_51_REG_RESVAL 0x0u

Definition at line 2000 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_51_SCHMITT_EN_51_BIT

#define PINMUX_DIO_PAD_ATTR_51_SCHMITT_EN_51_BIT 5

Definition at line 2006 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_51_SLEW_RATE_51_FIELD

#define PINMUX_DIO_PAD_ATTR_51_SLEW_RATE_51_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_51_SLEW_RATE_51_MASK, .index = PINMUX_DIO_PAD_ATTR_51_SLEW_RATE_51_OFFSET })

Definition at line 2011 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_51_SLEW_RATE_51_MASK

#define PINMUX_DIO_PAD_ATTR_51_SLEW_RATE_51_MASK 0x3u

Definition at line 2009 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_51_SLEW_RATE_51_OFFSET

#define PINMUX_DIO_PAD_ATTR_51_SLEW_RATE_51_OFFSET 16

Definition at line 2010 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_51_VIRTUAL_OD_EN_51_BIT

#define PINMUX_DIO_PAD_ATTR_51_VIRTUAL_OD_EN_51_BIT 1

Definition at line 2002 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_52_DRIVE_STRENGTH_52_FIELD

#define PINMUX_DIO_PAD_ATTR_52_DRIVE_STRENGTH_52_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_52_DRIVE_STRENGTH_52_MASK, .index = PINMUX_DIO_PAD_ATTR_52_DRIVE_STRENGTH_52_OFFSET })

Definition at line 2035 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_52_DRIVE_STRENGTH_52_MASK

#define PINMUX_DIO_PAD_ATTR_52_DRIVE_STRENGTH_52_MASK 0xfu

Definition at line 2033 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_52_DRIVE_STRENGTH_52_OFFSET

#define PINMUX_DIO_PAD_ATTR_52_DRIVE_STRENGTH_52_OFFSET 20

Definition at line 2034 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_52_INPUT_DISABLE_52_BIT

#define PINMUX_DIO_PAD_ATTR_52_INPUT_DISABLE_52_BIT 7

Definition at line 2028 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_52_INVERT_52_BIT

#define PINMUX_DIO_PAD_ATTR_52_INVERT_52_BIT 0

Definition at line 2021 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_52_KEEPER_EN_52_BIT

#define PINMUX_DIO_PAD_ATTR_52_KEEPER_EN_52_BIT 4

Definition at line 2025 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_52_OD_EN_52_BIT

#define PINMUX_DIO_PAD_ATTR_52_OD_EN_52_BIT 6

Definition at line 2027 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_52_PULL_EN_52_BIT

#define PINMUX_DIO_PAD_ATTR_52_PULL_EN_52_BIT 2

Definition at line 2023 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_52_PULL_SELECT_52_BIT

#define PINMUX_DIO_PAD_ATTR_52_PULL_SELECT_52_BIT 3

Definition at line 2024 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_52_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_52_REG_OFFSET 0x2d8

Definition at line 2019 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_52_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_52_REG_RESVAL 0x0u

Definition at line 2020 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_52_SCHMITT_EN_52_BIT

#define PINMUX_DIO_PAD_ATTR_52_SCHMITT_EN_52_BIT 5

Definition at line 2026 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_52_SLEW_RATE_52_FIELD

#define PINMUX_DIO_PAD_ATTR_52_SLEW_RATE_52_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_52_SLEW_RATE_52_MASK, .index = PINMUX_DIO_PAD_ATTR_52_SLEW_RATE_52_OFFSET })

Definition at line 2031 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_52_SLEW_RATE_52_MASK

#define PINMUX_DIO_PAD_ATTR_52_SLEW_RATE_52_MASK 0x3u

Definition at line 2029 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_52_SLEW_RATE_52_OFFSET

#define PINMUX_DIO_PAD_ATTR_52_SLEW_RATE_52_OFFSET 16

Definition at line 2030 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_52_VIRTUAL_OD_EN_52_BIT

#define PINMUX_DIO_PAD_ATTR_52_VIRTUAL_OD_EN_52_BIT 1

Definition at line 2022 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_53_DRIVE_STRENGTH_53_FIELD

#define PINMUX_DIO_PAD_ATTR_53_DRIVE_STRENGTH_53_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_53_DRIVE_STRENGTH_53_MASK, .index = PINMUX_DIO_PAD_ATTR_53_DRIVE_STRENGTH_53_OFFSET })

Definition at line 2055 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_53_DRIVE_STRENGTH_53_MASK

#define PINMUX_DIO_PAD_ATTR_53_DRIVE_STRENGTH_53_MASK 0xfu

Definition at line 2053 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_53_DRIVE_STRENGTH_53_OFFSET

#define PINMUX_DIO_PAD_ATTR_53_DRIVE_STRENGTH_53_OFFSET 20

Definition at line 2054 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_53_INPUT_DISABLE_53_BIT

#define PINMUX_DIO_PAD_ATTR_53_INPUT_DISABLE_53_BIT 7

Definition at line 2048 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_53_INVERT_53_BIT

#define PINMUX_DIO_PAD_ATTR_53_INVERT_53_BIT 0

Definition at line 2041 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_53_KEEPER_EN_53_BIT

#define PINMUX_DIO_PAD_ATTR_53_KEEPER_EN_53_BIT 4

Definition at line 2045 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_53_OD_EN_53_BIT

#define PINMUX_DIO_PAD_ATTR_53_OD_EN_53_BIT 6

Definition at line 2047 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_53_PULL_EN_53_BIT

#define PINMUX_DIO_PAD_ATTR_53_PULL_EN_53_BIT 2

Definition at line 2043 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_53_PULL_SELECT_53_BIT

#define PINMUX_DIO_PAD_ATTR_53_PULL_SELECT_53_BIT 3

Definition at line 2044 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_53_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_53_REG_OFFSET 0x2dc

Definition at line 2039 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_53_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_53_REG_RESVAL 0x0u

Definition at line 2040 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_53_SCHMITT_EN_53_BIT

#define PINMUX_DIO_PAD_ATTR_53_SCHMITT_EN_53_BIT 5

Definition at line 2046 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_53_SLEW_RATE_53_FIELD

#define PINMUX_DIO_PAD_ATTR_53_SLEW_RATE_53_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_53_SLEW_RATE_53_MASK, .index = PINMUX_DIO_PAD_ATTR_53_SLEW_RATE_53_OFFSET })

Definition at line 2051 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_53_SLEW_RATE_53_MASK

#define PINMUX_DIO_PAD_ATTR_53_SLEW_RATE_53_MASK 0x3u

Definition at line 2049 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_53_SLEW_RATE_53_OFFSET

#define PINMUX_DIO_PAD_ATTR_53_SLEW_RATE_53_OFFSET 16

Definition at line 2050 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_53_VIRTUAL_OD_EN_53_BIT

#define PINMUX_DIO_PAD_ATTR_53_VIRTUAL_OD_EN_53_BIT 1

Definition at line 2042 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_54_DRIVE_STRENGTH_54_FIELD

#define PINMUX_DIO_PAD_ATTR_54_DRIVE_STRENGTH_54_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_54_DRIVE_STRENGTH_54_MASK, .index = PINMUX_DIO_PAD_ATTR_54_DRIVE_STRENGTH_54_OFFSET })

Definition at line 2075 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_54_DRIVE_STRENGTH_54_MASK

#define PINMUX_DIO_PAD_ATTR_54_DRIVE_STRENGTH_54_MASK 0xfu

Definition at line 2073 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_54_DRIVE_STRENGTH_54_OFFSET

#define PINMUX_DIO_PAD_ATTR_54_DRIVE_STRENGTH_54_OFFSET 20

Definition at line 2074 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_54_INPUT_DISABLE_54_BIT

#define PINMUX_DIO_PAD_ATTR_54_INPUT_DISABLE_54_BIT 7

Definition at line 2068 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_54_INVERT_54_BIT

#define PINMUX_DIO_PAD_ATTR_54_INVERT_54_BIT 0

Definition at line 2061 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_54_KEEPER_EN_54_BIT

#define PINMUX_DIO_PAD_ATTR_54_KEEPER_EN_54_BIT 4

Definition at line 2065 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_54_OD_EN_54_BIT

#define PINMUX_DIO_PAD_ATTR_54_OD_EN_54_BIT 6

Definition at line 2067 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_54_PULL_EN_54_BIT

#define PINMUX_DIO_PAD_ATTR_54_PULL_EN_54_BIT 2

Definition at line 2063 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_54_PULL_SELECT_54_BIT

#define PINMUX_DIO_PAD_ATTR_54_PULL_SELECT_54_BIT 3

Definition at line 2064 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_54_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_54_REG_OFFSET 0x2e0

Definition at line 2059 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_54_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_54_REG_RESVAL 0x0u

Definition at line 2060 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_54_SCHMITT_EN_54_BIT

#define PINMUX_DIO_PAD_ATTR_54_SCHMITT_EN_54_BIT 5

Definition at line 2066 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_54_SLEW_RATE_54_FIELD

#define PINMUX_DIO_PAD_ATTR_54_SLEW_RATE_54_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_54_SLEW_RATE_54_MASK, .index = PINMUX_DIO_PAD_ATTR_54_SLEW_RATE_54_OFFSET })

Definition at line 2071 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_54_SLEW_RATE_54_MASK

#define PINMUX_DIO_PAD_ATTR_54_SLEW_RATE_54_MASK 0x3u

Definition at line 2069 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_54_SLEW_RATE_54_OFFSET

#define PINMUX_DIO_PAD_ATTR_54_SLEW_RATE_54_OFFSET 16

Definition at line 2070 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_54_VIRTUAL_OD_EN_54_BIT

#define PINMUX_DIO_PAD_ATTR_54_VIRTUAL_OD_EN_54_BIT 1

Definition at line 2062 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_55_DRIVE_STRENGTH_55_FIELD

#define PINMUX_DIO_PAD_ATTR_55_DRIVE_STRENGTH_55_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_55_DRIVE_STRENGTH_55_MASK, .index = PINMUX_DIO_PAD_ATTR_55_DRIVE_STRENGTH_55_OFFSET })

Definition at line 2095 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_55_DRIVE_STRENGTH_55_MASK

#define PINMUX_DIO_PAD_ATTR_55_DRIVE_STRENGTH_55_MASK 0xfu

Definition at line 2093 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_55_DRIVE_STRENGTH_55_OFFSET

#define PINMUX_DIO_PAD_ATTR_55_DRIVE_STRENGTH_55_OFFSET 20

Definition at line 2094 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_55_INPUT_DISABLE_55_BIT

#define PINMUX_DIO_PAD_ATTR_55_INPUT_DISABLE_55_BIT 7

Definition at line 2088 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_55_INVERT_55_BIT

#define PINMUX_DIO_PAD_ATTR_55_INVERT_55_BIT 0

Definition at line 2081 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_55_KEEPER_EN_55_BIT

#define PINMUX_DIO_PAD_ATTR_55_KEEPER_EN_55_BIT 4

Definition at line 2085 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_55_OD_EN_55_BIT

#define PINMUX_DIO_PAD_ATTR_55_OD_EN_55_BIT 6

Definition at line 2087 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_55_PULL_EN_55_BIT

#define PINMUX_DIO_PAD_ATTR_55_PULL_EN_55_BIT 2

Definition at line 2083 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_55_PULL_SELECT_55_BIT

#define PINMUX_DIO_PAD_ATTR_55_PULL_SELECT_55_BIT 3

Definition at line 2084 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_55_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_55_REG_OFFSET 0x2e4

Definition at line 2079 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_55_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_55_REG_RESVAL 0x0u

Definition at line 2080 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_55_SCHMITT_EN_55_BIT

#define PINMUX_DIO_PAD_ATTR_55_SCHMITT_EN_55_BIT 5

Definition at line 2086 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_55_SLEW_RATE_55_FIELD

#define PINMUX_DIO_PAD_ATTR_55_SLEW_RATE_55_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_55_SLEW_RATE_55_MASK, .index = PINMUX_DIO_PAD_ATTR_55_SLEW_RATE_55_OFFSET })

Definition at line 2091 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_55_SLEW_RATE_55_MASK

#define PINMUX_DIO_PAD_ATTR_55_SLEW_RATE_55_MASK 0x3u

Definition at line 2089 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_55_SLEW_RATE_55_OFFSET

#define PINMUX_DIO_PAD_ATTR_55_SLEW_RATE_55_OFFSET 16

Definition at line 2090 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_55_VIRTUAL_OD_EN_55_BIT

#define PINMUX_DIO_PAD_ATTR_55_VIRTUAL_OD_EN_55_BIT 1

Definition at line 2082 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_56_DRIVE_STRENGTH_56_FIELD

#define PINMUX_DIO_PAD_ATTR_56_DRIVE_STRENGTH_56_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_56_DRIVE_STRENGTH_56_MASK, .index = PINMUX_DIO_PAD_ATTR_56_DRIVE_STRENGTH_56_OFFSET })

Definition at line 2115 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_56_DRIVE_STRENGTH_56_MASK

#define PINMUX_DIO_PAD_ATTR_56_DRIVE_STRENGTH_56_MASK 0xfu

Definition at line 2113 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_56_DRIVE_STRENGTH_56_OFFSET

#define PINMUX_DIO_PAD_ATTR_56_DRIVE_STRENGTH_56_OFFSET 20

Definition at line 2114 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_56_INPUT_DISABLE_56_BIT

#define PINMUX_DIO_PAD_ATTR_56_INPUT_DISABLE_56_BIT 7

Definition at line 2108 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_56_INVERT_56_BIT

#define PINMUX_DIO_PAD_ATTR_56_INVERT_56_BIT 0

Definition at line 2101 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_56_KEEPER_EN_56_BIT

#define PINMUX_DIO_PAD_ATTR_56_KEEPER_EN_56_BIT 4

Definition at line 2105 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_56_OD_EN_56_BIT

#define PINMUX_DIO_PAD_ATTR_56_OD_EN_56_BIT 6

Definition at line 2107 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_56_PULL_EN_56_BIT

#define PINMUX_DIO_PAD_ATTR_56_PULL_EN_56_BIT 2

Definition at line 2103 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_56_PULL_SELECT_56_BIT

#define PINMUX_DIO_PAD_ATTR_56_PULL_SELECT_56_BIT 3

Definition at line 2104 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_56_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_56_REG_OFFSET 0x2e8

Definition at line 2099 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_56_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_56_REG_RESVAL 0x0u

Definition at line 2100 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_56_SCHMITT_EN_56_BIT

#define PINMUX_DIO_PAD_ATTR_56_SCHMITT_EN_56_BIT 5

Definition at line 2106 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_56_SLEW_RATE_56_FIELD

#define PINMUX_DIO_PAD_ATTR_56_SLEW_RATE_56_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_56_SLEW_RATE_56_MASK, .index = PINMUX_DIO_PAD_ATTR_56_SLEW_RATE_56_OFFSET })

Definition at line 2111 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_56_SLEW_RATE_56_MASK

#define PINMUX_DIO_PAD_ATTR_56_SLEW_RATE_56_MASK 0x3u

Definition at line 2109 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_56_SLEW_RATE_56_OFFSET

#define PINMUX_DIO_PAD_ATTR_56_SLEW_RATE_56_OFFSET 16

Definition at line 2110 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_56_VIRTUAL_OD_EN_56_BIT

#define PINMUX_DIO_PAD_ATTR_56_VIRTUAL_OD_EN_56_BIT 1

Definition at line 2102 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_57_DRIVE_STRENGTH_57_FIELD

#define PINMUX_DIO_PAD_ATTR_57_DRIVE_STRENGTH_57_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_57_DRIVE_STRENGTH_57_MASK, .index = PINMUX_DIO_PAD_ATTR_57_DRIVE_STRENGTH_57_OFFSET })

Definition at line 2135 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_57_DRIVE_STRENGTH_57_MASK

#define PINMUX_DIO_PAD_ATTR_57_DRIVE_STRENGTH_57_MASK 0xfu

Definition at line 2133 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_57_DRIVE_STRENGTH_57_OFFSET

#define PINMUX_DIO_PAD_ATTR_57_DRIVE_STRENGTH_57_OFFSET 20

Definition at line 2134 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_57_INPUT_DISABLE_57_BIT

#define PINMUX_DIO_PAD_ATTR_57_INPUT_DISABLE_57_BIT 7

Definition at line 2128 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_57_INVERT_57_BIT

#define PINMUX_DIO_PAD_ATTR_57_INVERT_57_BIT 0

Definition at line 2121 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_57_KEEPER_EN_57_BIT

#define PINMUX_DIO_PAD_ATTR_57_KEEPER_EN_57_BIT 4

Definition at line 2125 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_57_OD_EN_57_BIT

#define PINMUX_DIO_PAD_ATTR_57_OD_EN_57_BIT 6

Definition at line 2127 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_57_PULL_EN_57_BIT

#define PINMUX_DIO_PAD_ATTR_57_PULL_EN_57_BIT 2

Definition at line 2123 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_57_PULL_SELECT_57_BIT

#define PINMUX_DIO_PAD_ATTR_57_PULL_SELECT_57_BIT 3

Definition at line 2124 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_57_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_57_REG_OFFSET 0x2ec

Definition at line 2119 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_57_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_57_REG_RESVAL 0x0u

Definition at line 2120 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_57_SCHMITT_EN_57_BIT

#define PINMUX_DIO_PAD_ATTR_57_SCHMITT_EN_57_BIT 5

Definition at line 2126 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_57_SLEW_RATE_57_FIELD

#define PINMUX_DIO_PAD_ATTR_57_SLEW_RATE_57_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_57_SLEW_RATE_57_MASK, .index = PINMUX_DIO_PAD_ATTR_57_SLEW_RATE_57_OFFSET })

Definition at line 2131 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_57_SLEW_RATE_57_MASK

#define PINMUX_DIO_PAD_ATTR_57_SLEW_RATE_57_MASK 0x3u

Definition at line 2129 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_57_SLEW_RATE_57_OFFSET

#define PINMUX_DIO_PAD_ATTR_57_SLEW_RATE_57_OFFSET 16

Definition at line 2130 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_57_VIRTUAL_OD_EN_57_BIT

#define PINMUX_DIO_PAD_ATTR_57_VIRTUAL_OD_EN_57_BIT 1

Definition at line 2122 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_58_DRIVE_STRENGTH_58_FIELD

#define PINMUX_DIO_PAD_ATTR_58_DRIVE_STRENGTH_58_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_58_DRIVE_STRENGTH_58_MASK, .index = PINMUX_DIO_PAD_ATTR_58_DRIVE_STRENGTH_58_OFFSET })

Definition at line 2155 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_58_DRIVE_STRENGTH_58_MASK

#define PINMUX_DIO_PAD_ATTR_58_DRIVE_STRENGTH_58_MASK 0xfu

Definition at line 2153 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_58_DRIVE_STRENGTH_58_OFFSET

#define PINMUX_DIO_PAD_ATTR_58_DRIVE_STRENGTH_58_OFFSET 20

Definition at line 2154 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_58_INPUT_DISABLE_58_BIT

#define PINMUX_DIO_PAD_ATTR_58_INPUT_DISABLE_58_BIT 7

Definition at line 2148 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_58_INVERT_58_BIT

#define PINMUX_DIO_PAD_ATTR_58_INVERT_58_BIT 0

Definition at line 2141 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_58_KEEPER_EN_58_BIT

#define PINMUX_DIO_PAD_ATTR_58_KEEPER_EN_58_BIT 4

Definition at line 2145 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_58_OD_EN_58_BIT

#define PINMUX_DIO_PAD_ATTR_58_OD_EN_58_BIT 6

Definition at line 2147 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_58_PULL_EN_58_BIT

#define PINMUX_DIO_PAD_ATTR_58_PULL_EN_58_BIT 2

Definition at line 2143 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_58_PULL_SELECT_58_BIT

#define PINMUX_DIO_PAD_ATTR_58_PULL_SELECT_58_BIT 3

Definition at line 2144 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_58_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_58_REG_OFFSET 0x2f0

Definition at line 2139 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_58_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_58_REG_RESVAL 0x0u

Definition at line 2140 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_58_SCHMITT_EN_58_BIT

#define PINMUX_DIO_PAD_ATTR_58_SCHMITT_EN_58_BIT 5

Definition at line 2146 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_58_SLEW_RATE_58_FIELD

#define PINMUX_DIO_PAD_ATTR_58_SLEW_RATE_58_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_58_SLEW_RATE_58_MASK, .index = PINMUX_DIO_PAD_ATTR_58_SLEW_RATE_58_OFFSET })

Definition at line 2151 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_58_SLEW_RATE_58_MASK

#define PINMUX_DIO_PAD_ATTR_58_SLEW_RATE_58_MASK 0x3u

Definition at line 2149 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_58_SLEW_RATE_58_OFFSET

#define PINMUX_DIO_PAD_ATTR_58_SLEW_RATE_58_OFFSET 16

Definition at line 2150 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_58_VIRTUAL_OD_EN_58_BIT

#define PINMUX_DIO_PAD_ATTR_58_VIRTUAL_OD_EN_58_BIT 1

Definition at line 2142 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_59_DRIVE_STRENGTH_59_FIELD

#define PINMUX_DIO_PAD_ATTR_59_DRIVE_STRENGTH_59_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_59_DRIVE_STRENGTH_59_MASK, .index = PINMUX_DIO_PAD_ATTR_59_DRIVE_STRENGTH_59_OFFSET })

Definition at line 2175 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_59_DRIVE_STRENGTH_59_MASK

#define PINMUX_DIO_PAD_ATTR_59_DRIVE_STRENGTH_59_MASK 0xfu

Definition at line 2173 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_59_DRIVE_STRENGTH_59_OFFSET

#define PINMUX_DIO_PAD_ATTR_59_DRIVE_STRENGTH_59_OFFSET 20

Definition at line 2174 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_59_INPUT_DISABLE_59_BIT

#define PINMUX_DIO_PAD_ATTR_59_INPUT_DISABLE_59_BIT 7

Definition at line 2168 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_59_INVERT_59_BIT

#define PINMUX_DIO_PAD_ATTR_59_INVERT_59_BIT 0

Definition at line 2161 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_59_KEEPER_EN_59_BIT

#define PINMUX_DIO_PAD_ATTR_59_KEEPER_EN_59_BIT 4

Definition at line 2165 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_59_OD_EN_59_BIT

#define PINMUX_DIO_PAD_ATTR_59_OD_EN_59_BIT 6

Definition at line 2167 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_59_PULL_EN_59_BIT

#define PINMUX_DIO_PAD_ATTR_59_PULL_EN_59_BIT 2

Definition at line 2163 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_59_PULL_SELECT_59_BIT

#define PINMUX_DIO_PAD_ATTR_59_PULL_SELECT_59_BIT 3

Definition at line 2164 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_59_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_59_REG_OFFSET 0x2f4

Definition at line 2159 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_59_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_59_REG_RESVAL 0x0u

Definition at line 2160 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_59_SCHMITT_EN_59_BIT

#define PINMUX_DIO_PAD_ATTR_59_SCHMITT_EN_59_BIT 5

Definition at line 2166 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_59_SLEW_RATE_59_FIELD

#define PINMUX_DIO_PAD_ATTR_59_SLEW_RATE_59_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_59_SLEW_RATE_59_MASK, .index = PINMUX_DIO_PAD_ATTR_59_SLEW_RATE_59_OFFSET })

Definition at line 2171 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_59_SLEW_RATE_59_MASK

#define PINMUX_DIO_PAD_ATTR_59_SLEW_RATE_59_MASK 0x3u

Definition at line 2169 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_59_SLEW_RATE_59_OFFSET

#define PINMUX_DIO_PAD_ATTR_59_SLEW_RATE_59_OFFSET 16

Definition at line 2170 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_59_VIRTUAL_OD_EN_59_BIT

#define PINMUX_DIO_PAD_ATTR_59_VIRTUAL_OD_EN_59_BIT 1

Definition at line 2162 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_FIELD

#define PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_MASK, .index = PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_OFFSET })

Definition at line 1095 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_MASK

#define PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_MASK 0xfu

Definition at line 1093 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_OFFSET

#define PINMUX_DIO_PAD_ATTR_5_DRIVE_STRENGTH_5_OFFSET 20

Definition at line 1094 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_5_INPUT_DISABLE_5_BIT

#define PINMUX_DIO_PAD_ATTR_5_INPUT_DISABLE_5_BIT 7

Definition at line 1088 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_5_INVERT_5_BIT

#define PINMUX_DIO_PAD_ATTR_5_INVERT_5_BIT 0

Definition at line 1081 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_5_KEEPER_EN_5_BIT

#define PINMUX_DIO_PAD_ATTR_5_KEEPER_EN_5_BIT 4

Definition at line 1085 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_5_OD_EN_5_BIT

#define PINMUX_DIO_PAD_ATTR_5_OD_EN_5_BIT 6

Definition at line 1087 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_5_PULL_EN_5_BIT

#define PINMUX_DIO_PAD_ATTR_5_PULL_EN_5_BIT 2

Definition at line 1083 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_5_PULL_SELECT_5_BIT

#define PINMUX_DIO_PAD_ATTR_5_PULL_SELECT_5_BIT 3

Definition at line 1084 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_5_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_5_REG_OFFSET 0x21c

Definition at line 1079 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_5_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_5_REG_RESVAL 0x0u

Definition at line 1080 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_5_SCHMITT_EN_5_BIT

#define PINMUX_DIO_PAD_ATTR_5_SCHMITT_EN_5_BIT 5

Definition at line 1086 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_FIELD

#define PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_MASK, .index = PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_OFFSET })

Definition at line 1091 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_MASK

#define PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_MASK 0x3u

Definition at line 1089 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_OFFSET

#define PINMUX_DIO_PAD_ATTR_5_SLEW_RATE_5_OFFSET 16

Definition at line 1090 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_5_VIRTUAL_OD_EN_5_BIT

#define PINMUX_DIO_PAD_ATTR_5_VIRTUAL_OD_EN_5_BIT 1

Definition at line 1082 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_60_DRIVE_STRENGTH_60_FIELD

#define PINMUX_DIO_PAD_ATTR_60_DRIVE_STRENGTH_60_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_60_DRIVE_STRENGTH_60_MASK, .index = PINMUX_DIO_PAD_ATTR_60_DRIVE_STRENGTH_60_OFFSET })

Definition at line 2195 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_60_DRIVE_STRENGTH_60_MASK

#define PINMUX_DIO_PAD_ATTR_60_DRIVE_STRENGTH_60_MASK 0xfu

Definition at line 2193 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_60_DRIVE_STRENGTH_60_OFFSET

#define PINMUX_DIO_PAD_ATTR_60_DRIVE_STRENGTH_60_OFFSET 20

Definition at line 2194 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_60_INPUT_DISABLE_60_BIT

#define PINMUX_DIO_PAD_ATTR_60_INPUT_DISABLE_60_BIT 7

Definition at line 2188 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_60_INVERT_60_BIT

#define PINMUX_DIO_PAD_ATTR_60_INVERT_60_BIT 0

Definition at line 2181 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_60_KEEPER_EN_60_BIT

#define PINMUX_DIO_PAD_ATTR_60_KEEPER_EN_60_BIT 4

Definition at line 2185 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_60_OD_EN_60_BIT

#define PINMUX_DIO_PAD_ATTR_60_OD_EN_60_BIT 6

Definition at line 2187 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_60_PULL_EN_60_BIT

#define PINMUX_DIO_PAD_ATTR_60_PULL_EN_60_BIT 2

Definition at line 2183 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_60_PULL_SELECT_60_BIT

#define PINMUX_DIO_PAD_ATTR_60_PULL_SELECT_60_BIT 3

Definition at line 2184 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_60_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_60_REG_OFFSET 0x2f8

Definition at line 2179 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_60_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_60_REG_RESVAL 0x0u

Definition at line 2180 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_60_SCHMITT_EN_60_BIT

#define PINMUX_DIO_PAD_ATTR_60_SCHMITT_EN_60_BIT 5

Definition at line 2186 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_60_SLEW_RATE_60_FIELD

#define PINMUX_DIO_PAD_ATTR_60_SLEW_RATE_60_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_60_SLEW_RATE_60_MASK, .index = PINMUX_DIO_PAD_ATTR_60_SLEW_RATE_60_OFFSET })

Definition at line 2191 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_60_SLEW_RATE_60_MASK

#define PINMUX_DIO_PAD_ATTR_60_SLEW_RATE_60_MASK 0x3u

Definition at line 2189 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_60_SLEW_RATE_60_OFFSET

#define PINMUX_DIO_PAD_ATTR_60_SLEW_RATE_60_OFFSET 16

Definition at line 2190 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_60_VIRTUAL_OD_EN_60_BIT

#define PINMUX_DIO_PAD_ATTR_60_VIRTUAL_OD_EN_60_BIT 1

Definition at line 2182 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_61_DRIVE_STRENGTH_61_FIELD

#define PINMUX_DIO_PAD_ATTR_61_DRIVE_STRENGTH_61_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_61_DRIVE_STRENGTH_61_MASK, .index = PINMUX_DIO_PAD_ATTR_61_DRIVE_STRENGTH_61_OFFSET })

Definition at line 2215 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_61_DRIVE_STRENGTH_61_MASK

#define PINMUX_DIO_PAD_ATTR_61_DRIVE_STRENGTH_61_MASK 0xfu

Definition at line 2213 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_61_DRIVE_STRENGTH_61_OFFSET

#define PINMUX_DIO_PAD_ATTR_61_DRIVE_STRENGTH_61_OFFSET 20

Definition at line 2214 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_61_INPUT_DISABLE_61_BIT

#define PINMUX_DIO_PAD_ATTR_61_INPUT_DISABLE_61_BIT 7

Definition at line 2208 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_61_INVERT_61_BIT

#define PINMUX_DIO_PAD_ATTR_61_INVERT_61_BIT 0

Definition at line 2201 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_61_KEEPER_EN_61_BIT

#define PINMUX_DIO_PAD_ATTR_61_KEEPER_EN_61_BIT 4

Definition at line 2205 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_61_OD_EN_61_BIT

#define PINMUX_DIO_PAD_ATTR_61_OD_EN_61_BIT 6

Definition at line 2207 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_61_PULL_EN_61_BIT

#define PINMUX_DIO_PAD_ATTR_61_PULL_EN_61_BIT 2

Definition at line 2203 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_61_PULL_SELECT_61_BIT

#define PINMUX_DIO_PAD_ATTR_61_PULL_SELECT_61_BIT 3

Definition at line 2204 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_61_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_61_REG_OFFSET 0x2fc

Definition at line 2199 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_61_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_61_REG_RESVAL 0x0u

Definition at line 2200 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_61_SCHMITT_EN_61_BIT

#define PINMUX_DIO_PAD_ATTR_61_SCHMITT_EN_61_BIT 5

Definition at line 2206 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_61_SLEW_RATE_61_FIELD

#define PINMUX_DIO_PAD_ATTR_61_SLEW_RATE_61_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_61_SLEW_RATE_61_MASK, .index = PINMUX_DIO_PAD_ATTR_61_SLEW_RATE_61_OFFSET })

Definition at line 2211 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_61_SLEW_RATE_61_MASK

#define PINMUX_DIO_PAD_ATTR_61_SLEW_RATE_61_MASK 0x3u

Definition at line 2209 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_61_SLEW_RATE_61_OFFSET

#define PINMUX_DIO_PAD_ATTR_61_SLEW_RATE_61_OFFSET 16

Definition at line 2210 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_61_VIRTUAL_OD_EN_61_BIT

#define PINMUX_DIO_PAD_ATTR_61_VIRTUAL_OD_EN_61_BIT 1

Definition at line 2202 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_62_DRIVE_STRENGTH_62_FIELD

#define PINMUX_DIO_PAD_ATTR_62_DRIVE_STRENGTH_62_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_62_DRIVE_STRENGTH_62_MASK, .index = PINMUX_DIO_PAD_ATTR_62_DRIVE_STRENGTH_62_OFFSET })

Definition at line 2235 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_62_DRIVE_STRENGTH_62_MASK

#define PINMUX_DIO_PAD_ATTR_62_DRIVE_STRENGTH_62_MASK 0xfu

Definition at line 2233 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_62_DRIVE_STRENGTH_62_OFFSET

#define PINMUX_DIO_PAD_ATTR_62_DRIVE_STRENGTH_62_OFFSET 20

Definition at line 2234 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_62_INPUT_DISABLE_62_BIT

#define PINMUX_DIO_PAD_ATTR_62_INPUT_DISABLE_62_BIT 7

Definition at line 2228 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_62_INVERT_62_BIT

#define PINMUX_DIO_PAD_ATTR_62_INVERT_62_BIT 0

Definition at line 2221 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_62_KEEPER_EN_62_BIT

#define PINMUX_DIO_PAD_ATTR_62_KEEPER_EN_62_BIT 4

Definition at line 2225 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_62_OD_EN_62_BIT

#define PINMUX_DIO_PAD_ATTR_62_OD_EN_62_BIT 6

Definition at line 2227 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_62_PULL_EN_62_BIT

#define PINMUX_DIO_PAD_ATTR_62_PULL_EN_62_BIT 2

Definition at line 2223 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_62_PULL_SELECT_62_BIT

#define PINMUX_DIO_PAD_ATTR_62_PULL_SELECT_62_BIT 3

Definition at line 2224 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_62_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_62_REG_OFFSET 0x300

Definition at line 2219 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_62_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_62_REG_RESVAL 0x0u

Definition at line 2220 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_62_SCHMITT_EN_62_BIT

#define PINMUX_DIO_PAD_ATTR_62_SCHMITT_EN_62_BIT 5

Definition at line 2226 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_62_SLEW_RATE_62_FIELD

#define PINMUX_DIO_PAD_ATTR_62_SLEW_RATE_62_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_62_SLEW_RATE_62_MASK, .index = PINMUX_DIO_PAD_ATTR_62_SLEW_RATE_62_OFFSET })

Definition at line 2231 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_62_SLEW_RATE_62_MASK

#define PINMUX_DIO_PAD_ATTR_62_SLEW_RATE_62_MASK 0x3u

Definition at line 2229 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_62_SLEW_RATE_62_OFFSET

#define PINMUX_DIO_PAD_ATTR_62_SLEW_RATE_62_OFFSET 16

Definition at line 2230 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_62_VIRTUAL_OD_EN_62_BIT

#define PINMUX_DIO_PAD_ATTR_62_VIRTUAL_OD_EN_62_BIT 1

Definition at line 2222 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_63_DRIVE_STRENGTH_63_FIELD

#define PINMUX_DIO_PAD_ATTR_63_DRIVE_STRENGTH_63_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_63_DRIVE_STRENGTH_63_MASK, .index = PINMUX_DIO_PAD_ATTR_63_DRIVE_STRENGTH_63_OFFSET })

Definition at line 2255 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_63_DRIVE_STRENGTH_63_MASK

#define PINMUX_DIO_PAD_ATTR_63_DRIVE_STRENGTH_63_MASK 0xfu

Definition at line 2253 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_63_DRIVE_STRENGTH_63_OFFSET

#define PINMUX_DIO_PAD_ATTR_63_DRIVE_STRENGTH_63_OFFSET 20

Definition at line 2254 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_63_INPUT_DISABLE_63_BIT

#define PINMUX_DIO_PAD_ATTR_63_INPUT_DISABLE_63_BIT 7

Definition at line 2248 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_63_INVERT_63_BIT

#define PINMUX_DIO_PAD_ATTR_63_INVERT_63_BIT 0

Definition at line 2241 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_63_KEEPER_EN_63_BIT

#define PINMUX_DIO_PAD_ATTR_63_KEEPER_EN_63_BIT 4

Definition at line 2245 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_63_OD_EN_63_BIT

#define PINMUX_DIO_PAD_ATTR_63_OD_EN_63_BIT 6

Definition at line 2247 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_63_PULL_EN_63_BIT

#define PINMUX_DIO_PAD_ATTR_63_PULL_EN_63_BIT 2

Definition at line 2243 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_63_PULL_SELECT_63_BIT

#define PINMUX_DIO_PAD_ATTR_63_PULL_SELECT_63_BIT 3

Definition at line 2244 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_63_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_63_REG_OFFSET 0x304

Definition at line 2239 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_63_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_63_REG_RESVAL 0x0u

Definition at line 2240 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_63_SCHMITT_EN_63_BIT

#define PINMUX_DIO_PAD_ATTR_63_SCHMITT_EN_63_BIT 5

Definition at line 2246 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_63_SLEW_RATE_63_FIELD

#define PINMUX_DIO_PAD_ATTR_63_SLEW_RATE_63_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_63_SLEW_RATE_63_MASK, .index = PINMUX_DIO_PAD_ATTR_63_SLEW_RATE_63_OFFSET })

Definition at line 2251 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_63_SLEW_RATE_63_MASK

#define PINMUX_DIO_PAD_ATTR_63_SLEW_RATE_63_MASK 0x3u

Definition at line 2249 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_63_SLEW_RATE_63_OFFSET

#define PINMUX_DIO_PAD_ATTR_63_SLEW_RATE_63_OFFSET 16

Definition at line 2250 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_63_VIRTUAL_OD_EN_63_BIT

#define PINMUX_DIO_PAD_ATTR_63_VIRTUAL_OD_EN_63_BIT 1

Definition at line 2242 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_64_DRIVE_STRENGTH_64_FIELD

#define PINMUX_DIO_PAD_ATTR_64_DRIVE_STRENGTH_64_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_64_DRIVE_STRENGTH_64_MASK, .index = PINMUX_DIO_PAD_ATTR_64_DRIVE_STRENGTH_64_OFFSET })

Definition at line 2275 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_64_DRIVE_STRENGTH_64_MASK

#define PINMUX_DIO_PAD_ATTR_64_DRIVE_STRENGTH_64_MASK 0xfu

Definition at line 2273 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_64_DRIVE_STRENGTH_64_OFFSET

#define PINMUX_DIO_PAD_ATTR_64_DRIVE_STRENGTH_64_OFFSET 20

Definition at line 2274 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_64_INPUT_DISABLE_64_BIT

#define PINMUX_DIO_PAD_ATTR_64_INPUT_DISABLE_64_BIT 7

Definition at line 2268 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_64_INVERT_64_BIT

#define PINMUX_DIO_PAD_ATTR_64_INVERT_64_BIT 0

Definition at line 2261 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_64_KEEPER_EN_64_BIT

#define PINMUX_DIO_PAD_ATTR_64_KEEPER_EN_64_BIT 4

Definition at line 2265 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_64_OD_EN_64_BIT

#define PINMUX_DIO_PAD_ATTR_64_OD_EN_64_BIT 6

Definition at line 2267 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_64_PULL_EN_64_BIT

#define PINMUX_DIO_PAD_ATTR_64_PULL_EN_64_BIT 2

Definition at line 2263 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_64_PULL_SELECT_64_BIT

#define PINMUX_DIO_PAD_ATTR_64_PULL_SELECT_64_BIT 3

Definition at line 2264 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_64_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_64_REG_OFFSET 0x308

Definition at line 2259 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_64_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_64_REG_RESVAL 0x0u

Definition at line 2260 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_64_SCHMITT_EN_64_BIT

#define PINMUX_DIO_PAD_ATTR_64_SCHMITT_EN_64_BIT 5

Definition at line 2266 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_64_SLEW_RATE_64_FIELD

#define PINMUX_DIO_PAD_ATTR_64_SLEW_RATE_64_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_64_SLEW_RATE_64_MASK, .index = PINMUX_DIO_PAD_ATTR_64_SLEW_RATE_64_OFFSET })

Definition at line 2271 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_64_SLEW_RATE_64_MASK

#define PINMUX_DIO_PAD_ATTR_64_SLEW_RATE_64_MASK 0x3u

Definition at line 2269 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_64_SLEW_RATE_64_OFFSET

#define PINMUX_DIO_PAD_ATTR_64_SLEW_RATE_64_OFFSET 16

Definition at line 2270 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_64_VIRTUAL_OD_EN_64_BIT

#define PINMUX_DIO_PAD_ATTR_64_VIRTUAL_OD_EN_64_BIT 1

Definition at line 2262 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_65_DRIVE_STRENGTH_65_FIELD

#define PINMUX_DIO_PAD_ATTR_65_DRIVE_STRENGTH_65_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_65_DRIVE_STRENGTH_65_MASK, .index = PINMUX_DIO_PAD_ATTR_65_DRIVE_STRENGTH_65_OFFSET })

Definition at line 2295 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_65_DRIVE_STRENGTH_65_MASK

#define PINMUX_DIO_PAD_ATTR_65_DRIVE_STRENGTH_65_MASK 0xfu

Definition at line 2293 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_65_DRIVE_STRENGTH_65_OFFSET

#define PINMUX_DIO_PAD_ATTR_65_DRIVE_STRENGTH_65_OFFSET 20

Definition at line 2294 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_65_INPUT_DISABLE_65_BIT

#define PINMUX_DIO_PAD_ATTR_65_INPUT_DISABLE_65_BIT 7

Definition at line 2288 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_65_INVERT_65_BIT

#define PINMUX_DIO_PAD_ATTR_65_INVERT_65_BIT 0

Definition at line 2281 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_65_KEEPER_EN_65_BIT

#define PINMUX_DIO_PAD_ATTR_65_KEEPER_EN_65_BIT 4

Definition at line 2285 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_65_OD_EN_65_BIT

#define PINMUX_DIO_PAD_ATTR_65_OD_EN_65_BIT 6

Definition at line 2287 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_65_PULL_EN_65_BIT

#define PINMUX_DIO_PAD_ATTR_65_PULL_EN_65_BIT 2

Definition at line 2283 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_65_PULL_SELECT_65_BIT

#define PINMUX_DIO_PAD_ATTR_65_PULL_SELECT_65_BIT 3

Definition at line 2284 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_65_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_65_REG_OFFSET 0x30c

Definition at line 2279 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_65_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_65_REG_RESVAL 0x0u

Definition at line 2280 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_65_SCHMITT_EN_65_BIT

#define PINMUX_DIO_PAD_ATTR_65_SCHMITT_EN_65_BIT 5

Definition at line 2286 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_65_SLEW_RATE_65_FIELD

#define PINMUX_DIO_PAD_ATTR_65_SLEW_RATE_65_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_65_SLEW_RATE_65_MASK, .index = PINMUX_DIO_PAD_ATTR_65_SLEW_RATE_65_OFFSET })

Definition at line 2291 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_65_SLEW_RATE_65_MASK

#define PINMUX_DIO_PAD_ATTR_65_SLEW_RATE_65_MASK 0x3u

Definition at line 2289 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_65_SLEW_RATE_65_OFFSET

#define PINMUX_DIO_PAD_ATTR_65_SLEW_RATE_65_OFFSET 16

Definition at line 2290 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_65_VIRTUAL_OD_EN_65_BIT

#define PINMUX_DIO_PAD_ATTR_65_VIRTUAL_OD_EN_65_BIT 1

Definition at line 2282 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_66_DRIVE_STRENGTH_66_FIELD

#define PINMUX_DIO_PAD_ATTR_66_DRIVE_STRENGTH_66_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_66_DRIVE_STRENGTH_66_MASK, .index = PINMUX_DIO_PAD_ATTR_66_DRIVE_STRENGTH_66_OFFSET })

Definition at line 2315 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_66_DRIVE_STRENGTH_66_MASK

#define PINMUX_DIO_PAD_ATTR_66_DRIVE_STRENGTH_66_MASK 0xfu

Definition at line 2313 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_66_DRIVE_STRENGTH_66_OFFSET

#define PINMUX_DIO_PAD_ATTR_66_DRIVE_STRENGTH_66_OFFSET 20

Definition at line 2314 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_66_INPUT_DISABLE_66_BIT

#define PINMUX_DIO_PAD_ATTR_66_INPUT_DISABLE_66_BIT 7

Definition at line 2308 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_66_INVERT_66_BIT

#define PINMUX_DIO_PAD_ATTR_66_INVERT_66_BIT 0

Definition at line 2301 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_66_KEEPER_EN_66_BIT

#define PINMUX_DIO_PAD_ATTR_66_KEEPER_EN_66_BIT 4

Definition at line 2305 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_66_OD_EN_66_BIT

#define PINMUX_DIO_PAD_ATTR_66_OD_EN_66_BIT 6

Definition at line 2307 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_66_PULL_EN_66_BIT

#define PINMUX_DIO_PAD_ATTR_66_PULL_EN_66_BIT 2

Definition at line 2303 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_66_PULL_SELECT_66_BIT

#define PINMUX_DIO_PAD_ATTR_66_PULL_SELECT_66_BIT 3

Definition at line 2304 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_66_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_66_REG_OFFSET 0x310

Definition at line 2299 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_66_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_66_REG_RESVAL 0x0u

Definition at line 2300 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_66_SCHMITT_EN_66_BIT

#define PINMUX_DIO_PAD_ATTR_66_SCHMITT_EN_66_BIT 5

Definition at line 2306 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_66_SLEW_RATE_66_FIELD

#define PINMUX_DIO_PAD_ATTR_66_SLEW_RATE_66_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_66_SLEW_RATE_66_MASK, .index = PINMUX_DIO_PAD_ATTR_66_SLEW_RATE_66_OFFSET })

Definition at line 2311 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_66_SLEW_RATE_66_MASK

#define PINMUX_DIO_PAD_ATTR_66_SLEW_RATE_66_MASK 0x3u

Definition at line 2309 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_66_SLEW_RATE_66_OFFSET

#define PINMUX_DIO_PAD_ATTR_66_SLEW_RATE_66_OFFSET 16

Definition at line 2310 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_66_VIRTUAL_OD_EN_66_BIT

#define PINMUX_DIO_PAD_ATTR_66_VIRTUAL_OD_EN_66_BIT 1

Definition at line 2302 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_67_DRIVE_STRENGTH_67_FIELD

#define PINMUX_DIO_PAD_ATTR_67_DRIVE_STRENGTH_67_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_67_DRIVE_STRENGTH_67_MASK, .index = PINMUX_DIO_PAD_ATTR_67_DRIVE_STRENGTH_67_OFFSET })

Definition at line 2335 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_67_DRIVE_STRENGTH_67_MASK

#define PINMUX_DIO_PAD_ATTR_67_DRIVE_STRENGTH_67_MASK 0xfu

Definition at line 2333 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_67_DRIVE_STRENGTH_67_OFFSET

#define PINMUX_DIO_PAD_ATTR_67_DRIVE_STRENGTH_67_OFFSET 20

Definition at line 2334 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_67_INPUT_DISABLE_67_BIT

#define PINMUX_DIO_PAD_ATTR_67_INPUT_DISABLE_67_BIT 7

Definition at line 2328 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_67_INVERT_67_BIT

#define PINMUX_DIO_PAD_ATTR_67_INVERT_67_BIT 0

Definition at line 2321 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_67_KEEPER_EN_67_BIT

#define PINMUX_DIO_PAD_ATTR_67_KEEPER_EN_67_BIT 4

Definition at line 2325 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_67_OD_EN_67_BIT

#define PINMUX_DIO_PAD_ATTR_67_OD_EN_67_BIT 6

Definition at line 2327 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_67_PULL_EN_67_BIT

#define PINMUX_DIO_PAD_ATTR_67_PULL_EN_67_BIT 2

Definition at line 2323 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_67_PULL_SELECT_67_BIT

#define PINMUX_DIO_PAD_ATTR_67_PULL_SELECT_67_BIT 3

Definition at line 2324 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_67_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_67_REG_OFFSET 0x314

Definition at line 2319 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_67_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_67_REG_RESVAL 0x0u

Definition at line 2320 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_67_SCHMITT_EN_67_BIT

#define PINMUX_DIO_PAD_ATTR_67_SCHMITT_EN_67_BIT 5

Definition at line 2326 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_67_SLEW_RATE_67_FIELD

#define PINMUX_DIO_PAD_ATTR_67_SLEW_RATE_67_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_67_SLEW_RATE_67_MASK, .index = PINMUX_DIO_PAD_ATTR_67_SLEW_RATE_67_OFFSET })

Definition at line 2331 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_67_SLEW_RATE_67_MASK

#define PINMUX_DIO_PAD_ATTR_67_SLEW_RATE_67_MASK 0x3u

Definition at line 2329 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_67_SLEW_RATE_67_OFFSET

#define PINMUX_DIO_PAD_ATTR_67_SLEW_RATE_67_OFFSET 16

Definition at line 2330 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_67_VIRTUAL_OD_EN_67_BIT

#define PINMUX_DIO_PAD_ATTR_67_VIRTUAL_OD_EN_67_BIT 1

Definition at line 2322 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_68_DRIVE_STRENGTH_68_FIELD

#define PINMUX_DIO_PAD_ATTR_68_DRIVE_STRENGTH_68_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_68_DRIVE_STRENGTH_68_MASK, .index = PINMUX_DIO_PAD_ATTR_68_DRIVE_STRENGTH_68_OFFSET })

Definition at line 2355 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_68_DRIVE_STRENGTH_68_MASK

#define PINMUX_DIO_PAD_ATTR_68_DRIVE_STRENGTH_68_MASK 0xfu

Definition at line 2353 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_68_DRIVE_STRENGTH_68_OFFSET

#define PINMUX_DIO_PAD_ATTR_68_DRIVE_STRENGTH_68_OFFSET 20

Definition at line 2354 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_68_INPUT_DISABLE_68_BIT

#define PINMUX_DIO_PAD_ATTR_68_INPUT_DISABLE_68_BIT 7

Definition at line 2348 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_68_INVERT_68_BIT

#define PINMUX_DIO_PAD_ATTR_68_INVERT_68_BIT 0

Definition at line 2341 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_68_KEEPER_EN_68_BIT

#define PINMUX_DIO_PAD_ATTR_68_KEEPER_EN_68_BIT 4

Definition at line 2345 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_68_OD_EN_68_BIT

#define PINMUX_DIO_PAD_ATTR_68_OD_EN_68_BIT 6

Definition at line 2347 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_68_PULL_EN_68_BIT

#define PINMUX_DIO_PAD_ATTR_68_PULL_EN_68_BIT 2

Definition at line 2343 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_68_PULL_SELECT_68_BIT

#define PINMUX_DIO_PAD_ATTR_68_PULL_SELECT_68_BIT 3

Definition at line 2344 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_68_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_68_REG_OFFSET 0x318

Definition at line 2339 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_68_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_68_REG_RESVAL 0x0u

Definition at line 2340 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_68_SCHMITT_EN_68_BIT

#define PINMUX_DIO_PAD_ATTR_68_SCHMITT_EN_68_BIT 5

Definition at line 2346 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_68_SLEW_RATE_68_FIELD

#define PINMUX_DIO_PAD_ATTR_68_SLEW_RATE_68_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_68_SLEW_RATE_68_MASK, .index = PINMUX_DIO_PAD_ATTR_68_SLEW_RATE_68_OFFSET })

Definition at line 2351 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_68_SLEW_RATE_68_MASK

#define PINMUX_DIO_PAD_ATTR_68_SLEW_RATE_68_MASK 0x3u

Definition at line 2349 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_68_SLEW_RATE_68_OFFSET

#define PINMUX_DIO_PAD_ATTR_68_SLEW_RATE_68_OFFSET 16

Definition at line 2350 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_68_VIRTUAL_OD_EN_68_BIT

#define PINMUX_DIO_PAD_ATTR_68_VIRTUAL_OD_EN_68_BIT 1

Definition at line 2342 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_69_DRIVE_STRENGTH_69_FIELD

#define PINMUX_DIO_PAD_ATTR_69_DRIVE_STRENGTH_69_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_69_DRIVE_STRENGTH_69_MASK, .index = PINMUX_DIO_PAD_ATTR_69_DRIVE_STRENGTH_69_OFFSET })

Definition at line 2375 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_69_DRIVE_STRENGTH_69_MASK

#define PINMUX_DIO_PAD_ATTR_69_DRIVE_STRENGTH_69_MASK 0xfu

Definition at line 2373 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_69_DRIVE_STRENGTH_69_OFFSET

#define PINMUX_DIO_PAD_ATTR_69_DRIVE_STRENGTH_69_OFFSET 20

Definition at line 2374 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_69_INPUT_DISABLE_69_BIT

#define PINMUX_DIO_PAD_ATTR_69_INPUT_DISABLE_69_BIT 7

Definition at line 2368 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_69_INVERT_69_BIT

#define PINMUX_DIO_PAD_ATTR_69_INVERT_69_BIT 0

Definition at line 2361 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_69_KEEPER_EN_69_BIT

#define PINMUX_DIO_PAD_ATTR_69_KEEPER_EN_69_BIT 4

Definition at line 2365 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_69_OD_EN_69_BIT

#define PINMUX_DIO_PAD_ATTR_69_OD_EN_69_BIT 6

Definition at line 2367 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_69_PULL_EN_69_BIT

#define PINMUX_DIO_PAD_ATTR_69_PULL_EN_69_BIT 2

Definition at line 2363 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_69_PULL_SELECT_69_BIT

#define PINMUX_DIO_PAD_ATTR_69_PULL_SELECT_69_BIT 3

Definition at line 2364 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_69_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_69_REG_OFFSET 0x31c

Definition at line 2359 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_69_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_69_REG_RESVAL 0x0u

Definition at line 2360 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_69_SCHMITT_EN_69_BIT

#define PINMUX_DIO_PAD_ATTR_69_SCHMITT_EN_69_BIT 5

Definition at line 2366 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_69_SLEW_RATE_69_FIELD

#define PINMUX_DIO_PAD_ATTR_69_SLEW_RATE_69_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_69_SLEW_RATE_69_MASK, .index = PINMUX_DIO_PAD_ATTR_69_SLEW_RATE_69_OFFSET })

Definition at line 2371 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_69_SLEW_RATE_69_MASK

#define PINMUX_DIO_PAD_ATTR_69_SLEW_RATE_69_MASK 0x3u

Definition at line 2369 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_69_SLEW_RATE_69_OFFSET

#define PINMUX_DIO_PAD_ATTR_69_SLEW_RATE_69_OFFSET 16

Definition at line 2370 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_69_VIRTUAL_OD_EN_69_BIT

#define PINMUX_DIO_PAD_ATTR_69_VIRTUAL_OD_EN_69_BIT 1

Definition at line 2362 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_FIELD

#define PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_MASK, .index = PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_OFFSET })

Definition at line 1115 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_MASK

#define PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_MASK 0xfu

Definition at line 1113 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_OFFSET

#define PINMUX_DIO_PAD_ATTR_6_DRIVE_STRENGTH_6_OFFSET 20

Definition at line 1114 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_6_INPUT_DISABLE_6_BIT

#define PINMUX_DIO_PAD_ATTR_6_INPUT_DISABLE_6_BIT 7

Definition at line 1108 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_6_INVERT_6_BIT

#define PINMUX_DIO_PAD_ATTR_6_INVERT_6_BIT 0

Definition at line 1101 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_6_KEEPER_EN_6_BIT

#define PINMUX_DIO_PAD_ATTR_6_KEEPER_EN_6_BIT 4

Definition at line 1105 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_6_OD_EN_6_BIT

#define PINMUX_DIO_PAD_ATTR_6_OD_EN_6_BIT 6

Definition at line 1107 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_6_PULL_EN_6_BIT

#define PINMUX_DIO_PAD_ATTR_6_PULL_EN_6_BIT 2

Definition at line 1103 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_6_PULL_SELECT_6_BIT

#define PINMUX_DIO_PAD_ATTR_6_PULL_SELECT_6_BIT 3

Definition at line 1104 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_6_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_6_REG_OFFSET 0x220

Definition at line 1099 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_6_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_6_REG_RESVAL 0x0u

Definition at line 1100 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_6_SCHMITT_EN_6_BIT

#define PINMUX_DIO_PAD_ATTR_6_SCHMITT_EN_6_BIT 5

Definition at line 1106 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_FIELD

#define PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_MASK, .index = PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_OFFSET })

Definition at line 1111 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_MASK

#define PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_MASK 0x3u

Definition at line 1109 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_OFFSET

#define PINMUX_DIO_PAD_ATTR_6_SLEW_RATE_6_OFFSET 16

Definition at line 1110 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_6_VIRTUAL_OD_EN_6_BIT

#define PINMUX_DIO_PAD_ATTR_6_VIRTUAL_OD_EN_6_BIT 1

Definition at line 1102 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_70_DRIVE_STRENGTH_70_FIELD

#define PINMUX_DIO_PAD_ATTR_70_DRIVE_STRENGTH_70_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_70_DRIVE_STRENGTH_70_MASK, .index = PINMUX_DIO_PAD_ATTR_70_DRIVE_STRENGTH_70_OFFSET })

Definition at line 2395 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_70_DRIVE_STRENGTH_70_MASK

#define PINMUX_DIO_PAD_ATTR_70_DRIVE_STRENGTH_70_MASK 0xfu

Definition at line 2393 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_70_DRIVE_STRENGTH_70_OFFSET

#define PINMUX_DIO_PAD_ATTR_70_DRIVE_STRENGTH_70_OFFSET 20

Definition at line 2394 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_70_INPUT_DISABLE_70_BIT

#define PINMUX_DIO_PAD_ATTR_70_INPUT_DISABLE_70_BIT 7

Definition at line 2388 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_70_INVERT_70_BIT

#define PINMUX_DIO_PAD_ATTR_70_INVERT_70_BIT 0

Definition at line 2381 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_70_KEEPER_EN_70_BIT

#define PINMUX_DIO_PAD_ATTR_70_KEEPER_EN_70_BIT 4

Definition at line 2385 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_70_OD_EN_70_BIT

#define PINMUX_DIO_PAD_ATTR_70_OD_EN_70_BIT 6

Definition at line 2387 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_70_PULL_EN_70_BIT

#define PINMUX_DIO_PAD_ATTR_70_PULL_EN_70_BIT 2

Definition at line 2383 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_70_PULL_SELECT_70_BIT

#define PINMUX_DIO_PAD_ATTR_70_PULL_SELECT_70_BIT 3

Definition at line 2384 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_70_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_70_REG_OFFSET 0x320

Definition at line 2379 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_70_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_70_REG_RESVAL 0x0u

Definition at line 2380 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_70_SCHMITT_EN_70_BIT

#define PINMUX_DIO_PAD_ATTR_70_SCHMITT_EN_70_BIT 5

Definition at line 2386 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_70_SLEW_RATE_70_FIELD

#define PINMUX_DIO_PAD_ATTR_70_SLEW_RATE_70_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_70_SLEW_RATE_70_MASK, .index = PINMUX_DIO_PAD_ATTR_70_SLEW_RATE_70_OFFSET })

Definition at line 2391 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_70_SLEW_RATE_70_MASK

#define PINMUX_DIO_PAD_ATTR_70_SLEW_RATE_70_MASK 0x3u

Definition at line 2389 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_70_SLEW_RATE_70_OFFSET

#define PINMUX_DIO_PAD_ATTR_70_SLEW_RATE_70_OFFSET 16

Definition at line 2390 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_70_VIRTUAL_OD_EN_70_BIT

#define PINMUX_DIO_PAD_ATTR_70_VIRTUAL_OD_EN_70_BIT 1

Definition at line 2382 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_71_DRIVE_STRENGTH_71_FIELD

#define PINMUX_DIO_PAD_ATTR_71_DRIVE_STRENGTH_71_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_71_DRIVE_STRENGTH_71_MASK, .index = PINMUX_DIO_PAD_ATTR_71_DRIVE_STRENGTH_71_OFFSET })

Definition at line 2415 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_71_DRIVE_STRENGTH_71_MASK

#define PINMUX_DIO_PAD_ATTR_71_DRIVE_STRENGTH_71_MASK 0xfu

Definition at line 2413 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_71_DRIVE_STRENGTH_71_OFFSET

#define PINMUX_DIO_PAD_ATTR_71_DRIVE_STRENGTH_71_OFFSET 20

Definition at line 2414 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_71_INPUT_DISABLE_71_BIT

#define PINMUX_DIO_PAD_ATTR_71_INPUT_DISABLE_71_BIT 7

Definition at line 2408 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_71_INVERT_71_BIT

#define PINMUX_DIO_PAD_ATTR_71_INVERT_71_BIT 0

Definition at line 2401 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_71_KEEPER_EN_71_BIT

#define PINMUX_DIO_PAD_ATTR_71_KEEPER_EN_71_BIT 4

Definition at line 2405 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_71_OD_EN_71_BIT

#define PINMUX_DIO_PAD_ATTR_71_OD_EN_71_BIT 6

Definition at line 2407 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_71_PULL_EN_71_BIT

#define PINMUX_DIO_PAD_ATTR_71_PULL_EN_71_BIT 2

Definition at line 2403 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_71_PULL_SELECT_71_BIT

#define PINMUX_DIO_PAD_ATTR_71_PULL_SELECT_71_BIT 3

Definition at line 2404 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_71_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_71_REG_OFFSET 0x324

Definition at line 2399 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_71_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_71_REG_RESVAL 0x0u

Definition at line 2400 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_71_SCHMITT_EN_71_BIT

#define PINMUX_DIO_PAD_ATTR_71_SCHMITT_EN_71_BIT 5

Definition at line 2406 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_71_SLEW_RATE_71_FIELD

#define PINMUX_DIO_PAD_ATTR_71_SLEW_RATE_71_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_71_SLEW_RATE_71_MASK, .index = PINMUX_DIO_PAD_ATTR_71_SLEW_RATE_71_OFFSET })

Definition at line 2411 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_71_SLEW_RATE_71_MASK

#define PINMUX_DIO_PAD_ATTR_71_SLEW_RATE_71_MASK 0x3u

Definition at line 2409 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_71_SLEW_RATE_71_OFFSET

#define PINMUX_DIO_PAD_ATTR_71_SLEW_RATE_71_OFFSET 16

Definition at line 2410 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_71_VIRTUAL_OD_EN_71_BIT

#define PINMUX_DIO_PAD_ATTR_71_VIRTUAL_OD_EN_71_BIT 1

Definition at line 2402 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_72_DRIVE_STRENGTH_72_FIELD

#define PINMUX_DIO_PAD_ATTR_72_DRIVE_STRENGTH_72_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_72_DRIVE_STRENGTH_72_MASK, .index = PINMUX_DIO_PAD_ATTR_72_DRIVE_STRENGTH_72_OFFSET })

Definition at line 2435 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_72_DRIVE_STRENGTH_72_MASK

#define PINMUX_DIO_PAD_ATTR_72_DRIVE_STRENGTH_72_MASK 0xfu

Definition at line 2433 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_72_DRIVE_STRENGTH_72_OFFSET

#define PINMUX_DIO_PAD_ATTR_72_DRIVE_STRENGTH_72_OFFSET 20

Definition at line 2434 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_72_INPUT_DISABLE_72_BIT

#define PINMUX_DIO_PAD_ATTR_72_INPUT_DISABLE_72_BIT 7

Definition at line 2428 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_72_INVERT_72_BIT

#define PINMUX_DIO_PAD_ATTR_72_INVERT_72_BIT 0

Definition at line 2421 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_72_KEEPER_EN_72_BIT

#define PINMUX_DIO_PAD_ATTR_72_KEEPER_EN_72_BIT 4

Definition at line 2425 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_72_OD_EN_72_BIT

#define PINMUX_DIO_PAD_ATTR_72_OD_EN_72_BIT 6

Definition at line 2427 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_72_PULL_EN_72_BIT

#define PINMUX_DIO_PAD_ATTR_72_PULL_EN_72_BIT 2

Definition at line 2423 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_72_PULL_SELECT_72_BIT

#define PINMUX_DIO_PAD_ATTR_72_PULL_SELECT_72_BIT 3

Definition at line 2424 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_72_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_72_REG_OFFSET 0x328

Definition at line 2419 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_72_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_72_REG_RESVAL 0x0u

Definition at line 2420 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_72_SCHMITT_EN_72_BIT

#define PINMUX_DIO_PAD_ATTR_72_SCHMITT_EN_72_BIT 5

Definition at line 2426 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_72_SLEW_RATE_72_FIELD

#define PINMUX_DIO_PAD_ATTR_72_SLEW_RATE_72_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_72_SLEW_RATE_72_MASK, .index = PINMUX_DIO_PAD_ATTR_72_SLEW_RATE_72_OFFSET })

Definition at line 2431 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_72_SLEW_RATE_72_MASK

#define PINMUX_DIO_PAD_ATTR_72_SLEW_RATE_72_MASK 0x3u

Definition at line 2429 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_72_SLEW_RATE_72_OFFSET

#define PINMUX_DIO_PAD_ATTR_72_SLEW_RATE_72_OFFSET 16

Definition at line 2430 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_72_VIRTUAL_OD_EN_72_BIT

#define PINMUX_DIO_PAD_ATTR_72_VIRTUAL_OD_EN_72_BIT 1

Definition at line 2422 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_FIELD

#define PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_MASK, .index = PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_OFFSET })

Definition at line 1135 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_MASK

#define PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_MASK 0xfu

Definition at line 1133 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_OFFSET

#define PINMUX_DIO_PAD_ATTR_7_DRIVE_STRENGTH_7_OFFSET 20

Definition at line 1134 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_7_INPUT_DISABLE_7_BIT

#define PINMUX_DIO_PAD_ATTR_7_INPUT_DISABLE_7_BIT 7

Definition at line 1128 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_7_INVERT_7_BIT

#define PINMUX_DIO_PAD_ATTR_7_INVERT_7_BIT 0

Definition at line 1121 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_7_KEEPER_EN_7_BIT

#define PINMUX_DIO_PAD_ATTR_7_KEEPER_EN_7_BIT 4

Definition at line 1125 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_7_OD_EN_7_BIT

#define PINMUX_DIO_PAD_ATTR_7_OD_EN_7_BIT 6

Definition at line 1127 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_7_PULL_EN_7_BIT

#define PINMUX_DIO_PAD_ATTR_7_PULL_EN_7_BIT 2

Definition at line 1123 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_7_PULL_SELECT_7_BIT

#define PINMUX_DIO_PAD_ATTR_7_PULL_SELECT_7_BIT 3

Definition at line 1124 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_7_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_7_REG_OFFSET 0x224

Definition at line 1119 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_7_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_7_REG_RESVAL 0x0u

Definition at line 1120 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_7_SCHMITT_EN_7_BIT

#define PINMUX_DIO_PAD_ATTR_7_SCHMITT_EN_7_BIT 5

Definition at line 1126 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_FIELD

#define PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_MASK, .index = PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_OFFSET })

Definition at line 1131 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_MASK

#define PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_MASK 0x3u

Definition at line 1129 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_OFFSET

#define PINMUX_DIO_PAD_ATTR_7_SLEW_RATE_7_OFFSET 16

Definition at line 1130 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_7_VIRTUAL_OD_EN_7_BIT

#define PINMUX_DIO_PAD_ATTR_7_VIRTUAL_OD_EN_7_BIT 1

Definition at line 1122 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_FIELD

#define PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_MASK, .index = PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_OFFSET })

Definition at line 1155 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_MASK

#define PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_MASK 0xfu

Definition at line 1153 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_OFFSET

#define PINMUX_DIO_PAD_ATTR_8_DRIVE_STRENGTH_8_OFFSET 20

Definition at line 1154 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_8_INPUT_DISABLE_8_BIT

#define PINMUX_DIO_PAD_ATTR_8_INPUT_DISABLE_8_BIT 7

Definition at line 1148 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_8_INVERT_8_BIT

#define PINMUX_DIO_PAD_ATTR_8_INVERT_8_BIT 0

Definition at line 1141 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_8_KEEPER_EN_8_BIT

#define PINMUX_DIO_PAD_ATTR_8_KEEPER_EN_8_BIT 4

Definition at line 1145 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_8_OD_EN_8_BIT

#define PINMUX_DIO_PAD_ATTR_8_OD_EN_8_BIT 6

Definition at line 1147 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_8_PULL_EN_8_BIT

#define PINMUX_DIO_PAD_ATTR_8_PULL_EN_8_BIT 2

Definition at line 1143 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_8_PULL_SELECT_8_BIT

#define PINMUX_DIO_PAD_ATTR_8_PULL_SELECT_8_BIT 3

Definition at line 1144 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_8_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_8_REG_OFFSET 0x228

Definition at line 1139 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_8_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_8_REG_RESVAL 0x0u

Definition at line 1140 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_8_SCHMITT_EN_8_BIT

#define PINMUX_DIO_PAD_ATTR_8_SCHMITT_EN_8_BIT 5

Definition at line 1146 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_FIELD

#define PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_MASK, .index = PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_OFFSET })

Definition at line 1151 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_MASK

#define PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_MASK 0x3u

Definition at line 1149 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_OFFSET

#define PINMUX_DIO_PAD_ATTR_8_SLEW_RATE_8_OFFSET 16

Definition at line 1150 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_8_VIRTUAL_OD_EN_8_BIT

#define PINMUX_DIO_PAD_ATTR_8_VIRTUAL_OD_EN_8_BIT 1

Definition at line 1142 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_FIELD

#define PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_MASK, .index = PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_OFFSET })

Definition at line 1175 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_MASK

#define PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_MASK 0xfu

Definition at line 1173 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_OFFSET

#define PINMUX_DIO_PAD_ATTR_9_DRIVE_STRENGTH_9_OFFSET 20

Definition at line 1174 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_9_INPUT_DISABLE_9_BIT

#define PINMUX_DIO_PAD_ATTR_9_INPUT_DISABLE_9_BIT 7

Definition at line 1168 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_9_INVERT_9_BIT

#define PINMUX_DIO_PAD_ATTR_9_INVERT_9_BIT 0

Definition at line 1161 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_9_KEEPER_EN_9_BIT

#define PINMUX_DIO_PAD_ATTR_9_KEEPER_EN_9_BIT 4

Definition at line 1165 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_9_OD_EN_9_BIT

#define PINMUX_DIO_PAD_ATTR_9_OD_EN_9_BIT 6

Definition at line 1167 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_9_PULL_EN_9_BIT

#define PINMUX_DIO_PAD_ATTR_9_PULL_EN_9_BIT 2

Definition at line 1163 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_9_PULL_SELECT_9_BIT

#define PINMUX_DIO_PAD_ATTR_9_PULL_SELECT_9_BIT 3

Definition at line 1164 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_9_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_9_REG_OFFSET 0x22c

Definition at line 1159 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_9_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_9_REG_RESVAL 0x0u

Definition at line 1160 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_9_SCHMITT_EN_9_BIT

#define PINMUX_DIO_PAD_ATTR_9_SCHMITT_EN_9_BIT 5

Definition at line 1166 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_FIELD

#define PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_MASK, .index = PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_OFFSET })

Definition at line 1171 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_MASK

#define PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_MASK 0x3u

Definition at line 1169 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_OFFSET

#define PINMUX_DIO_PAD_ATTR_9_SLEW_RATE_9_OFFSET 16

Definition at line 1170 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_9_VIRTUAL_OD_EN_9_BIT

#define PINMUX_DIO_PAD_ATTR_9_VIRTUAL_OD_EN_9_BIT 1

Definition at line 1162 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_DRIVE_STRENGTH_FIELD_WIDTH

#define PINMUX_DIO_PAD_ATTR_DRIVE_STRENGTH_FIELD_WIDTH 4

Definition at line 973 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_INPUT_DISABLE_FIELD_WIDTH

#define PINMUX_DIO_PAD_ATTR_INPUT_DISABLE_FIELD_WIDTH 1

Definition at line 971 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_INVERT_FIELD_WIDTH

#define PINMUX_DIO_PAD_ATTR_INVERT_FIELD_WIDTH 1

Definition at line 964 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_KEEPER_EN_FIELD_WIDTH

#define PINMUX_DIO_PAD_ATTR_KEEPER_EN_FIELD_WIDTH 1

Definition at line 968 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_MULTIREG_COUNT

#define PINMUX_DIO_PAD_ATTR_MULTIREG_COUNT 73

Definition at line 974 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_OD_EN_FIELD_WIDTH

#define PINMUX_DIO_PAD_ATTR_OD_EN_FIELD_WIDTH 1

Definition at line 970 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_PULL_EN_FIELD_WIDTH

#define PINMUX_DIO_PAD_ATTR_PULL_EN_FIELD_WIDTH 1

Definition at line 966 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_PULL_SELECT_FIELD_WIDTH

#define PINMUX_DIO_PAD_ATTR_PULL_SELECT_FIELD_WIDTH 1

Definition at line 967 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_0_EN_0_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_0_EN_0_BIT 0

Definition at line 601 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_0_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_0_REG_OFFSET 0xe4

Definition at line 599 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_0_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_0_REG_RESVAL 0x1u

Definition at line 600 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_10_EN_10_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_10_EN_10_BIT 0

Definition at line 651 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_10_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_10_REG_OFFSET 0x10c

Definition at line 649 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_10_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_10_REG_RESVAL 0x1u

Definition at line 650 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_11_EN_11_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_11_EN_11_BIT 0

Definition at line 656 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_11_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_11_REG_OFFSET 0x110

Definition at line 654 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_11_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_11_REG_RESVAL 0x1u

Definition at line 655 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_12_EN_12_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_12_EN_12_BIT 0

Definition at line 661 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_12_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_12_REG_OFFSET 0x114

Definition at line 659 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_12_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_12_REG_RESVAL 0x1u

Definition at line 660 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_13_EN_13_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_13_EN_13_BIT 0

Definition at line 666 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_13_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_13_REG_OFFSET 0x118

Definition at line 664 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_13_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_13_REG_RESVAL 0x1u

Definition at line 665 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_14_EN_14_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_14_EN_14_BIT 0

Definition at line 671 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_14_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_14_REG_OFFSET 0x11c

Definition at line 669 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_14_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_14_REG_RESVAL 0x1u

Definition at line 670 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_15_EN_15_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_15_EN_15_BIT 0

Definition at line 676 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_15_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_15_REG_OFFSET 0x120

Definition at line 674 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_15_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_15_REG_RESVAL 0x1u

Definition at line 675 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_16_EN_16_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_16_EN_16_BIT 0

Definition at line 681 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_16_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_16_REG_OFFSET 0x124

Definition at line 679 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_16_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_16_REG_RESVAL 0x1u

Definition at line 680 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_17_EN_17_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_17_EN_17_BIT 0

Definition at line 686 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_17_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_17_REG_OFFSET 0x128

Definition at line 684 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_17_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_17_REG_RESVAL 0x1u

Definition at line 685 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_18_EN_18_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_18_EN_18_BIT 0

Definition at line 691 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_18_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_18_REG_OFFSET 0x12c

Definition at line 689 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_18_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_18_REG_RESVAL 0x1u

Definition at line 690 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_19_EN_19_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_19_EN_19_BIT 0

Definition at line 696 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_19_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_19_REG_OFFSET 0x130

Definition at line 694 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_19_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_19_REG_RESVAL 0x1u

Definition at line 695 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_1_EN_1_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_1_EN_1_BIT 0

Definition at line 606 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_1_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_1_REG_OFFSET 0xe8

Definition at line 604 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_1_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_1_REG_RESVAL 0x1u

Definition at line 605 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_20_EN_20_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_20_EN_20_BIT 0

Definition at line 701 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_20_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_20_REG_OFFSET 0x134

Definition at line 699 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_20_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_20_REG_RESVAL 0x1u

Definition at line 700 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_21_EN_21_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_21_EN_21_BIT 0

Definition at line 706 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_21_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_21_REG_OFFSET 0x138

Definition at line 704 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_21_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_21_REG_RESVAL 0x1u

Definition at line 705 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_22_EN_22_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_22_EN_22_BIT 0

Definition at line 711 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_22_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_22_REG_OFFSET 0x13c

Definition at line 709 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_22_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_22_REG_RESVAL 0x1u

Definition at line 710 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_23_EN_23_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_23_EN_23_BIT 0

Definition at line 716 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_23_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_23_REG_OFFSET 0x140

Definition at line 714 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_23_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_23_REG_RESVAL 0x1u

Definition at line 715 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_24_EN_24_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_24_EN_24_BIT 0

Definition at line 721 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_24_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_24_REG_OFFSET 0x144

Definition at line 719 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_24_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_24_REG_RESVAL 0x1u

Definition at line 720 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_25_EN_25_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_25_EN_25_BIT 0

Definition at line 726 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_25_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_25_REG_OFFSET 0x148

Definition at line 724 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_25_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_25_REG_RESVAL 0x1u

Definition at line 725 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_26_EN_26_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_26_EN_26_BIT 0

Definition at line 731 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_26_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_26_REG_OFFSET 0x14c

Definition at line 729 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_26_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_26_REG_RESVAL 0x1u

Definition at line 730 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_27_EN_27_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_27_EN_27_BIT 0

Definition at line 736 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_27_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_27_REG_OFFSET 0x150

Definition at line 734 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_27_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_27_REG_RESVAL 0x1u

Definition at line 735 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_28_EN_28_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_28_EN_28_BIT 0

Definition at line 741 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_28_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_28_REG_OFFSET 0x154

Definition at line 739 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_28_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_28_REG_RESVAL 0x1u

Definition at line 740 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_29_EN_29_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_29_EN_29_BIT 0

Definition at line 746 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_29_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_29_REG_OFFSET 0x158

Definition at line 744 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_29_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_29_REG_RESVAL 0x1u

Definition at line 745 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_2_EN_2_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_2_EN_2_BIT 0

Definition at line 611 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_2_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_2_REG_OFFSET 0xec

Definition at line 609 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_2_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_2_REG_RESVAL 0x1u

Definition at line 610 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_30_EN_30_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_30_EN_30_BIT 0

Definition at line 751 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_30_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_30_REG_OFFSET 0x15c

Definition at line 749 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_30_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_30_REG_RESVAL 0x1u

Definition at line 750 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_31_EN_31_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_31_EN_31_BIT 0

Definition at line 756 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_31_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_31_REG_OFFSET 0x160

Definition at line 754 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_31_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_31_REG_RESVAL 0x1u

Definition at line 755 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_32_EN_32_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_32_EN_32_BIT 0

Definition at line 761 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_32_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_32_REG_OFFSET 0x164

Definition at line 759 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_32_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_32_REG_RESVAL 0x1u

Definition at line 760 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_33_EN_33_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_33_EN_33_BIT 0

Definition at line 766 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_33_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_33_REG_OFFSET 0x168

Definition at line 764 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_33_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_33_REG_RESVAL 0x1u

Definition at line 765 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_34_EN_34_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_34_EN_34_BIT 0

Definition at line 771 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_34_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_34_REG_OFFSET 0x16c

Definition at line 769 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_34_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_34_REG_RESVAL 0x1u

Definition at line 770 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_35_EN_35_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_35_EN_35_BIT 0

Definition at line 776 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_35_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_35_REG_OFFSET 0x170

Definition at line 774 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_35_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_35_REG_RESVAL 0x1u

Definition at line 775 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_36_EN_36_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_36_EN_36_BIT 0

Definition at line 781 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_36_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_36_REG_OFFSET 0x174

Definition at line 779 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_36_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_36_REG_RESVAL 0x1u

Definition at line 780 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_37_EN_37_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_37_EN_37_BIT 0

Definition at line 786 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_37_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_37_REG_OFFSET 0x178

Definition at line 784 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_37_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_37_REG_RESVAL 0x1u

Definition at line 785 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_38_EN_38_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_38_EN_38_BIT 0

Definition at line 791 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_38_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_38_REG_OFFSET 0x17c

Definition at line 789 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_38_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_38_REG_RESVAL 0x1u

Definition at line 790 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_39_EN_39_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_39_EN_39_BIT 0

Definition at line 796 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_39_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_39_REG_OFFSET 0x180

Definition at line 794 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_39_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_39_REG_RESVAL 0x1u

Definition at line 795 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_3_EN_3_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_3_EN_3_BIT 0

Definition at line 616 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_3_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_3_REG_OFFSET 0xf0

Definition at line 614 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_3_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_3_REG_RESVAL 0x1u

Definition at line 615 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_40_EN_40_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_40_EN_40_BIT 0

Definition at line 801 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_40_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_40_REG_OFFSET 0x184

Definition at line 799 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_40_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_40_REG_RESVAL 0x1u

Definition at line 800 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_41_EN_41_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_41_EN_41_BIT 0

Definition at line 806 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_41_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_41_REG_OFFSET 0x188

Definition at line 804 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_41_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_41_REG_RESVAL 0x1u

Definition at line 805 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_42_EN_42_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_42_EN_42_BIT 0

Definition at line 811 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_42_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_42_REG_OFFSET 0x18c

Definition at line 809 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_42_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_42_REG_RESVAL 0x1u

Definition at line 810 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_43_EN_43_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_43_EN_43_BIT 0

Definition at line 816 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_43_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_43_REG_OFFSET 0x190

Definition at line 814 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_43_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_43_REG_RESVAL 0x1u

Definition at line 815 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_44_EN_44_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_44_EN_44_BIT 0

Definition at line 821 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_44_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_44_REG_OFFSET 0x194

Definition at line 819 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_44_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_44_REG_RESVAL 0x1u

Definition at line 820 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_45_EN_45_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_45_EN_45_BIT 0

Definition at line 826 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_45_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_45_REG_OFFSET 0x198

Definition at line 824 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_45_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_45_REG_RESVAL 0x1u

Definition at line 825 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_46_EN_46_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_46_EN_46_BIT 0

Definition at line 831 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_46_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_46_REG_OFFSET 0x19c

Definition at line 829 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_46_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_46_REG_RESVAL 0x1u

Definition at line 830 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_47_EN_47_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_47_EN_47_BIT 0

Definition at line 836 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_47_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_47_REG_OFFSET 0x1a0

Definition at line 834 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_47_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_47_REG_RESVAL 0x1u

Definition at line 835 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_48_EN_48_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_48_EN_48_BIT 0

Definition at line 841 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_48_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_48_REG_OFFSET 0x1a4

Definition at line 839 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_48_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_48_REG_RESVAL 0x1u

Definition at line 840 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_49_EN_49_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_49_EN_49_BIT 0

Definition at line 846 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_49_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_49_REG_OFFSET 0x1a8

Definition at line 844 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_49_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_49_REG_RESVAL 0x1u

Definition at line 845 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_4_EN_4_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_4_EN_4_BIT 0

Definition at line 621 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_4_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_4_REG_OFFSET 0xf4

Definition at line 619 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_4_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_4_REG_RESVAL 0x1u

Definition at line 620 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_50_EN_50_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_50_EN_50_BIT 0

Definition at line 851 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_50_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_50_REG_OFFSET 0x1ac

Definition at line 849 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_50_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_50_REG_RESVAL 0x1u

Definition at line 850 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_51_EN_51_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_51_EN_51_BIT 0

Definition at line 856 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_51_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_51_REG_OFFSET 0x1b0

Definition at line 854 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_51_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_51_REG_RESVAL 0x1u

Definition at line 855 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_52_EN_52_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_52_EN_52_BIT 0

Definition at line 861 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_52_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_52_REG_OFFSET 0x1b4

Definition at line 859 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_52_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_52_REG_RESVAL 0x1u

Definition at line 860 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_53_EN_53_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_53_EN_53_BIT 0

Definition at line 866 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_53_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_53_REG_OFFSET 0x1b8

Definition at line 864 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_53_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_53_REG_RESVAL 0x1u

Definition at line 865 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_54_EN_54_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_54_EN_54_BIT 0

Definition at line 871 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_54_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_54_REG_OFFSET 0x1bc

Definition at line 869 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_54_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_54_REG_RESVAL 0x1u

Definition at line 870 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_55_EN_55_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_55_EN_55_BIT 0

Definition at line 876 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_55_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_55_REG_OFFSET 0x1c0

Definition at line 874 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_55_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_55_REG_RESVAL 0x1u

Definition at line 875 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_56_EN_56_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_56_EN_56_BIT 0

Definition at line 881 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_56_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_56_REG_OFFSET 0x1c4

Definition at line 879 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_56_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_56_REG_RESVAL 0x1u

Definition at line 880 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_57_EN_57_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_57_EN_57_BIT 0

Definition at line 886 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_57_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_57_REG_OFFSET 0x1c8

Definition at line 884 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_57_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_57_REG_RESVAL 0x1u

Definition at line 885 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_58_EN_58_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_58_EN_58_BIT 0

Definition at line 891 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_58_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_58_REG_OFFSET 0x1cc

Definition at line 889 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_58_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_58_REG_RESVAL 0x1u

Definition at line 890 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_59_EN_59_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_59_EN_59_BIT 0

Definition at line 896 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_59_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_59_REG_OFFSET 0x1d0

Definition at line 894 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_59_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_59_REG_RESVAL 0x1u

Definition at line 895 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_5_EN_5_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_5_EN_5_BIT 0

Definition at line 626 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_5_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_5_REG_OFFSET 0xf8

Definition at line 624 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_5_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_5_REG_RESVAL 0x1u

Definition at line 625 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_60_EN_60_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_60_EN_60_BIT 0

Definition at line 901 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_60_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_60_REG_OFFSET 0x1d4

Definition at line 899 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_60_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_60_REG_RESVAL 0x1u

Definition at line 900 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_61_EN_61_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_61_EN_61_BIT 0

Definition at line 906 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_61_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_61_REG_OFFSET 0x1d8

Definition at line 904 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_61_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_61_REG_RESVAL 0x1u

Definition at line 905 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_62_EN_62_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_62_EN_62_BIT 0

Definition at line 911 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_62_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_62_REG_OFFSET 0x1dc

Definition at line 909 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_62_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_62_REG_RESVAL 0x1u

Definition at line 910 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_63_EN_63_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_63_EN_63_BIT 0

Definition at line 916 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_63_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_63_REG_OFFSET 0x1e0

Definition at line 914 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_63_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_63_REG_RESVAL 0x1u

Definition at line 915 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_64_EN_64_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_64_EN_64_BIT 0

Definition at line 921 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_64_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_64_REG_OFFSET 0x1e4

Definition at line 919 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_64_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_64_REG_RESVAL 0x1u

Definition at line 920 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_65_EN_65_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_65_EN_65_BIT 0

Definition at line 926 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_65_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_65_REG_OFFSET 0x1e8

Definition at line 924 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_65_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_65_REG_RESVAL 0x1u

Definition at line 925 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_66_EN_66_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_66_EN_66_BIT 0

Definition at line 931 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_66_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_66_REG_OFFSET 0x1ec

Definition at line 929 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_66_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_66_REG_RESVAL 0x1u

Definition at line 930 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_67_EN_67_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_67_EN_67_BIT 0

Definition at line 936 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_67_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_67_REG_OFFSET 0x1f0

Definition at line 934 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_67_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_67_REG_RESVAL 0x1u

Definition at line 935 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_68_EN_68_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_68_EN_68_BIT 0

Definition at line 941 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_68_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_68_REG_OFFSET 0x1f4

Definition at line 939 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_68_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_68_REG_RESVAL 0x1u

Definition at line 940 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_69_EN_69_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_69_EN_69_BIT 0

Definition at line 946 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_69_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_69_REG_OFFSET 0x1f8

Definition at line 944 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_69_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_69_REG_RESVAL 0x1u

Definition at line 945 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_6_EN_6_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_6_EN_6_BIT 0

Definition at line 631 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_6_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_6_REG_OFFSET 0xfc

Definition at line 629 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_6_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_6_REG_RESVAL 0x1u

Definition at line 630 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_70_EN_70_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_70_EN_70_BIT 0

Definition at line 951 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_70_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_70_REG_OFFSET 0x1fc

Definition at line 949 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_70_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_70_REG_RESVAL 0x1u

Definition at line 950 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_71_EN_71_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_71_EN_71_BIT 0

Definition at line 956 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_71_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_71_REG_OFFSET 0x200

Definition at line 954 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_71_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_71_REG_RESVAL 0x1u

Definition at line 955 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_72_EN_72_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_72_EN_72_BIT 0

Definition at line 961 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_72_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_72_REG_OFFSET 0x204

Definition at line 959 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_72_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_72_REG_RESVAL 0x1u

Definition at line 960 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_7_EN_7_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_7_EN_7_BIT 0

Definition at line 636 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_7_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_7_REG_OFFSET 0x100

Definition at line 634 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_7_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_7_REG_RESVAL 0x1u

Definition at line 635 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_8_EN_8_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_8_EN_8_BIT 0

Definition at line 641 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_8_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_8_REG_OFFSET 0x104

Definition at line 639 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_8_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_8_REG_RESVAL 0x1u

Definition at line 640 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_9_EN_9_BIT

#define PINMUX_DIO_PAD_ATTR_REGWEN_9_EN_9_BIT 0

Definition at line 646 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_9_REG_OFFSET

#define PINMUX_DIO_PAD_ATTR_REGWEN_9_REG_OFFSET 0x108

Definition at line 644 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_9_REG_RESVAL

#define PINMUX_DIO_PAD_ATTR_REGWEN_9_REG_RESVAL 0x1u

Definition at line 645 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_EN_FIELD_WIDTH

#define PINMUX_DIO_PAD_ATTR_REGWEN_EN_FIELD_WIDTH 1

Definition at line 595 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_REGWEN_MULTIREG_COUNT

#define PINMUX_DIO_PAD_ATTR_REGWEN_MULTIREG_COUNT 73

Definition at line 596 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_SCHMITT_EN_FIELD_WIDTH

#define PINMUX_DIO_PAD_ATTR_SCHMITT_EN_FIELD_WIDTH 1

Definition at line 969 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_SLEW_RATE_FIELD_WIDTH

#define PINMUX_DIO_PAD_ATTR_SLEW_RATE_FIELD_WIDTH 2

Definition at line 972 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_ATTR_VIRTUAL_OD_EN_FIELD_WIDTH

#define PINMUX_DIO_PAD_ATTR_VIRTUAL_OD_EN_FIELD_WIDTH 1

Definition at line 965 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_0_EN_0_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_0_EN_0_BIT 0

Definition at line 3160 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_0_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_0_REG_OFFSET 0x4f0

Definition at line 3158 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_0_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_0_REG_RESVAL 0x0u

Definition at line 3159 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_10_EN_10_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_10_EN_10_BIT 0

Definition at line 3210 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_10_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_10_REG_OFFSET 0x518

Definition at line 3208 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_10_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_10_REG_RESVAL 0x0u

Definition at line 3209 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_11_EN_11_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_11_EN_11_BIT 0

Definition at line 3215 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_11_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_11_REG_OFFSET 0x51c

Definition at line 3213 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_11_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_11_REG_RESVAL 0x0u

Definition at line 3214 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_12_EN_12_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_12_EN_12_BIT 0

Definition at line 3220 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_12_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_12_REG_OFFSET 0x520

Definition at line 3218 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_12_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_12_REG_RESVAL 0x0u

Definition at line 3219 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_13_EN_13_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_13_EN_13_BIT 0

Definition at line 3225 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_13_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_13_REG_OFFSET 0x524

Definition at line 3223 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_13_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_13_REG_RESVAL 0x0u

Definition at line 3224 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_14_EN_14_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_14_EN_14_BIT 0

Definition at line 3230 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_14_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_14_REG_OFFSET 0x528

Definition at line 3228 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_14_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_14_REG_RESVAL 0x0u

Definition at line 3229 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_15_EN_15_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_15_EN_15_BIT 0

Definition at line 3235 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_15_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_15_REG_OFFSET 0x52c

Definition at line 3233 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_15_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_15_REG_RESVAL 0x0u

Definition at line 3234 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_16_EN_16_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_16_EN_16_BIT 0

Definition at line 3240 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_16_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_16_REG_OFFSET 0x530

Definition at line 3238 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_16_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_16_REG_RESVAL 0x0u

Definition at line 3239 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_17_EN_17_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_17_EN_17_BIT 0

Definition at line 3245 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_17_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_17_REG_OFFSET 0x534

Definition at line 3243 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_17_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_17_REG_RESVAL 0x0u

Definition at line 3244 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_18_EN_18_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_18_EN_18_BIT 0

Definition at line 3250 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_18_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_18_REG_OFFSET 0x538

Definition at line 3248 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_18_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_18_REG_RESVAL 0x0u

Definition at line 3249 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_19_EN_19_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_19_EN_19_BIT 0

Definition at line 3255 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_19_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_19_REG_OFFSET 0x53c

Definition at line 3253 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_19_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_19_REG_RESVAL 0x0u

Definition at line 3254 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_1_EN_1_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_1_EN_1_BIT 0

Definition at line 3165 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_1_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_1_REG_OFFSET 0x4f4

Definition at line 3163 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_1_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_1_REG_RESVAL 0x0u

Definition at line 3164 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_20_EN_20_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_20_EN_20_BIT 0

Definition at line 3260 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_20_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_20_REG_OFFSET 0x540

Definition at line 3258 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_20_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_20_REG_RESVAL 0x0u

Definition at line 3259 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_21_EN_21_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_21_EN_21_BIT 0

Definition at line 3265 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_21_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_21_REG_OFFSET 0x544

Definition at line 3263 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_21_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_21_REG_RESVAL 0x0u

Definition at line 3264 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_22_EN_22_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_22_EN_22_BIT 0

Definition at line 3270 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_22_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_22_REG_OFFSET 0x548

Definition at line 3268 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_22_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_22_REG_RESVAL 0x0u

Definition at line 3269 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_23_EN_23_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_23_EN_23_BIT 0

Definition at line 3275 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_23_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_23_REG_OFFSET 0x54c

Definition at line 3273 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_23_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_23_REG_RESVAL 0x0u

Definition at line 3274 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_24_EN_24_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_24_EN_24_BIT 0

Definition at line 3280 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_24_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_24_REG_OFFSET 0x550

Definition at line 3278 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_24_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_24_REG_RESVAL 0x0u

Definition at line 3279 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_25_EN_25_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_25_EN_25_BIT 0

Definition at line 3285 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_25_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_25_REG_OFFSET 0x554

Definition at line 3283 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_25_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_25_REG_RESVAL 0x0u

Definition at line 3284 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_26_EN_26_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_26_EN_26_BIT 0

Definition at line 3290 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_26_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_26_REG_OFFSET 0x558

Definition at line 3288 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_26_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_26_REG_RESVAL 0x0u

Definition at line 3289 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_27_EN_27_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_27_EN_27_BIT 0

Definition at line 3295 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_27_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_27_REG_OFFSET 0x55c

Definition at line 3293 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_27_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_27_REG_RESVAL 0x0u

Definition at line 3294 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_28_EN_28_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_28_EN_28_BIT 0

Definition at line 3300 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_28_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_28_REG_OFFSET 0x560

Definition at line 3298 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_28_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_28_REG_RESVAL 0x0u

Definition at line 3299 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_29_EN_29_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_29_EN_29_BIT 0

Definition at line 3305 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_29_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_29_REG_OFFSET 0x564

Definition at line 3303 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_29_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_29_REG_RESVAL 0x0u

Definition at line 3304 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_2_EN_2_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_2_EN_2_BIT 0

Definition at line 3170 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_2_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_2_REG_OFFSET 0x4f8

Definition at line 3168 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_2_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_2_REG_RESVAL 0x0u

Definition at line 3169 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_30_EN_30_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_30_EN_30_BIT 0

Definition at line 3310 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_30_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_30_REG_OFFSET 0x568

Definition at line 3308 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_30_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_30_REG_RESVAL 0x0u

Definition at line 3309 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_31_EN_31_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_31_EN_31_BIT 0

Definition at line 3315 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_31_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_31_REG_OFFSET 0x56c

Definition at line 3313 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_31_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_31_REG_RESVAL 0x0u

Definition at line 3314 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_32_EN_32_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_32_EN_32_BIT 0

Definition at line 3320 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_32_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_32_REG_OFFSET 0x570

Definition at line 3318 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_32_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_32_REG_RESVAL 0x0u

Definition at line 3319 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_33_EN_33_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_33_EN_33_BIT 0

Definition at line 3325 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_33_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_33_REG_OFFSET 0x574

Definition at line 3323 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_33_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_33_REG_RESVAL 0x0u

Definition at line 3324 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_34_EN_34_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_34_EN_34_BIT 0

Definition at line 3330 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_34_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_34_REG_OFFSET 0x578

Definition at line 3328 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_34_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_34_REG_RESVAL 0x0u

Definition at line 3329 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_35_EN_35_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_35_EN_35_BIT 0

Definition at line 3335 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_35_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_35_REG_OFFSET 0x57c

Definition at line 3333 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_35_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_35_REG_RESVAL 0x0u

Definition at line 3334 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_36_EN_36_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_36_EN_36_BIT 0

Definition at line 3340 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_36_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_36_REG_OFFSET 0x580

Definition at line 3338 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_36_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_36_REG_RESVAL 0x0u

Definition at line 3339 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_37_EN_37_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_37_EN_37_BIT 0

Definition at line 3345 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_37_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_37_REG_OFFSET 0x584

Definition at line 3343 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_37_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_37_REG_RESVAL 0x0u

Definition at line 3344 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_38_EN_38_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_38_EN_38_BIT 0

Definition at line 3350 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_38_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_38_REG_OFFSET 0x588

Definition at line 3348 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_38_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_38_REG_RESVAL 0x0u

Definition at line 3349 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_39_EN_39_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_39_EN_39_BIT 0

Definition at line 3355 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_39_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_39_REG_OFFSET 0x58c

Definition at line 3353 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_39_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_39_REG_RESVAL 0x0u

Definition at line 3354 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_3_EN_3_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_3_EN_3_BIT 0

Definition at line 3175 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_3_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_3_REG_OFFSET 0x4fc

Definition at line 3173 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_3_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_3_REG_RESVAL 0x0u

Definition at line 3174 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_40_EN_40_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_40_EN_40_BIT 0

Definition at line 3360 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_40_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_40_REG_OFFSET 0x590

Definition at line 3358 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_40_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_40_REG_RESVAL 0x0u

Definition at line 3359 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_41_EN_41_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_41_EN_41_BIT 0

Definition at line 3365 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_41_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_41_REG_OFFSET 0x594

Definition at line 3363 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_41_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_41_REG_RESVAL 0x0u

Definition at line 3364 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_42_EN_42_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_42_EN_42_BIT 0

Definition at line 3370 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_42_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_42_REG_OFFSET 0x598

Definition at line 3368 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_42_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_42_REG_RESVAL 0x0u

Definition at line 3369 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_43_EN_43_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_43_EN_43_BIT 0

Definition at line 3375 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_43_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_43_REG_OFFSET 0x59c

Definition at line 3373 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_43_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_43_REG_RESVAL 0x0u

Definition at line 3374 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_44_EN_44_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_44_EN_44_BIT 0

Definition at line 3380 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_44_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_44_REG_OFFSET 0x5a0

Definition at line 3378 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_44_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_44_REG_RESVAL 0x0u

Definition at line 3379 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_45_EN_45_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_45_EN_45_BIT 0

Definition at line 3385 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_45_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_45_REG_OFFSET 0x5a4

Definition at line 3383 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_45_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_45_REG_RESVAL 0x0u

Definition at line 3384 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_46_EN_46_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_46_EN_46_BIT 0

Definition at line 3390 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_46_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_46_REG_OFFSET 0x5a8

Definition at line 3388 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_46_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_46_REG_RESVAL 0x0u

Definition at line 3389 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_47_EN_47_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_47_EN_47_BIT 0

Definition at line 3395 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_47_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_47_REG_OFFSET 0x5ac

Definition at line 3393 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_47_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_47_REG_RESVAL 0x0u

Definition at line 3394 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_48_EN_48_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_48_EN_48_BIT 0

Definition at line 3400 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_48_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_48_REG_OFFSET 0x5b0

Definition at line 3398 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_48_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_48_REG_RESVAL 0x0u

Definition at line 3399 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_49_EN_49_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_49_EN_49_BIT 0

Definition at line 3405 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_49_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_49_REG_OFFSET 0x5b4

Definition at line 3403 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_49_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_49_REG_RESVAL 0x0u

Definition at line 3404 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_4_EN_4_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_4_EN_4_BIT 0

Definition at line 3180 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_4_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_4_REG_OFFSET 0x500

Definition at line 3178 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_4_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_4_REG_RESVAL 0x0u

Definition at line 3179 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_50_EN_50_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_50_EN_50_BIT 0

Definition at line 3410 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_50_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_50_REG_OFFSET 0x5b8

Definition at line 3408 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_50_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_50_REG_RESVAL 0x0u

Definition at line 3409 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_51_EN_51_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_51_EN_51_BIT 0

Definition at line 3415 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_51_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_51_REG_OFFSET 0x5bc

Definition at line 3413 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_51_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_51_REG_RESVAL 0x0u

Definition at line 3414 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_52_EN_52_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_52_EN_52_BIT 0

Definition at line 3420 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_52_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_52_REG_OFFSET 0x5c0

Definition at line 3418 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_52_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_52_REG_RESVAL 0x0u

Definition at line 3419 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_53_EN_53_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_53_EN_53_BIT 0

Definition at line 3425 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_53_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_53_REG_OFFSET 0x5c4

Definition at line 3423 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_53_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_53_REG_RESVAL 0x0u

Definition at line 3424 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_54_EN_54_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_54_EN_54_BIT 0

Definition at line 3430 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_54_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_54_REG_OFFSET 0x5c8

Definition at line 3428 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_54_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_54_REG_RESVAL 0x0u

Definition at line 3429 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_55_EN_55_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_55_EN_55_BIT 0

Definition at line 3435 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_55_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_55_REG_OFFSET 0x5cc

Definition at line 3433 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_55_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_55_REG_RESVAL 0x0u

Definition at line 3434 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_56_EN_56_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_56_EN_56_BIT 0

Definition at line 3440 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_56_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_56_REG_OFFSET 0x5d0

Definition at line 3438 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_56_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_56_REG_RESVAL 0x0u

Definition at line 3439 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_57_EN_57_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_57_EN_57_BIT 0

Definition at line 3445 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_57_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_57_REG_OFFSET 0x5d4

Definition at line 3443 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_57_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_57_REG_RESVAL 0x0u

Definition at line 3444 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_58_EN_58_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_58_EN_58_BIT 0

Definition at line 3450 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_58_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_58_REG_OFFSET 0x5d8

Definition at line 3448 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_58_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_58_REG_RESVAL 0x0u

Definition at line 3449 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_59_EN_59_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_59_EN_59_BIT 0

Definition at line 3455 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_59_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_59_REG_OFFSET 0x5dc

Definition at line 3453 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_59_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_59_REG_RESVAL 0x0u

Definition at line 3454 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_5_EN_5_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_5_EN_5_BIT 0

Definition at line 3185 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_5_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_5_REG_OFFSET 0x504

Definition at line 3183 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_5_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_5_REG_RESVAL 0x0u

Definition at line 3184 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_60_EN_60_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_60_EN_60_BIT 0

Definition at line 3460 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_60_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_60_REG_OFFSET 0x5e0

Definition at line 3458 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_60_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_60_REG_RESVAL 0x0u

Definition at line 3459 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_61_EN_61_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_61_EN_61_BIT 0

Definition at line 3465 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_61_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_61_REG_OFFSET 0x5e4

Definition at line 3463 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_61_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_61_REG_RESVAL 0x0u

Definition at line 3464 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_62_EN_62_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_62_EN_62_BIT 0

Definition at line 3470 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_62_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_62_REG_OFFSET 0x5e8

Definition at line 3468 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_62_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_62_REG_RESVAL 0x0u

Definition at line 3469 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_63_EN_63_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_63_EN_63_BIT 0

Definition at line 3475 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_63_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_63_REG_OFFSET 0x5ec

Definition at line 3473 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_63_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_63_REG_RESVAL 0x0u

Definition at line 3474 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_64_EN_64_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_64_EN_64_BIT 0

Definition at line 3480 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_64_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_64_REG_OFFSET 0x5f0

Definition at line 3478 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_64_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_64_REG_RESVAL 0x0u

Definition at line 3479 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_65_EN_65_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_65_EN_65_BIT 0

Definition at line 3485 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_65_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_65_REG_OFFSET 0x5f4

Definition at line 3483 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_65_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_65_REG_RESVAL 0x0u

Definition at line 3484 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_66_EN_66_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_66_EN_66_BIT 0

Definition at line 3490 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_66_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_66_REG_OFFSET 0x5f8

Definition at line 3488 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_66_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_66_REG_RESVAL 0x0u

Definition at line 3489 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_67_EN_67_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_67_EN_67_BIT 0

Definition at line 3495 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_67_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_67_REG_OFFSET 0x5fc

Definition at line 3493 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_67_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_67_REG_RESVAL 0x0u

Definition at line 3494 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_68_EN_68_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_68_EN_68_BIT 0

Definition at line 3500 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_68_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_68_REG_OFFSET 0x600

Definition at line 3498 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_68_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_68_REG_RESVAL 0x0u

Definition at line 3499 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_69_EN_69_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_69_EN_69_BIT 0

Definition at line 3505 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_69_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_69_REG_OFFSET 0x604

Definition at line 3503 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_69_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_69_REG_RESVAL 0x0u

Definition at line 3504 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_6_EN_6_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_6_EN_6_BIT 0

Definition at line 3190 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_6_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_6_REG_OFFSET 0x508

Definition at line 3188 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_6_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_6_REG_RESVAL 0x0u

Definition at line 3189 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_70_EN_70_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_70_EN_70_BIT 0

Definition at line 3510 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_70_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_70_REG_OFFSET 0x608

Definition at line 3508 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_70_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_70_REG_RESVAL 0x0u

Definition at line 3509 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_71_EN_71_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_71_EN_71_BIT 0

Definition at line 3515 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_71_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_71_REG_OFFSET 0x60c

Definition at line 3513 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_71_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_71_REG_RESVAL 0x0u

Definition at line 3514 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_72_EN_72_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_72_EN_72_BIT 0

Definition at line 3520 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_72_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_72_REG_OFFSET 0x610

Definition at line 3518 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_72_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_72_REG_RESVAL 0x0u

Definition at line 3519 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_7_EN_7_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_7_EN_7_BIT 0

Definition at line 3195 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_7_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_7_REG_OFFSET 0x50c

Definition at line 3193 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_7_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_7_REG_RESVAL 0x0u

Definition at line 3194 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_8_EN_8_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_8_EN_8_BIT 0

Definition at line 3200 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_8_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_8_REG_OFFSET 0x510

Definition at line 3198 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_8_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_8_REG_RESVAL 0x0u

Definition at line 3199 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_9_EN_9_BIT

#define PINMUX_DIO_PAD_SLEEP_EN_9_EN_9_BIT 0

Definition at line 3205 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_9_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_EN_9_REG_OFFSET 0x514

Definition at line 3203 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_9_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_EN_9_REG_RESVAL 0x0u

Definition at line 3204 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_EN_FIELD_WIDTH

#define PINMUX_DIO_PAD_SLEEP_EN_EN_FIELD_WIDTH 1

Definition at line 3154 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_EN_MULTIREG_COUNT

#define PINMUX_DIO_PAD_SLEEP_EN_MULTIREG_COUNT 73

Definition at line 3155 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_OFFSET })

Definition at line 3532 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_MASK 0x3u

Definition at line 3530 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_OFFSET 0

Definition at line 3531 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_HIGH_Z

#define PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_HIGH_Z 0x2

Definition at line 3536 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_KEEP

#define PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_KEEP 0x3

Definition at line 3537 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_TIE_HIGH

#define PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_TIE_HIGH 0x1

Definition at line 3535 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_TIE_LOW

#define PINMUX_DIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_TIE_LOW 0x0

Definition at line 3534 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_0_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_0_REG_OFFSET 0x614

Definition at line 3528 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_0_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_0_REG_RESVAL 0x2u

Definition at line 3529 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_10_OUT_10_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_10_OUT_10_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_10_OUT_10_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_10_OUT_10_OFFSET })

Definition at line 3616 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_10_OUT_10_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_10_OUT_10_MASK 0x3u

Definition at line 3614 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_10_OUT_10_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_10_OUT_10_OFFSET 0

Definition at line 3615 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_10_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_10_REG_OFFSET 0x63c

Definition at line 3612 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_10_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_10_REG_RESVAL 0x2u

Definition at line 3613 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_11_OUT_11_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_11_OUT_11_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_11_OUT_11_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_11_OUT_11_OFFSET })

Definition at line 3624 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_11_OUT_11_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_11_OUT_11_MASK 0x3u

Definition at line 3622 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_11_OUT_11_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_11_OUT_11_OFFSET 0

Definition at line 3623 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_11_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_11_REG_OFFSET 0x640

Definition at line 3620 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_11_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_11_REG_RESVAL 0x2u

Definition at line 3621 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_12_OUT_12_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_12_OUT_12_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_12_OUT_12_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_12_OUT_12_OFFSET })

Definition at line 3632 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_12_OUT_12_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_12_OUT_12_MASK 0x3u

Definition at line 3630 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_12_OUT_12_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_12_OUT_12_OFFSET 0

Definition at line 3631 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_12_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_12_REG_OFFSET 0x644

Definition at line 3628 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_12_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_12_REG_RESVAL 0x2u

Definition at line 3629 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_13_OUT_13_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_13_OUT_13_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_13_OUT_13_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_13_OUT_13_OFFSET })

Definition at line 3640 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_13_OUT_13_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_13_OUT_13_MASK 0x3u

Definition at line 3638 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_13_OUT_13_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_13_OUT_13_OFFSET 0

Definition at line 3639 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_13_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_13_REG_OFFSET 0x648

Definition at line 3636 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_13_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_13_REG_RESVAL 0x2u

Definition at line 3637 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_14_OUT_14_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_14_OUT_14_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_14_OUT_14_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_14_OUT_14_OFFSET })

Definition at line 3648 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_14_OUT_14_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_14_OUT_14_MASK 0x3u

Definition at line 3646 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_14_OUT_14_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_14_OUT_14_OFFSET 0

Definition at line 3647 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_14_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_14_REG_OFFSET 0x64c

Definition at line 3644 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_14_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_14_REG_RESVAL 0x2u

Definition at line 3645 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_15_OUT_15_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_15_OUT_15_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_15_OUT_15_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_15_OUT_15_OFFSET })

Definition at line 3656 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_15_OUT_15_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_15_OUT_15_MASK 0x3u

Definition at line 3654 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_15_OUT_15_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_15_OUT_15_OFFSET 0

Definition at line 3655 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_15_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_15_REG_OFFSET 0x650

Definition at line 3652 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_15_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_15_REG_RESVAL 0x2u

Definition at line 3653 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_16_OUT_16_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_16_OUT_16_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_16_OUT_16_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_16_OUT_16_OFFSET })

Definition at line 3664 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_16_OUT_16_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_16_OUT_16_MASK 0x3u

Definition at line 3662 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_16_OUT_16_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_16_OUT_16_OFFSET 0

Definition at line 3663 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_16_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_16_REG_OFFSET 0x654

Definition at line 3660 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_16_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_16_REG_RESVAL 0x2u

Definition at line 3661 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_17_OUT_17_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_17_OUT_17_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_17_OUT_17_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_17_OUT_17_OFFSET })

Definition at line 3672 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_17_OUT_17_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_17_OUT_17_MASK 0x3u

Definition at line 3670 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_17_OUT_17_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_17_OUT_17_OFFSET 0

Definition at line 3671 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_17_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_17_REG_OFFSET 0x658

Definition at line 3668 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_17_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_17_REG_RESVAL 0x2u

Definition at line 3669 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_18_OUT_18_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_18_OUT_18_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_18_OUT_18_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_18_OUT_18_OFFSET })

Definition at line 3680 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_18_OUT_18_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_18_OUT_18_MASK 0x3u

Definition at line 3678 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_18_OUT_18_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_18_OUT_18_OFFSET 0

Definition at line 3679 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_18_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_18_REG_OFFSET 0x65c

Definition at line 3676 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_18_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_18_REG_RESVAL 0x2u

Definition at line 3677 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_19_OUT_19_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_19_OUT_19_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_19_OUT_19_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_19_OUT_19_OFFSET })

Definition at line 3688 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_19_OUT_19_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_19_OUT_19_MASK 0x3u

Definition at line 3686 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_19_OUT_19_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_19_OUT_19_OFFSET 0

Definition at line 3687 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_19_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_19_REG_OFFSET 0x660

Definition at line 3684 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_19_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_19_REG_RESVAL 0x2u

Definition at line 3685 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_1_OUT_1_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_1_OUT_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_1_OUT_1_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_1_OUT_1_OFFSET })

Definition at line 3544 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_1_OUT_1_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_1_OUT_1_MASK 0x3u

Definition at line 3542 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_1_OUT_1_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_1_OUT_1_OFFSET 0

Definition at line 3543 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_1_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_1_REG_OFFSET 0x618

Definition at line 3540 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_1_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_1_REG_RESVAL 0x2u

Definition at line 3541 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_20_OUT_20_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_20_OUT_20_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_20_OUT_20_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_20_OUT_20_OFFSET })

Definition at line 3696 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_20_OUT_20_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_20_OUT_20_MASK 0x3u

Definition at line 3694 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_20_OUT_20_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_20_OUT_20_OFFSET 0

Definition at line 3695 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_20_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_20_REG_OFFSET 0x664

Definition at line 3692 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_20_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_20_REG_RESVAL 0x2u

Definition at line 3693 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_21_OUT_21_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_21_OUT_21_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_21_OUT_21_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_21_OUT_21_OFFSET })

Definition at line 3704 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_21_OUT_21_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_21_OUT_21_MASK 0x3u

Definition at line 3702 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_21_OUT_21_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_21_OUT_21_OFFSET 0

Definition at line 3703 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_21_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_21_REG_OFFSET 0x668

Definition at line 3700 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_21_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_21_REG_RESVAL 0x2u

Definition at line 3701 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_22_OUT_22_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_22_OUT_22_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_22_OUT_22_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_22_OUT_22_OFFSET })

Definition at line 3712 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_22_OUT_22_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_22_OUT_22_MASK 0x3u

Definition at line 3710 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_22_OUT_22_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_22_OUT_22_OFFSET 0

Definition at line 3711 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_22_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_22_REG_OFFSET 0x66c

Definition at line 3708 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_22_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_22_REG_RESVAL 0x2u

Definition at line 3709 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_23_OUT_23_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_23_OUT_23_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_23_OUT_23_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_23_OUT_23_OFFSET })

Definition at line 3720 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_23_OUT_23_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_23_OUT_23_MASK 0x3u

Definition at line 3718 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_23_OUT_23_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_23_OUT_23_OFFSET 0

Definition at line 3719 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_23_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_23_REG_OFFSET 0x670

Definition at line 3716 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_23_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_23_REG_RESVAL 0x2u

Definition at line 3717 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_24_OUT_24_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_24_OUT_24_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_24_OUT_24_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_24_OUT_24_OFFSET })

Definition at line 3728 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_24_OUT_24_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_24_OUT_24_MASK 0x3u

Definition at line 3726 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_24_OUT_24_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_24_OUT_24_OFFSET 0

Definition at line 3727 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_24_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_24_REG_OFFSET 0x674

Definition at line 3724 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_24_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_24_REG_RESVAL 0x2u

Definition at line 3725 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_25_OUT_25_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_25_OUT_25_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_25_OUT_25_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_25_OUT_25_OFFSET })

Definition at line 3736 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_25_OUT_25_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_25_OUT_25_MASK 0x3u

Definition at line 3734 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_25_OUT_25_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_25_OUT_25_OFFSET 0

Definition at line 3735 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_25_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_25_REG_OFFSET 0x678

Definition at line 3732 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_25_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_25_REG_RESVAL 0x2u

Definition at line 3733 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_26_OUT_26_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_26_OUT_26_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_26_OUT_26_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_26_OUT_26_OFFSET })

Definition at line 3744 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_26_OUT_26_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_26_OUT_26_MASK 0x3u

Definition at line 3742 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_26_OUT_26_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_26_OUT_26_OFFSET 0

Definition at line 3743 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_26_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_26_REG_OFFSET 0x67c

Definition at line 3740 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_26_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_26_REG_RESVAL 0x2u

Definition at line 3741 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_27_OUT_27_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_27_OUT_27_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_27_OUT_27_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_27_OUT_27_OFFSET })

Definition at line 3752 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_27_OUT_27_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_27_OUT_27_MASK 0x3u

Definition at line 3750 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_27_OUT_27_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_27_OUT_27_OFFSET 0

Definition at line 3751 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_27_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_27_REG_OFFSET 0x680

Definition at line 3748 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_27_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_27_REG_RESVAL 0x2u

Definition at line 3749 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_28_OUT_28_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_28_OUT_28_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_28_OUT_28_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_28_OUT_28_OFFSET })

Definition at line 3760 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_28_OUT_28_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_28_OUT_28_MASK 0x3u

Definition at line 3758 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_28_OUT_28_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_28_OUT_28_OFFSET 0

Definition at line 3759 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_28_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_28_REG_OFFSET 0x684

Definition at line 3756 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_28_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_28_REG_RESVAL 0x2u

Definition at line 3757 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_29_OUT_29_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_29_OUT_29_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_29_OUT_29_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_29_OUT_29_OFFSET })

Definition at line 3768 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_29_OUT_29_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_29_OUT_29_MASK 0x3u

Definition at line 3766 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_29_OUT_29_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_29_OUT_29_OFFSET 0

Definition at line 3767 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_29_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_29_REG_OFFSET 0x688

Definition at line 3764 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_29_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_29_REG_RESVAL 0x2u

Definition at line 3765 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_2_OUT_2_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_2_OUT_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_2_OUT_2_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_2_OUT_2_OFFSET })

Definition at line 3552 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_2_OUT_2_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_2_OUT_2_MASK 0x3u

Definition at line 3550 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_2_OUT_2_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_2_OUT_2_OFFSET 0

Definition at line 3551 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_2_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_2_REG_OFFSET 0x61c

Definition at line 3548 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_2_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_2_REG_RESVAL 0x2u

Definition at line 3549 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_30_OUT_30_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_30_OUT_30_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_30_OUT_30_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_30_OUT_30_OFFSET })

Definition at line 3776 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_30_OUT_30_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_30_OUT_30_MASK 0x3u

Definition at line 3774 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_30_OUT_30_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_30_OUT_30_OFFSET 0

Definition at line 3775 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_30_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_30_REG_OFFSET 0x68c

Definition at line 3772 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_30_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_30_REG_RESVAL 0x2u

Definition at line 3773 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_31_OUT_31_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_31_OUT_31_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_31_OUT_31_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_31_OUT_31_OFFSET })

Definition at line 3784 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_31_OUT_31_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_31_OUT_31_MASK 0x3u

Definition at line 3782 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_31_OUT_31_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_31_OUT_31_OFFSET 0

Definition at line 3783 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_31_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_31_REG_OFFSET 0x690

Definition at line 3780 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_31_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_31_REG_RESVAL 0x2u

Definition at line 3781 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_32_OUT_32_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_32_OUT_32_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_32_OUT_32_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_32_OUT_32_OFFSET })

Definition at line 3792 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_32_OUT_32_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_32_OUT_32_MASK 0x3u

Definition at line 3790 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_32_OUT_32_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_32_OUT_32_OFFSET 0

Definition at line 3791 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_32_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_32_REG_OFFSET 0x694

Definition at line 3788 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_32_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_32_REG_RESVAL 0x2u

Definition at line 3789 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_33_OUT_33_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_33_OUT_33_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_33_OUT_33_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_33_OUT_33_OFFSET })

Definition at line 3800 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_33_OUT_33_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_33_OUT_33_MASK 0x3u

Definition at line 3798 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_33_OUT_33_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_33_OUT_33_OFFSET 0

Definition at line 3799 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_33_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_33_REG_OFFSET 0x698

Definition at line 3796 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_33_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_33_REG_RESVAL 0x2u

Definition at line 3797 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_34_OUT_34_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_34_OUT_34_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_34_OUT_34_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_34_OUT_34_OFFSET })

Definition at line 3808 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_34_OUT_34_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_34_OUT_34_MASK 0x3u

Definition at line 3806 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_34_OUT_34_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_34_OUT_34_OFFSET 0

Definition at line 3807 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_34_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_34_REG_OFFSET 0x69c

Definition at line 3804 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_34_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_34_REG_RESVAL 0x2u

Definition at line 3805 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_35_OUT_35_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_35_OUT_35_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_35_OUT_35_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_35_OUT_35_OFFSET })

Definition at line 3816 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_35_OUT_35_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_35_OUT_35_MASK 0x3u

Definition at line 3814 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_35_OUT_35_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_35_OUT_35_OFFSET 0

Definition at line 3815 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_35_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_35_REG_OFFSET 0x6a0

Definition at line 3812 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_35_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_35_REG_RESVAL 0x2u

Definition at line 3813 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_36_OUT_36_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_36_OUT_36_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_36_OUT_36_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_36_OUT_36_OFFSET })

Definition at line 3824 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_36_OUT_36_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_36_OUT_36_MASK 0x3u

Definition at line 3822 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_36_OUT_36_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_36_OUT_36_OFFSET 0

Definition at line 3823 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_36_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_36_REG_OFFSET 0x6a4

Definition at line 3820 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_36_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_36_REG_RESVAL 0x2u

Definition at line 3821 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_37_OUT_37_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_37_OUT_37_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_37_OUT_37_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_37_OUT_37_OFFSET })

Definition at line 3832 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_37_OUT_37_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_37_OUT_37_MASK 0x3u

Definition at line 3830 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_37_OUT_37_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_37_OUT_37_OFFSET 0

Definition at line 3831 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_37_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_37_REG_OFFSET 0x6a8

Definition at line 3828 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_37_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_37_REG_RESVAL 0x2u

Definition at line 3829 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_38_OUT_38_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_38_OUT_38_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_38_OUT_38_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_38_OUT_38_OFFSET })

Definition at line 3840 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_38_OUT_38_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_38_OUT_38_MASK 0x3u

Definition at line 3838 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_38_OUT_38_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_38_OUT_38_OFFSET 0

Definition at line 3839 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_38_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_38_REG_OFFSET 0x6ac

Definition at line 3836 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_38_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_38_REG_RESVAL 0x2u

Definition at line 3837 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_39_OUT_39_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_39_OUT_39_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_39_OUT_39_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_39_OUT_39_OFFSET })

Definition at line 3848 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_39_OUT_39_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_39_OUT_39_MASK 0x3u

Definition at line 3846 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_39_OUT_39_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_39_OUT_39_OFFSET 0

Definition at line 3847 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_39_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_39_REG_OFFSET 0x6b0

Definition at line 3844 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_39_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_39_REG_RESVAL 0x2u

Definition at line 3845 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_3_OUT_3_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_3_OUT_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_3_OUT_3_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_3_OUT_3_OFFSET })

Definition at line 3560 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_3_OUT_3_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_3_OUT_3_MASK 0x3u

Definition at line 3558 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_3_OUT_3_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_3_OUT_3_OFFSET 0

Definition at line 3559 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_3_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_3_REG_OFFSET 0x620

Definition at line 3556 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_3_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_3_REG_RESVAL 0x2u

Definition at line 3557 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_40_OUT_40_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_40_OUT_40_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_40_OUT_40_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_40_OUT_40_OFFSET })

Definition at line 3856 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_40_OUT_40_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_40_OUT_40_MASK 0x3u

Definition at line 3854 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_40_OUT_40_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_40_OUT_40_OFFSET 0

Definition at line 3855 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_40_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_40_REG_OFFSET 0x6b4

Definition at line 3852 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_40_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_40_REG_RESVAL 0x2u

Definition at line 3853 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_41_OUT_41_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_41_OUT_41_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_41_OUT_41_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_41_OUT_41_OFFSET })

Definition at line 3864 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_41_OUT_41_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_41_OUT_41_MASK 0x3u

Definition at line 3862 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_41_OUT_41_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_41_OUT_41_OFFSET 0

Definition at line 3863 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_41_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_41_REG_OFFSET 0x6b8

Definition at line 3860 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_41_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_41_REG_RESVAL 0x2u

Definition at line 3861 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_42_OUT_42_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_42_OUT_42_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_42_OUT_42_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_42_OUT_42_OFFSET })

Definition at line 3872 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_42_OUT_42_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_42_OUT_42_MASK 0x3u

Definition at line 3870 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_42_OUT_42_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_42_OUT_42_OFFSET 0

Definition at line 3871 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_42_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_42_REG_OFFSET 0x6bc

Definition at line 3868 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_42_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_42_REG_RESVAL 0x2u

Definition at line 3869 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_43_OUT_43_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_43_OUT_43_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_43_OUT_43_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_43_OUT_43_OFFSET })

Definition at line 3880 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_43_OUT_43_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_43_OUT_43_MASK 0x3u

Definition at line 3878 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_43_OUT_43_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_43_OUT_43_OFFSET 0

Definition at line 3879 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_43_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_43_REG_OFFSET 0x6c0

Definition at line 3876 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_43_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_43_REG_RESVAL 0x2u

Definition at line 3877 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_44_OUT_44_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_44_OUT_44_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_44_OUT_44_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_44_OUT_44_OFFSET })

Definition at line 3888 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_44_OUT_44_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_44_OUT_44_MASK 0x3u

Definition at line 3886 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_44_OUT_44_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_44_OUT_44_OFFSET 0

Definition at line 3887 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_44_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_44_REG_OFFSET 0x6c4

Definition at line 3884 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_44_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_44_REG_RESVAL 0x2u

Definition at line 3885 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_45_OUT_45_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_45_OUT_45_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_45_OUT_45_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_45_OUT_45_OFFSET })

Definition at line 3896 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_45_OUT_45_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_45_OUT_45_MASK 0x3u

Definition at line 3894 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_45_OUT_45_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_45_OUT_45_OFFSET 0

Definition at line 3895 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_45_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_45_REG_OFFSET 0x6c8

Definition at line 3892 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_45_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_45_REG_RESVAL 0x2u

Definition at line 3893 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_46_OUT_46_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_46_OUT_46_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_46_OUT_46_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_46_OUT_46_OFFSET })

Definition at line 3904 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_46_OUT_46_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_46_OUT_46_MASK 0x3u

Definition at line 3902 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_46_OUT_46_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_46_OUT_46_OFFSET 0

Definition at line 3903 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_46_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_46_REG_OFFSET 0x6cc

Definition at line 3900 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_46_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_46_REG_RESVAL 0x2u

Definition at line 3901 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_47_OUT_47_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_47_OUT_47_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_47_OUT_47_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_47_OUT_47_OFFSET })

Definition at line 3912 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_47_OUT_47_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_47_OUT_47_MASK 0x3u

Definition at line 3910 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_47_OUT_47_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_47_OUT_47_OFFSET 0

Definition at line 3911 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_47_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_47_REG_OFFSET 0x6d0

Definition at line 3908 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_47_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_47_REG_RESVAL 0x2u

Definition at line 3909 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_48_OUT_48_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_48_OUT_48_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_48_OUT_48_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_48_OUT_48_OFFSET })

Definition at line 3920 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_48_OUT_48_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_48_OUT_48_MASK 0x3u

Definition at line 3918 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_48_OUT_48_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_48_OUT_48_OFFSET 0

Definition at line 3919 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_48_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_48_REG_OFFSET 0x6d4

Definition at line 3916 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_48_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_48_REG_RESVAL 0x2u

Definition at line 3917 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_49_OUT_49_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_49_OUT_49_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_49_OUT_49_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_49_OUT_49_OFFSET })

Definition at line 3928 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_49_OUT_49_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_49_OUT_49_MASK 0x3u

Definition at line 3926 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_49_OUT_49_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_49_OUT_49_OFFSET 0

Definition at line 3927 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_49_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_49_REG_OFFSET 0x6d8

Definition at line 3924 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_49_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_49_REG_RESVAL 0x2u

Definition at line 3925 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_4_OUT_4_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_4_OUT_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_4_OUT_4_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_4_OUT_4_OFFSET })

Definition at line 3568 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_4_OUT_4_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_4_OUT_4_MASK 0x3u

Definition at line 3566 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_4_OUT_4_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_4_OUT_4_OFFSET 0

Definition at line 3567 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_4_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_4_REG_OFFSET 0x624

Definition at line 3564 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_4_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_4_REG_RESVAL 0x2u

Definition at line 3565 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_50_OUT_50_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_50_OUT_50_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_50_OUT_50_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_50_OUT_50_OFFSET })

Definition at line 3936 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_50_OUT_50_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_50_OUT_50_MASK 0x3u

Definition at line 3934 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_50_OUT_50_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_50_OUT_50_OFFSET 0

Definition at line 3935 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_50_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_50_REG_OFFSET 0x6dc

Definition at line 3932 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_50_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_50_REG_RESVAL 0x2u

Definition at line 3933 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_51_OUT_51_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_51_OUT_51_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_51_OUT_51_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_51_OUT_51_OFFSET })

Definition at line 3944 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_51_OUT_51_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_51_OUT_51_MASK 0x3u

Definition at line 3942 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_51_OUT_51_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_51_OUT_51_OFFSET 0

Definition at line 3943 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_51_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_51_REG_OFFSET 0x6e0

Definition at line 3940 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_51_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_51_REG_RESVAL 0x2u

Definition at line 3941 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_52_OUT_52_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_52_OUT_52_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_52_OUT_52_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_52_OUT_52_OFFSET })

Definition at line 3952 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_52_OUT_52_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_52_OUT_52_MASK 0x3u

Definition at line 3950 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_52_OUT_52_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_52_OUT_52_OFFSET 0

Definition at line 3951 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_52_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_52_REG_OFFSET 0x6e4

Definition at line 3948 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_52_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_52_REG_RESVAL 0x2u

Definition at line 3949 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_53_OUT_53_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_53_OUT_53_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_53_OUT_53_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_53_OUT_53_OFFSET })

Definition at line 3960 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_53_OUT_53_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_53_OUT_53_MASK 0x3u

Definition at line 3958 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_53_OUT_53_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_53_OUT_53_OFFSET 0

Definition at line 3959 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_53_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_53_REG_OFFSET 0x6e8

Definition at line 3956 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_53_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_53_REG_RESVAL 0x2u

Definition at line 3957 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_54_OUT_54_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_54_OUT_54_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_54_OUT_54_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_54_OUT_54_OFFSET })

Definition at line 3968 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_54_OUT_54_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_54_OUT_54_MASK 0x3u

Definition at line 3966 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_54_OUT_54_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_54_OUT_54_OFFSET 0

Definition at line 3967 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_54_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_54_REG_OFFSET 0x6ec

Definition at line 3964 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_54_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_54_REG_RESVAL 0x2u

Definition at line 3965 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_55_OUT_55_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_55_OUT_55_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_55_OUT_55_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_55_OUT_55_OFFSET })

Definition at line 3976 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_55_OUT_55_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_55_OUT_55_MASK 0x3u

Definition at line 3974 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_55_OUT_55_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_55_OUT_55_OFFSET 0

Definition at line 3975 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_55_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_55_REG_OFFSET 0x6f0

Definition at line 3972 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_55_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_55_REG_RESVAL 0x2u

Definition at line 3973 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_56_OUT_56_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_56_OUT_56_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_56_OUT_56_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_56_OUT_56_OFFSET })

Definition at line 3984 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_56_OUT_56_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_56_OUT_56_MASK 0x3u

Definition at line 3982 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_56_OUT_56_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_56_OUT_56_OFFSET 0

Definition at line 3983 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_56_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_56_REG_OFFSET 0x6f4

Definition at line 3980 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_56_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_56_REG_RESVAL 0x2u

Definition at line 3981 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_57_OUT_57_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_57_OUT_57_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_57_OUT_57_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_57_OUT_57_OFFSET })

Definition at line 3992 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_57_OUT_57_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_57_OUT_57_MASK 0x3u

Definition at line 3990 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_57_OUT_57_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_57_OUT_57_OFFSET 0

Definition at line 3991 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_57_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_57_REG_OFFSET 0x6f8

Definition at line 3988 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_57_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_57_REG_RESVAL 0x2u

Definition at line 3989 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_58_OUT_58_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_58_OUT_58_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_58_OUT_58_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_58_OUT_58_OFFSET })

Definition at line 4000 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_58_OUT_58_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_58_OUT_58_MASK 0x3u

Definition at line 3998 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_58_OUT_58_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_58_OUT_58_OFFSET 0

Definition at line 3999 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_58_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_58_REG_OFFSET 0x6fc

Definition at line 3996 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_58_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_58_REG_RESVAL 0x2u

Definition at line 3997 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_59_OUT_59_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_59_OUT_59_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_59_OUT_59_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_59_OUT_59_OFFSET })

Definition at line 4008 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_59_OUT_59_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_59_OUT_59_MASK 0x3u

Definition at line 4006 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_59_OUT_59_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_59_OUT_59_OFFSET 0

Definition at line 4007 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_59_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_59_REG_OFFSET 0x700

Definition at line 4004 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_59_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_59_REG_RESVAL 0x2u

Definition at line 4005 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_5_OUT_5_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_5_OUT_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_5_OUT_5_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_5_OUT_5_OFFSET })

Definition at line 3576 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_5_OUT_5_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_5_OUT_5_MASK 0x3u

Definition at line 3574 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_5_OUT_5_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_5_OUT_5_OFFSET 0

Definition at line 3575 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_5_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_5_REG_OFFSET 0x628

Definition at line 3572 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_5_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_5_REG_RESVAL 0x2u

Definition at line 3573 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_60_OUT_60_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_60_OUT_60_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_60_OUT_60_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_60_OUT_60_OFFSET })

Definition at line 4016 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_60_OUT_60_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_60_OUT_60_MASK 0x3u

Definition at line 4014 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_60_OUT_60_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_60_OUT_60_OFFSET 0

Definition at line 4015 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_60_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_60_REG_OFFSET 0x704

Definition at line 4012 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_60_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_60_REG_RESVAL 0x2u

Definition at line 4013 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_61_OUT_61_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_61_OUT_61_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_61_OUT_61_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_61_OUT_61_OFFSET })

Definition at line 4024 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_61_OUT_61_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_61_OUT_61_MASK 0x3u

Definition at line 4022 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_61_OUT_61_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_61_OUT_61_OFFSET 0

Definition at line 4023 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_61_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_61_REG_OFFSET 0x708

Definition at line 4020 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_61_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_61_REG_RESVAL 0x2u

Definition at line 4021 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_62_OUT_62_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_62_OUT_62_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_62_OUT_62_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_62_OUT_62_OFFSET })

Definition at line 4032 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_62_OUT_62_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_62_OUT_62_MASK 0x3u

Definition at line 4030 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_62_OUT_62_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_62_OUT_62_OFFSET 0

Definition at line 4031 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_62_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_62_REG_OFFSET 0x70c

Definition at line 4028 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_62_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_62_REG_RESVAL 0x2u

Definition at line 4029 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_63_OUT_63_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_63_OUT_63_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_63_OUT_63_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_63_OUT_63_OFFSET })

Definition at line 4040 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_63_OUT_63_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_63_OUT_63_MASK 0x3u

Definition at line 4038 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_63_OUT_63_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_63_OUT_63_OFFSET 0

Definition at line 4039 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_63_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_63_REG_OFFSET 0x710

Definition at line 4036 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_63_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_63_REG_RESVAL 0x2u

Definition at line 4037 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_64_OUT_64_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_64_OUT_64_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_64_OUT_64_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_64_OUT_64_OFFSET })

Definition at line 4048 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_64_OUT_64_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_64_OUT_64_MASK 0x3u

Definition at line 4046 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_64_OUT_64_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_64_OUT_64_OFFSET 0

Definition at line 4047 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_64_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_64_REG_OFFSET 0x714

Definition at line 4044 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_64_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_64_REG_RESVAL 0x2u

Definition at line 4045 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_65_OUT_65_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_65_OUT_65_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_65_OUT_65_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_65_OUT_65_OFFSET })

Definition at line 4056 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_65_OUT_65_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_65_OUT_65_MASK 0x3u

Definition at line 4054 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_65_OUT_65_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_65_OUT_65_OFFSET 0

Definition at line 4055 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_65_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_65_REG_OFFSET 0x718

Definition at line 4052 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_65_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_65_REG_RESVAL 0x2u

Definition at line 4053 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_66_OUT_66_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_66_OUT_66_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_66_OUT_66_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_66_OUT_66_OFFSET })

Definition at line 4064 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_66_OUT_66_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_66_OUT_66_MASK 0x3u

Definition at line 4062 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_66_OUT_66_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_66_OUT_66_OFFSET 0

Definition at line 4063 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_66_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_66_REG_OFFSET 0x71c

Definition at line 4060 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_66_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_66_REG_RESVAL 0x2u

Definition at line 4061 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_67_OUT_67_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_67_OUT_67_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_67_OUT_67_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_67_OUT_67_OFFSET })

Definition at line 4072 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_67_OUT_67_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_67_OUT_67_MASK 0x3u

Definition at line 4070 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_67_OUT_67_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_67_OUT_67_OFFSET 0

Definition at line 4071 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_67_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_67_REG_OFFSET 0x720

Definition at line 4068 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_67_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_67_REG_RESVAL 0x2u

Definition at line 4069 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_68_OUT_68_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_68_OUT_68_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_68_OUT_68_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_68_OUT_68_OFFSET })

Definition at line 4080 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_68_OUT_68_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_68_OUT_68_MASK 0x3u

Definition at line 4078 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_68_OUT_68_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_68_OUT_68_OFFSET 0

Definition at line 4079 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_68_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_68_REG_OFFSET 0x724

Definition at line 4076 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_68_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_68_REG_RESVAL 0x2u

Definition at line 4077 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_69_OUT_69_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_69_OUT_69_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_69_OUT_69_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_69_OUT_69_OFFSET })

Definition at line 4088 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_69_OUT_69_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_69_OUT_69_MASK 0x3u

Definition at line 4086 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_69_OUT_69_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_69_OUT_69_OFFSET 0

Definition at line 4087 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_69_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_69_REG_OFFSET 0x728

Definition at line 4084 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_69_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_69_REG_RESVAL 0x2u

Definition at line 4085 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_6_OUT_6_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_6_OUT_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_6_OUT_6_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_6_OUT_6_OFFSET })

Definition at line 3584 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_6_OUT_6_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_6_OUT_6_MASK 0x3u

Definition at line 3582 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_6_OUT_6_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_6_OUT_6_OFFSET 0

Definition at line 3583 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_6_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_6_REG_OFFSET 0x62c

Definition at line 3580 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_6_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_6_REG_RESVAL 0x2u

Definition at line 3581 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_70_OUT_70_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_70_OUT_70_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_70_OUT_70_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_70_OUT_70_OFFSET })

Definition at line 4096 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_70_OUT_70_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_70_OUT_70_MASK 0x3u

Definition at line 4094 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_70_OUT_70_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_70_OUT_70_OFFSET 0

Definition at line 4095 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_70_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_70_REG_OFFSET 0x72c

Definition at line 4092 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_70_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_70_REG_RESVAL 0x2u

Definition at line 4093 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_71_OUT_71_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_71_OUT_71_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_71_OUT_71_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_71_OUT_71_OFFSET })

Definition at line 4104 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_71_OUT_71_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_71_OUT_71_MASK 0x3u

Definition at line 4102 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_71_OUT_71_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_71_OUT_71_OFFSET 0

Definition at line 4103 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_71_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_71_REG_OFFSET 0x730

Definition at line 4100 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_71_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_71_REG_RESVAL 0x2u

Definition at line 4101 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_72_OUT_72_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_72_OUT_72_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_72_OUT_72_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_72_OUT_72_OFFSET })

Definition at line 4112 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_72_OUT_72_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_72_OUT_72_MASK 0x3u

Definition at line 4110 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_72_OUT_72_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_72_OUT_72_OFFSET 0

Definition at line 4111 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_72_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_72_REG_OFFSET 0x734

Definition at line 4108 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_72_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_72_REG_RESVAL 0x2u

Definition at line 4109 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_7_OUT_7_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_7_OUT_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_7_OUT_7_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_7_OUT_7_OFFSET })

Definition at line 3592 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_7_OUT_7_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_7_OUT_7_MASK 0x3u

Definition at line 3590 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_7_OUT_7_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_7_OUT_7_OFFSET 0

Definition at line 3591 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_7_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_7_REG_OFFSET 0x630

Definition at line 3588 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_7_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_7_REG_RESVAL 0x2u

Definition at line 3589 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_8_OUT_8_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_8_OUT_8_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_8_OUT_8_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_8_OUT_8_OFFSET })

Definition at line 3600 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_8_OUT_8_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_8_OUT_8_MASK 0x3u

Definition at line 3598 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_8_OUT_8_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_8_OUT_8_OFFSET 0

Definition at line 3599 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_8_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_8_REG_OFFSET 0x634

Definition at line 3596 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_8_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_8_REG_RESVAL 0x2u

Definition at line 3597 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_9_OUT_9_FIELD

#define PINMUX_DIO_PAD_SLEEP_MODE_9_OUT_9_FIELD ((bitfield_field32_t) { .mask = PINMUX_DIO_PAD_SLEEP_MODE_9_OUT_9_MASK, .index = PINMUX_DIO_PAD_SLEEP_MODE_9_OUT_9_OFFSET })

Definition at line 3608 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_9_OUT_9_MASK

#define PINMUX_DIO_PAD_SLEEP_MODE_9_OUT_9_MASK 0x3u

Definition at line 3606 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_9_OUT_9_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_9_OUT_9_OFFSET 0

Definition at line 3607 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_9_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_MODE_9_REG_OFFSET 0x638

Definition at line 3604 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_9_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_MODE_9_REG_RESVAL 0x2u

Definition at line 3605 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_MULTIREG_COUNT

#define PINMUX_DIO_PAD_SLEEP_MODE_MULTIREG_COUNT 73

Definition at line 3525 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_MODE_OUT_FIELD_WIDTH

#define PINMUX_DIO_PAD_SLEEP_MODE_OUT_FIELD_WIDTH 2

Definition at line 3524 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_0_EN_0_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_0_EN_0_BIT 0

Definition at line 2790 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_0_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_0_REG_OFFSET 0x3cc

Definition at line 2788 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_0_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_0_REG_RESVAL 0x1u

Definition at line 2789 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_10_EN_10_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_10_EN_10_BIT 0

Definition at line 2840 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_10_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_10_REG_OFFSET 0x3f4

Definition at line 2838 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_10_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_10_REG_RESVAL 0x1u

Definition at line 2839 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_11_EN_11_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_11_EN_11_BIT 0

Definition at line 2845 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_11_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_11_REG_OFFSET 0x3f8

Definition at line 2843 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_11_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_11_REG_RESVAL 0x1u

Definition at line 2844 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_12_EN_12_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_12_EN_12_BIT 0

Definition at line 2850 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_12_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_12_REG_OFFSET 0x3fc

Definition at line 2848 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_12_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_12_REG_RESVAL 0x1u

Definition at line 2849 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_13_EN_13_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_13_EN_13_BIT 0

Definition at line 2855 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_13_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_13_REG_OFFSET 0x400

Definition at line 2853 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_13_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_13_REG_RESVAL 0x1u

Definition at line 2854 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_14_EN_14_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_14_EN_14_BIT 0

Definition at line 2860 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_14_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_14_REG_OFFSET 0x404

Definition at line 2858 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_14_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_14_REG_RESVAL 0x1u

Definition at line 2859 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_15_EN_15_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_15_EN_15_BIT 0

Definition at line 2865 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_15_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_15_REG_OFFSET 0x408

Definition at line 2863 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_15_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_15_REG_RESVAL 0x1u

Definition at line 2864 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_16_EN_16_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_16_EN_16_BIT 0

Definition at line 2870 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_16_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_16_REG_OFFSET 0x40c

Definition at line 2868 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_16_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_16_REG_RESVAL 0x1u

Definition at line 2869 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_17_EN_17_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_17_EN_17_BIT 0

Definition at line 2875 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_17_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_17_REG_OFFSET 0x410

Definition at line 2873 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_17_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_17_REG_RESVAL 0x1u

Definition at line 2874 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_18_EN_18_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_18_EN_18_BIT 0

Definition at line 2880 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_18_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_18_REG_OFFSET 0x414

Definition at line 2878 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_18_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_18_REG_RESVAL 0x1u

Definition at line 2879 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_19_EN_19_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_19_EN_19_BIT 0

Definition at line 2885 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_19_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_19_REG_OFFSET 0x418

Definition at line 2883 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_19_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_19_REG_RESVAL 0x1u

Definition at line 2884 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_1_EN_1_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_1_EN_1_BIT 0

Definition at line 2795 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_1_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_1_REG_OFFSET 0x3d0

Definition at line 2793 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_1_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_1_REG_RESVAL 0x1u

Definition at line 2794 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_20_EN_20_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_20_EN_20_BIT 0

Definition at line 2890 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_20_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_20_REG_OFFSET 0x41c

Definition at line 2888 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_20_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_20_REG_RESVAL 0x1u

Definition at line 2889 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_21_EN_21_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_21_EN_21_BIT 0

Definition at line 2895 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_21_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_21_REG_OFFSET 0x420

Definition at line 2893 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_21_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_21_REG_RESVAL 0x1u

Definition at line 2894 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_22_EN_22_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_22_EN_22_BIT 0

Definition at line 2900 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_22_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_22_REG_OFFSET 0x424

Definition at line 2898 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_22_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_22_REG_RESVAL 0x1u

Definition at line 2899 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_23_EN_23_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_23_EN_23_BIT 0

Definition at line 2905 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_23_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_23_REG_OFFSET 0x428

Definition at line 2903 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_23_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_23_REG_RESVAL 0x1u

Definition at line 2904 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_24_EN_24_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_24_EN_24_BIT 0

Definition at line 2910 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_24_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_24_REG_OFFSET 0x42c

Definition at line 2908 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_24_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_24_REG_RESVAL 0x1u

Definition at line 2909 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_25_EN_25_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_25_EN_25_BIT 0

Definition at line 2915 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_25_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_25_REG_OFFSET 0x430

Definition at line 2913 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_25_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_25_REG_RESVAL 0x1u

Definition at line 2914 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_26_EN_26_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_26_EN_26_BIT 0

Definition at line 2920 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_26_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_26_REG_OFFSET 0x434

Definition at line 2918 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_26_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_26_REG_RESVAL 0x1u

Definition at line 2919 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_27_EN_27_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_27_EN_27_BIT 0

Definition at line 2925 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_27_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_27_REG_OFFSET 0x438

Definition at line 2923 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_27_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_27_REG_RESVAL 0x1u

Definition at line 2924 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_28_EN_28_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_28_EN_28_BIT 0

Definition at line 2930 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_28_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_28_REG_OFFSET 0x43c

Definition at line 2928 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_28_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_28_REG_RESVAL 0x1u

Definition at line 2929 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_29_EN_29_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_29_EN_29_BIT 0

Definition at line 2935 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_29_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_29_REG_OFFSET 0x440

Definition at line 2933 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_29_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_29_REG_RESVAL 0x1u

Definition at line 2934 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_2_EN_2_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_2_EN_2_BIT 0

Definition at line 2800 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_2_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_2_REG_OFFSET 0x3d4

Definition at line 2798 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_2_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_2_REG_RESVAL 0x1u

Definition at line 2799 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_30_EN_30_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_30_EN_30_BIT 0

Definition at line 2940 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_30_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_30_REG_OFFSET 0x444

Definition at line 2938 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_30_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_30_REG_RESVAL 0x1u

Definition at line 2939 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_31_EN_31_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_31_EN_31_BIT 0

Definition at line 2945 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_31_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_31_REG_OFFSET 0x448

Definition at line 2943 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_31_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_31_REG_RESVAL 0x1u

Definition at line 2944 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_32_EN_32_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_32_EN_32_BIT 0

Definition at line 2950 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_32_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_32_REG_OFFSET 0x44c

Definition at line 2948 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_32_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_32_REG_RESVAL 0x1u

Definition at line 2949 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_33_EN_33_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_33_EN_33_BIT 0

Definition at line 2955 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_33_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_33_REG_OFFSET 0x450

Definition at line 2953 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_33_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_33_REG_RESVAL 0x1u

Definition at line 2954 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_34_EN_34_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_34_EN_34_BIT 0

Definition at line 2960 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_34_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_34_REG_OFFSET 0x454

Definition at line 2958 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_34_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_34_REG_RESVAL 0x1u

Definition at line 2959 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_35_EN_35_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_35_EN_35_BIT 0

Definition at line 2965 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_35_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_35_REG_OFFSET 0x458

Definition at line 2963 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_35_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_35_REG_RESVAL 0x1u

Definition at line 2964 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_36_EN_36_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_36_EN_36_BIT 0

Definition at line 2970 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_36_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_36_REG_OFFSET 0x45c

Definition at line 2968 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_36_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_36_REG_RESVAL 0x1u

Definition at line 2969 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_37_EN_37_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_37_EN_37_BIT 0

Definition at line 2975 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_37_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_37_REG_OFFSET 0x460

Definition at line 2973 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_37_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_37_REG_RESVAL 0x1u

Definition at line 2974 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_38_EN_38_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_38_EN_38_BIT 0

Definition at line 2980 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_38_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_38_REG_OFFSET 0x464

Definition at line 2978 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_38_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_38_REG_RESVAL 0x1u

Definition at line 2979 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_39_EN_39_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_39_EN_39_BIT 0

Definition at line 2985 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_39_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_39_REG_OFFSET 0x468

Definition at line 2983 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_39_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_39_REG_RESVAL 0x1u

Definition at line 2984 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_3_EN_3_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_3_EN_3_BIT 0

Definition at line 2805 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_3_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_3_REG_OFFSET 0x3d8

Definition at line 2803 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_3_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_3_REG_RESVAL 0x1u

Definition at line 2804 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_40_EN_40_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_40_EN_40_BIT 0

Definition at line 2990 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_40_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_40_REG_OFFSET 0x46c

Definition at line 2988 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_40_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_40_REG_RESVAL 0x1u

Definition at line 2989 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_41_EN_41_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_41_EN_41_BIT 0

Definition at line 2995 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_41_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_41_REG_OFFSET 0x470

Definition at line 2993 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_41_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_41_REG_RESVAL 0x1u

Definition at line 2994 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_42_EN_42_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_42_EN_42_BIT 0

Definition at line 3000 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_42_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_42_REG_OFFSET 0x474

Definition at line 2998 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_42_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_42_REG_RESVAL 0x1u

Definition at line 2999 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_43_EN_43_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_43_EN_43_BIT 0

Definition at line 3005 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_43_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_43_REG_OFFSET 0x478

Definition at line 3003 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_43_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_43_REG_RESVAL 0x1u

Definition at line 3004 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_44_EN_44_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_44_EN_44_BIT 0

Definition at line 3010 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_44_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_44_REG_OFFSET 0x47c

Definition at line 3008 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_44_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_44_REG_RESVAL 0x1u

Definition at line 3009 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_45_EN_45_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_45_EN_45_BIT 0

Definition at line 3015 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_45_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_45_REG_OFFSET 0x480

Definition at line 3013 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_45_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_45_REG_RESVAL 0x1u

Definition at line 3014 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_46_EN_46_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_46_EN_46_BIT 0

Definition at line 3020 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_46_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_46_REG_OFFSET 0x484

Definition at line 3018 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_46_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_46_REG_RESVAL 0x1u

Definition at line 3019 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_47_EN_47_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_47_EN_47_BIT 0

Definition at line 3025 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_47_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_47_REG_OFFSET 0x488

Definition at line 3023 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_47_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_47_REG_RESVAL 0x1u

Definition at line 3024 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_48_EN_48_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_48_EN_48_BIT 0

Definition at line 3030 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_48_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_48_REG_OFFSET 0x48c

Definition at line 3028 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_48_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_48_REG_RESVAL 0x1u

Definition at line 3029 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_49_EN_49_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_49_EN_49_BIT 0

Definition at line 3035 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_49_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_49_REG_OFFSET 0x490

Definition at line 3033 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_49_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_49_REG_RESVAL 0x1u

Definition at line 3034 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_4_EN_4_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_4_EN_4_BIT 0

Definition at line 2810 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_4_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_4_REG_OFFSET 0x3dc

Definition at line 2808 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_4_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_4_REG_RESVAL 0x1u

Definition at line 2809 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_50_EN_50_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_50_EN_50_BIT 0

Definition at line 3040 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_50_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_50_REG_OFFSET 0x494

Definition at line 3038 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_50_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_50_REG_RESVAL 0x1u

Definition at line 3039 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_51_EN_51_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_51_EN_51_BIT 0

Definition at line 3045 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_51_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_51_REG_OFFSET 0x498

Definition at line 3043 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_51_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_51_REG_RESVAL 0x1u

Definition at line 3044 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_52_EN_52_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_52_EN_52_BIT 0

Definition at line 3050 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_52_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_52_REG_OFFSET 0x49c

Definition at line 3048 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_52_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_52_REG_RESVAL 0x1u

Definition at line 3049 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_53_EN_53_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_53_EN_53_BIT 0

Definition at line 3055 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_53_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_53_REG_OFFSET 0x4a0

Definition at line 3053 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_53_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_53_REG_RESVAL 0x1u

Definition at line 3054 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_54_EN_54_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_54_EN_54_BIT 0

Definition at line 3060 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_54_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_54_REG_OFFSET 0x4a4

Definition at line 3058 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_54_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_54_REG_RESVAL 0x1u

Definition at line 3059 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_55_EN_55_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_55_EN_55_BIT 0

Definition at line 3065 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_55_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_55_REG_OFFSET 0x4a8

Definition at line 3063 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_55_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_55_REG_RESVAL 0x1u

Definition at line 3064 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_56_EN_56_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_56_EN_56_BIT 0

Definition at line 3070 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_56_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_56_REG_OFFSET 0x4ac

Definition at line 3068 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_56_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_56_REG_RESVAL 0x1u

Definition at line 3069 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_57_EN_57_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_57_EN_57_BIT 0

Definition at line 3075 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_57_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_57_REG_OFFSET 0x4b0

Definition at line 3073 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_57_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_57_REG_RESVAL 0x1u

Definition at line 3074 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_58_EN_58_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_58_EN_58_BIT 0

Definition at line 3080 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_58_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_58_REG_OFFSET 0x4b4

Definition at line 3078 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_58_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_58_REG_RESVAL 0x1u

Definition at line 3079 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_59_EN_59_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_59_EN_59_BIT 0

Definition at line 3085 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_59_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_59_REG_OFFSET 0x4b8

Definition at line 3083 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_59_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_59_REG_RESVAL 0x1u

Definition at line 3084 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_5_EN_5_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_5_EN_5_BIT 0

Definition at line 2815 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_5_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_5_REG_OFFSET 0x3e0

Definition at line 2813 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_5_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_5_REG_RESVAL 0x1u

Definition at line 2814 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_60_EN_60_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_60_EN_60_BIT 0

Definition at line 3090 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_60_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_60_REG_OFFSET 0x4bc

Definition at line 3088 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_60_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_60_REG_RESVAL 0x1u

Definition at line 3089 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_61_EN_61_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_61_EN_61_BIT 0

Definition at line 3095 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_61_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_61_REG_OFFSET 0x4c0

Definition at line 3093 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_61_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_61_REG_RESVAL 0x1u

Definition at line 3094 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_62_EN_62_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_62_EN_62_BIT 0

Definition at line 3100 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_62_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_62_REG_OFFSET 0x4c4

Definition at line 3098 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_62_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_62_REG_RESVAL 0x1u

Definition at line 3099 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_63_EN_63_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_63_EN_63_BIT 0

Definition at line 3105 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_63_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_63_REG_OFFSET 0x4c8

Definition at line 3103 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_63_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_63_REG_RESVAL 0x1u

Definition at line 3104 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_64_EN_64_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_64_EN_64_BIT 0

Definition at line 3110 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_64_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_64_REG_OFFSET 0x4cc

Definition at line 3108 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_64_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_64_REG_RESVAL 0x1u

Definition at line 3109 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_65_EN_65_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_65_EN_65_BIT 0

Definition at line 3115 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_65_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_65_REG_OFFSET 0x4d0

Definition at line 3113 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_65_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_65_REG_RESVAL 0x1u

Definition at line 3114 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_66_EN_66_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_66_EN_66_BIT 0

Definition at line 3120 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_66_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_66_REG_OFFSET 0x4d4

Definition at line 3118 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_66_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_66_REG_RESVAL 0x1u

Definition at line 3119 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_67_EN_67_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_67_EN_67_BIT 0

Definition at line 3125 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_67_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_67_REG_OFFSET 0x4d8

Definition at line 3123 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_67_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_67_REG_RESVAL 0x1u

Definition at line 3124 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_68_EN_68_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_68_EN_68_BIT 0

Definition at line 3130 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_68_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_68_REG_OFFSET 0x4dc

Definition at line 3128 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_68_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_68_REG_RESVAL 0x1u

Definition at line 3129 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_69_EN_69_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_69_EN_69_BIT 0

Definition at line 3135 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_69_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_69_REG_OFFSET 0x4e0

Definition at line 3133 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_69_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_69_REG_RESVAL 0x1u

Definition at line 3134 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_6_EN_6_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_6_EN_6_BIT 0

Definition at line 2820 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_6_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_6_REG_OFFSET 0x3e4

Definition at line 2818 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_6_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_6_REG_RESVAL 0x1u

Definition at line 2819 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_70_EN_70_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_70_EN_70_BIT 0

Definition at line 3140 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_70_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_70_REG_OFFSET 0x4e4

Definition at line 3138 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_70_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_70_REG_RESVAL 0x1u

Definition at line 3139 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_71_EN_71_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_71_EN_71_BIT 0

Definition at line 3145 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_71_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_71_REG_OFFSET 0x4e8

Definition at line 3143 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_71_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_71_REG_RESVAL 0x1u

Definition at line 3144 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_72_EN_72_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_72_EN_72_BIT 0

Definition at line 3150 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_72_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_72_REG_OFFSET 0x4ec

Definition at line 3148 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_72_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_72_REG_RESVAL 0x1u

Definition at line 3149 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_7_EN_7_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_7_EN_7_BIT 0

Definition at line 2825 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_7_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_7_REG_OFFSET 0x3e8

Definition at line 2823 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_7_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_7_REG_RESVAL 0x1u

Definition at line 2824 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_8_EN_8_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_8_EN_8_BIT 0

Definition at line 2830 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_8_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_8_REG_OFFSET 0x3ec

Definition at line 2828 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_8_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_8_REG_RESVAL 0x1u

Definition at line 2829 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_9_EN_9_BIT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_9_EN_9_BIT 0

Definition at line 2835 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_9_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_REGWEN_9_REG_OFFSET 0x3f0

Definition at line 2833 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_9_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_REGWEN_9_REG_RESVAL 0x1u

Definition at line 2834 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_EN_FIELD_WIDTH

#define PINMUX_DIO_PAD_SLEEP_REGWEN_EN_FIELD_WIDTH 1

Definition at line 2784 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_REGWEN_MULTIREG_COUNT

#define PINMUX_DIO_PAD_SLEEP_REGWEN_MULTIREG_COUNT 73

Definition at line 2785 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_0_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_0_BIT 0

Definition at line 2700 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_10_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_10_BIT 10

Definition at line 2710 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_11_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_11_BIT 11

Definition at line 2711 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_12_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_12_BIT 12

Definition at line 2712 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_13_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_13_BIT 13

Definition at line 2713 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_14_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_14_BIT 14

Definition at line 2714 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_15_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_15_BIT 15

Definition at line 2715 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_16_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_16_BIT 16

Definition at line 2716 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_17_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_17_BIT 17

Definition at line 2717 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_18_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_18_BIT 18

Definition at line 2718 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_19_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_19_BIT 19

Definition at line 2719 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_1_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_1_BIT 1

Definition at line 2701 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_20_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_20_BIT 20

Definition at line 2720 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_21_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_21_BIT 21

Definition at line 2721 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_22_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_22_BIT 22

Definition at line 2722 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_23_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_23_BIT 23

Definition at line 2723 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_24_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_24_BIT 24

Definition at line 2724 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_25_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_25_BIT 25

Definition at line 2725 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_26_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_26_BIT 26

Definition at line 2726 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_27_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_27_BIT 27

Definition at line 2727 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_28_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_28_BIT 28

Definition at line 2728 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_29_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_29_BIT 29

Definition at line 2729 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_2_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_2_BIT 2

Definition at line 2702 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_30_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_30_BIT 30

Definition at line 2730 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_31_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_31_BIT 31

Definition at line 2731 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_3_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_3_BIT 3

Definition at line 2703 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_4_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_4_BIT 4

Definition at line 2704 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_5_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_5_BIT 5

Definition at line 2705 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_6_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_6_BIT 6

Definition at line 2706 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_7_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_7_BIT 7

Definition at line 2707 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_8_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_8_BIT 8

Definition at line 2708 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_9_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_EN_9_BIT 9

Definition at line 2709 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_REG_OFFSET 0x3c0

Definition at line 2698 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_0_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_STATUS_0_REG_RESVAL 0x0u

Definition at line 2699 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_32_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_32_BIT 0

Definition at line 2736 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_33_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_33_BIT 1

Definition at line 2737 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_34_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_34_BIT 2

Definition at line 2738 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_35_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_35_BIT 3

Definition at line 2739 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_36_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_36_BIT 4

Definition at line 2740 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_37_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_37_BIT 5

Definition at line 2741 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_38_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_38_BIT 6

Definition at line 2742 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_39_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_39_BIT 7

Definition at line 2743 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_40_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_40_BIT 8

Definition at line 2744 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_41_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_41_BIT 9

Definition at line 2745 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_42_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_42_BIT 10

Definition at line 2746 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_43_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_43_BIT 11

Definition at line 2747 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_44_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_44_BIT 12

Definition at line 2748 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_45_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_45_BIT 13

Definition at line 2749 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_46_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_46_BIT 14

Definition at line 2750 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_47_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_47_BIT 15

Definition at line 2751 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_48_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_48_BIT 16

Definition at line 2752 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_49_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_49_BIT 17

Definition at line 2753 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_50_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_50_BIT 18

Definition at line 2754 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_51_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_51_BIT 19

Definition at line 2755 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_52_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_52_BIT 20

Definition at line 2756 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_53_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_53_BIT 21

Definition at line 2757 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_54_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_54_BIT 22

Definition at line 2758 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_55_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_55_BIT 23

Definition at line 2759 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_56_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_56_BIT 24

Definition at line 2760 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_57_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_57_BIT 25

Definition at line 2761 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_58_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_58_BIT 26

Definition at line 2762 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_59_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_59_BIT 27

Definition at line 2763 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_60_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_60_BIT 28

Definition at line 2764 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_61_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_61_BIT 29

Definition at line 2765 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_62_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_62_BIT 30

Definition at line 2766 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_63_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_EN_63_BIT 31

Definition at line 2767 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_REG_OFFSET 0x3c4

Definition at line 2734 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_1_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_STATUS_1_REG_RESVAL 0x0u

Definition at line 2735 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_2_EN_64_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_2_EN_64_BIT 0

Definition at line 2772 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_2_EN_65_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_2_EN_65_BIT 1

Definition at line 2773 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_2_EN_66_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_2_EN_66_BIT 2

Definition at line 2774 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_2_EN_67_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_2_EN_67_BIT 3

Definition at line 2775 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_2_EN_68_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_2_EN_68_BIT 4

Definition at line 2776 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_2_EN_69_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_2_EN_69_BIT 5

Definition at line 2777 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_2_EN_70_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_2_EN_70_BIT 6

Definition at line 2778 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_2_EN_71_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_2_EN_71_BIT 7

Definition at line 2779 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_2_EN_72_BIT

#define PINMUX_DIO_PAD_SLEEP_STATUS_2_EN_72_BIT 8

Definition at line 2780 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_2_REG_OFFSET

#define PINMUX_DIO_PAD_SLEEP_STATUS_2_REG_OFFSET 0x3c8

Definition at line 2770 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_2_REG_RESVAL

#define PINMUX_DIO_PAD_SLEEP_STATUS_2_REG_RESVAL 0x0u

Definition at line 2771 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_EN_FIELD_WIDTH

#define PINMUX_DIO_PAD_SLEEP_STATUS_EN_FIELD_WIDTH 1

Definition at line 2694 of file pinmux_regs.h.

◆ PINMUX_DIO_PAD_SLEEP_STATUS_MULTIREG_COUNT

#define PINMUX_DIO_PAD_SLEEP_STATUS_MULTIREG_COUNT 3

Definition at line 2695 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_0_OUT_0_FIELD

#define PINMUX_MIO_OUTSEL_0_OUT_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_0_OUT_0_MASK, .index = PINMUX_MIO_OUTSEL_0_OUT_0_OFFSET })

Definition at line 184 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_0_OUT_0_MASK

#define PINMUX_MIO_OUTSEL_0_OUT_0_MASK 0x7u

Definition at line 182 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_0_OUT_0_OFFSET

#define PINMUX_MIO_OUTSEL_0_OUT_0_OFFSET 0

Definition at line 183 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_0_REG_OFFSET

#define PINMUX_MIO_OUTSEL_0_REG_OFFSET 0x54

Definition at line 180 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_0_REG_RESVAL

#define PINMUX_MIO_OUTSEL_0_REG_RESVAL 0x2u

Definition at line 181 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_10_OUT_10_FIELD

#define PINMUX_MIO_OUTSEL_10_OUT_10_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_10_OUT_10_MASK, .index = PINMUX_MIO_OUTSEL_10_OUT_10_OFFSET })

Definition at line 264 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_10_OUT_10_MASK

#define PINMUX_MIO_OUTSEL_10_OUT_10_MASK 0x7u

Definition at line 262 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_10_OUT_10_OFFSET

#define PINMUX_MIO_OUTSEL_10_OUT_10_OFFSET 0

Definition at line 263 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_10_REG_OFFSET

#define PINMUX_MIO_OUTSEL_10_REG_OFFSET 0x7c

Definition at line 260 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_10_REG_RESVAL

#define PINMUX_MIO_OUTSEL_10_REG_RESVAL 0x2u

Definition at line 261 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_11_OUT_11_FIELD

#define PINMUX_MIO_OUTSEL_11_OUT_11_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_11_OUT_11_MASK, .index = PINMUX_MIO_OUTSEL_11_OUT_11_OFFSET })

Definition at line 272 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_11_OUT_11_MASK

#define PINMUX_MIO_OUTSEL_11_OUT_11_MASK 0x7u

Definition at line 270 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_11_OUT_11_OFFSET

#define PINMUX_MIO_OUTSEL_11_OUT_11_OFFSET 0

Definition at line 271 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_11_REG_OFFSET

#define PINMUX_MIO_OUTSEL_11_REG_OFFSET 0x80

Definition at line 268 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_11_REG_RESVAL

#define PINMUX_MIO_OUTSEL_11_REG_RESVAL 0x2u

Definition at line 269 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_1_OUT_1_FIELD

#define PINMUX_MIO_OUTSEL_1_OUT_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_1_OUT_1_MASK, .index = PINMUX_MIO_OUTSEL_1_OUT_1_OFFSET })

Definition at line 192 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_1_OUT_1_MASK

#define PINMUX_MIO_OUTSEL_1_OUT_1_MASK 0x7u

Definition at line 190 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_1_OUT_1_OFFSET

#define PINMUX_MIO_OUTSEL_1_OUT_1_OFFSET 0

Definition at line 191 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_1_REG_OFFSET

#define PINMUX_MIO_OUTSEL_1_REG_OFFSET 0x58

Definition at line 188 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_1_REG_RESVAL

#define PINMUX_MIO_OUTSEL_1_REG_RESVAL 0x2u

Definition at line 189 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_2_OUT_2_FIELD

#define PINMUX_MIO_OUTSEL_2_OUT_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_2_OUT_2_MASK, .index = PINMUX_MIO_OUTSEL_2_OUT_2_OFFSET })

Definition at line 200 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_2_OUT_2_MASK

#define PINMUX_MIO_OUTSEL_2_OUT_2_MASK 0x7u

Definition at line 198 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_2_OUT_2_OFFSET

#define PINMUX_MIO_OUTSEL_2_OUT_2_OFFSET 0

Definition at line 199 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_2_REG_OFFSET

#define PINMUX_MIO_OUTSEL_2_REG_OFFSET 0x5c

Definition at line 196 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_2_REG_RESVAL

#define PINMUX_MIO_OUTSEL_2_REG_RESVAL 0x2u

Definition at line 197 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_3_OUT_3_FIELD

#define PINMUX_MIO_OUTSEL_3_OUT_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_3_OUT_3_MASK, .index = PINMUX_MIO_OUTSEL_3_OUT_3_OFFSET })

Definition at line 208 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_3_OUT_3_MASK

#define PINMUX_MIO_OUTSEL_3_OUT_3_MASK 0x7u

Definition at line 206 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_3_OUT_3_OFFSET

#define PINMUX_MIO_OUTSEL_3_OUT_3_OFFSET 0

Definition at line 207 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_3_REG_OFFSET

#define PINMUX_MIO_OUTSEL_3_REG_OFFSET 0x60

Definition at line 204 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_3_REG_RESVAL

#define PINMUX_MIO_OUTSEL_3_REG_RESVAL 0x2u

Definition at line 205 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_4_OUT_4_FIELD

#define PINMUX_MIO_OUTSEL_4_OUT_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_4_OUT_4_MASK, .index = PINMUX_MIO_OUTSEL_4_OUT_4_OFFSET })

Definition at line 216 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_4_OUT_4_MASK

#define PINMUX_MIO_OUTSEL_4_OUT_4_MASK 0x7u

Definition at line 214 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_4_OUT_4_OFFSET

#define PINMUX_MIO_OUTSEL_4_OUT_4_OFFSET 0

Definition at line 215 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_4_REG_OFFSET

#define PINMUX_MIO_OUTSEL_4_REG_OFFSET 0x64

Definition at line 212 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_4_REG_RESVAL

#define PINMUX_MIO_OUTSEL_4_REG_RESVAL 0x2u

Definition at line 213 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_5_OUT_5_FIELD

#define PINMUX_MIO_OUTSEL_5_OUT_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_5_OUT_5_MASK, .index = PINMUX_MIO_OUTSEL_5_OUT_5_OFFSET })

Definition at line 224 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_5_OUT_5_MASK

#define PINMUX_MIO_OUTSEL_5_OUT_5_MASK 0x7u

Definition at line 222 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_5_OUT_5_OFFSET

#define PINMUX_MIO_OUTSEL_5_OUT_5_OFFSET 0

Definition at line 223 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_5_REG_OFFSET

#define PINMUX_MIO_OUTSEL_5_REG_OFFSET 0x68

Definition at line 220 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_5_REG_RESVAL

#define PINMUX_MIO_OUTSEL_5_REG_RESVAL 0x2u

Definition at line 221 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_6_OUT_6_FIELD

#define PINMUX_MIO_OUTSEL_6_OUT_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_6_OUT_6_MASK, .index = PINMUX_MIO_OUTSEL_6_OUT_6_OFFSET })

Definition at line 232 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_6_OUT_6_MASK

#define PINMUX_MIO_OUTSEL_6_OUT_6_MASK 0x7u

Definition at line 230 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_6_OUT_6_OFFSET

#define PINMUX_MIO_OUTSEL_6_OUT_6_OFFSET 0

Definition at line 231 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_6_REG_OFFSET

#define PINMUX_MIO_OUTSEL_6_REG_OFFSET 0x6c

Definition at line 228 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_6_REG_RESVAL

#define PINMUX_MIO_OUTSEL_6_REG_RESVAL 0x2u

Definition at line 229 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_7_OUT_7_FIELD

#define PINMUX_MIO_OUTSEL_7_OUT_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_7_OUT_7_MASK, .index = PINMUX_MIO_OUTSEL_7_OUT_7_OFFSET })

Definition at line 240 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_7_OUT_7_MASK

#define PINMUX_MIO_OUTSEL_7_OUT_7_MASK 0x7u

Definition at line 238 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_7_OUT_7_OFFSET

#define PINMUX_MIO_OUTSEL_7_OUT_7_OFFSET 0

Definition at line 239 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_7_REG_OFFSET

#define PINMUX_MIO_OUTSEL_7_REG_OFFSET 0x70

Definition at line 236 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_7_REG_RESVAL

#define PINMUX_MIO_OUTSEL_7_REG_RESVAL 0x2u

Definition at line 237 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_8_OUT_8_FIELD

#define PINMUX_MIO_OUTSEL_8_OUT_8_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_8_OUT_8_MASK, .index = PINMUX_MIO_OUTSEL_8_OUT_8_OFFSET })

Definition at line 248 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_8_OUT_8_MASK

#define PINMUX_MIO_OUTSEL_8_OUT_8_MASK 0x7u

Definition at line 246 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_8_OUT_8_OFFSET

#define PINMUX_MIO_OUTSEL_8_OUT_8_OFFSET 0

Definition at line 247 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_8_REG_OFFSET

#define PINMUX_MIO_OUTSEL_8_REG_OFFSET 0x74

Definition at line 244 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_8_REG_RESVAL

#define PINMUX_MIO_OUTSEL_8_REG_RESVAL 0x2u

Definition at line 245 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_9_OUT_9_FIELD

#define PINMUX_MIO_OUTSEL_9_OUT_9_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_OUTSEL_9_OUT_9_MASK, .index = PINMUX_MIO_OUTSEL_9_OUT_9_OFFSET })

Definition at line 256 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_9_OUT_9_MASK

#define PINMUX_MIO_OUTSEL_9_OUT_9_MASK 0x7u

Definition at line 254 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_9_OUT_9_OFFSET

#define PINMUX_MIO_OUTSEL_9_OUT_9_OFFSET 0

Definition at line 255 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_9_REG_OFFSET

#define PINMUX_MIO_OUTSEL_9_REG_OFFSET 0x78

Definition at line 252 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_9_REG_RESVAL

#define PINMUX_MIO_OUTSEL_9_REG_RESVAL 0x2u

Definition at line 253 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_MULTIREG_COUNT

#define PINMUX_MIO_OUTSEL_MULTIREG_COUNT 12

Definition at line 177 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_OUT_FIELD_WIDTH

#define PINMUX_MIO_OUTSEL_OUT_FIELD_WIDTH 3

Definition at line 176 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_0_EN_0_BIT

#define PINMUX_MIO_OUTSEL_REGWEN_0_EN_0_BIT 0

Definition at line 117 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_0_REG_OFFSET

#define PINMUX_MIO_OUTSEL_REGWEN_0_REG_OFFSET 0x24

Definition at line 115 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_0_REG_RESVAL

#define PINMUX_MIO_OUTSEL_REGWEN_0_REG_RESVAL 0x1u

Definition at line 116 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_10_EN_10_BIT

#define PINMUX_MIO_OUTSEL_REGWEN_10_EN_10_BIT 0

Definition at line 167 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_10_REG_OFFSET

#define PINMUX_MIO_OUTSEL_REGWEN_10_REG_OFFSET 0x4c

Definition at line 165 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_10_REG_RESVAL

#define PINMUX_MIO_OUTSEL_REGWEN_10_REG_RESVAL 0x1u

Definition at line 166 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_11_EN_11_BIT

#define PINMUX_MIO_OUTSEL_REGWEN_11_EN_11_BIT 0

Definition at line 172 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_11_REG_OFFSET

#define PINMUX_MIO_OUTSEL_REGWEN_11_REG_OFFSET 0x50

Definition at line 170 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_11_REG_RESVAL

#define PINMUX_MIO_OUTSEL_REGWEN_11_REG_RESVAL 0x1u

Definition at line 171 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_1_EN_1_BIT

#define PINMUX_MIO_OUTSEL_REGWEN_1_EN_1_BIT 0

Definition at line 122 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_1_REG_OFFSET

#define PINMUX_MIO_OUTSEL_REGWEN_1_REG_OFFSET 0x28

Definition at line 120 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_1_REG_RESVAL

#define PINMUX_MIO_OUTSEL_REGWEN_1_REG_RESVAL 0x1u

Definition at line 121 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_2_EN_2_BIT

#define PINMUX_MIO_OUTSEL_REGWEN_2_EN_2_BIT 0

Definition at line 127 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_2_REG_OFFSET

#define PINMUX_MIO_OUTSEL_REGWEN_2_REG_OFFSET 0x2c

Definition at line 125 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_2_REG_RESVAL

#define PINMUX_MIO_OUTSEL_REGWEN_2_REG_RESVAL 0x1u

Definition at line 126 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_3_EN_3_BIT

#define PINMUX_MIO_OUTSEL_REGWEN_3_EN_3_BIT 0

Definition at line 132 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_3_REG_OFFSET

#define PINMUX_MIO_OUTSEL_REGWEN_3_REG_OFFSET 0x30

Definition at line 130 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_3_REG_RESVAL

#define PINMUX_MIO_OUTSEL_REGWEN_3_REG_RESVAL 0x1u

Definition at line 131 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_4_EN_4_BIT

#define PINMUX_MIO_OUTSEL_REGWEN_4_EN_4_BIT 0

Definition at line 137 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_4_REG_OFFSET

#define PINMUX_MIO_OUTSEL_REGWEN_4_REG_OFFSET 0x34

Definition at line 135 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_4_REG_RESVAL

#define PINMUX_MIO_OUTSEL_REGWEN_4_REG_RESVAL 0x1u

Definition at line 136 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_5_EN_5_BIT

#define PINMUX_MIO_OUTSEL_REGWEN_5_EN_5_BIT 0

Definition at line 142 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_5_REG_OFFSET

#define PINMUX_MIO_OUTSEL_REGWEN_5_REG_OFFSET 0x38

Definition at line 140 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_5_REG_RESVAL

#define PINMUX_MIO_OUTSEL_REGWEN_5_REG_RESVAL 0x1u

Definition at line 141 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_6_EN_6_BIT

#define PINMUX_MIO_OUTSEL_REGWEN_6_EN_6_BIT 0

Definition at line 147 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_6_REG_OFFSET

#define PINMUX_MIO_OUTSEL_REGWEN_6_REG_OFFSET 0x3c

Definition at line 145 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_6_REG_RESVAL

#define PINMUX_MIO_OUTSEL_REGWEN_6_REG_RESVAL 0x1u

Definition at line 146 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_7_EN_7_BIT

#define PINMUX_MIO_OUTSEL_REGWEN_7_EN_7_BIT 0

Definition at line 152 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_7_REG_OFFSET

#define PINMUX_MIO_OUTSEL_REGWEN_7_REG_OFFSET 0x40

Definition at line 150 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_7_REG_RESVAL

#define PINMUX_MIO_OUTSEL_REGWEN_7_REG_RESVAL 0x1u

Definition at line 151 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_8_EN_8_BIT

#define PINMUX_MIO_OUTSEL_REGWEN_8_EN_8_BIT 0

Definition at line 157 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_8_REG_OFFSET

#define PINMUX_MIO_OUTSEL_REGWEN_8_REG_OFFSET 0x44

Definition at line 155 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_8_REG_RESVAL

#define PINMUX_MIO_OUTSEL_REGWEN_8_REG_RESVAL 0x1u

Definition at line 156 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_9_EN_9_BIT

#define PINMUX_MIO_OUTSEL_REGWEN_9_EN_9_BIT 0

Definition at line 162 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_9_REG_OFFSET

#define PINMUX_MIO_OUTSEL_REGWEN_9_REG_OFFSET 0x48

Definition at line 160 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_9_REG_RESVAL

#define PINMUX_MIO_OUTSEL_REGWEN_9_REG_RESVAL 0x1u

Definition at line 161 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_EN_FIELD_WIDTH

#define PINMUX_MIO_OUTSEL_REGWEN_EN_FIELD_WIDTH 1

Definition at line 111 of file pinmux_regs.h.

◆ PINMUX_MIO_OUTSEL_REGWEN_MULTIREG_COUNT

#define PINMUX_MIO_OUTSEL_REGWEN_MULTIREG_COUNT 12

Definition at line 112 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_FIELD

#define PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_MASK, .index = PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_OFFSET })

Definition at line 371 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_MASK

#define PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_MASK 0xfu

Definition at line 369 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_OFFSET

#define PINMUX_MIO_PAD_ATTR_0_DRIVE_STRENGTH_0_OFFSET 20

Definition at line 370 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_0_INPUT_DISABLE_0_BIT

#define PINMUX_MIO_PAD_ATTR_0_INPUT_DISABLE_0_BIT 7

Definition at line 364 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_0_INVERT_0_BIT

#define PINMUX_MIO_PAD_ATTR_0_INVERT_0_BIT 0

Definition at line 355 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_0_KEEPER_EN_0_BIT

#define PINMUX_MIO_PAD_ATTR_0_KEEPER_EN_0_BIT 4

Definition at line 361 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_0_OD_EN_0_BIT

#define PINMUX_MIO_PAD_ATTR_0_OD_EN_0_BIT 6

Definition at line 363 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_0_PULL_EN_0_BIT

#define PINMUX_MIO_PAD_ATTR_0_PULL_EN_0_BIT 2

Definition at line 357 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_0_PULL_SELECT_0_BIT

#define PINMUX_MIO_PAD_ATTR_0_PULL_SELECT_0_BIT 3

Definition at line 358 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_0_PULL_SELECT_0_VALUE_PULL_DOWN

#define PINMUX_MIO_PAD_ATTR_0_PULL_SELECT_0_VALUE_PULL_DOWN 0x0

Definition at line 359 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_0_PULL_SELECT_0_VALUE_PULL_UP

#define PINMUX_MIO_PAD_ATTR_0_PULL_SELECT_0_VALUE_PULL_UP 0x1

Definition at line 360 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_0_REG_OFFSET

#define PINMUX_MIO_PAD_ATTR_0_REG_OFFSET 0xb4

Definition at line 353 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_0_REG_RESVAL

#define PINMUX_MIO_PAD_ATTR_0_REG_RESVAL 0x0u

Definition at line 354 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_0_SCHMITT_EN_0_BIT

#define PINMUX_MIO_PAD_ATTR_0_SCHMITT_EN_0_BIT 5

Definition at line 362 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_FIELD

#define PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_MASK, .index = PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_OFFSET })

Definition at line 367 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_MASK

#define PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_MASK 0x3u

Definition at line 365 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_OFFSET

#define PINMUX_MIO_PAD_ATTR_0_SLEW_RATE_0_OFFSET 16

Definition at line 366 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_0_VIRTUAL_OD_EN_0_BIT

#define PINMUX_MIO_PAD_ATTR_0_VIRTUAL_OD_EN_0_BIT 1

Definition at line 356 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_FIELD

#define PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_MASK, .index = PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_OFFSET })

Definition at line 571 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_MASK

#define PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_MASK 0xfu

Definition at line 569 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_OFFSET

#define PINMUX_MIO_PAD_ATTR_10_DRIVE_STRENGTH_10_OFFSET 20

Definition at line 570 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_10_INPUT_DISABLE_10_BIT

#define PINMUX_MIO_PAD_ATTR_10_INPUT_DISABLE_10_BIT 7

Definition at line 564 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_10_INVERT_10_BIT

#define PINMUX_MIO_PAD_ATTR_10_INVERT_10_BIT 0

Definition at line 557 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_10_KEEPER_EN_10_BIT

#define PINMUX_MIO_PAD_ATTR_10_KEEPER_EN_10_BIT 4

Definition at line 561 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_10_OD_EN_10_BIT

#define PINMUX_MIO_PAD_ATTR_10_OD_EN_10_BIT 6

Definition at line 563 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_10_PULL_EN_10_BIT

#define PINMUX_MIO_PAD_ATTR_10_PULL_EN_10_BIT 2

Definition at line 559 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_10_PULL_SELECT_10_BIT

#define PINMUX_MIO_PAD_ATTR_10_PULL_SELECT_10_BIT 3

Definition at line 560 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_10_REG_OFFSET

#define PINMUX_MIO_PAD_ATTR_10_REG_OFFSET 0xdc

Definition at line 555 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_10_REG_RESVAL

#define PINMUX_MIO_PAD_ATTR_10_REG_RESVAL 0x0u

Definition at line 556 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_10_SCHMITT_EN_10_BIT

#define PINMUX_MIO_PAD_ATTR_10_SCHMITT_EN_10_BIT 5

Definition at line 562 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_FIELD

#define PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_MASK, .index = PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_OFFSET })

Definition at line 567 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_MASK

#define PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_MASK 0x3u

Definition at line 565 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_OFFSET

#define PINMUX_MIO_PAD_ATTR_10_SLEW_RATE_10_OFFSET 16

Definition at line 566 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_10_VIRTUAL_OD_EN_10_BIT

#define PINMUX_MIO_PAD_ATTR_10_VIRTUAL_OD_EN_10_BIT 1

Definition at line 558 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_FIELD

#define PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_MASK, .index = PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_OFFSET })

Definition at line 591 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_MASK

#define PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_MASK 0xfu

Definition at line 589 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_OFFSET

#define PINMUX_MIO_PAD_ATTR_11_DRIVE_STRENGTH_11_OFFSET 20

Definition at line 590 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_11_INPUT_DISABLE_11_BIT

#define PINMUX_MIO_PAD_ATTR_11_INPUT_DISABLE_11_BIT 7

Definition at line 584 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_11_INVERT_11_BIT

#define PINMUX_MIO_PAD_ATTR_11_INVERT_11_BIT 0

Definition at line 577 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_11_KEEPER_EN_11_BIT

#define PINMUX_MIO_PAD_ATTR_11_KEEPER_EN_11_BIT 4

Definition at line 581 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_11_OD_EN_11_BIT

#define PINMUX_MIO_PAD_ATTR_11_OD_EN_11_BIT 6

Definition at line 583 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_11_PULL_EN_11_BIT

#define PINMUX_MIO_PAD_ATTR_11_PULL_EN_11_BIT 2

Definition at line 579 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_11_PULL_SELECT_11_BIT

#define PINMUX_MIO_PAD_ATTR_11_PULL_SELECT_11_BIT 3

Definition at line 580 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_11_REG_OFFSET

#define PINMUX_MIO_PAD_ATTR_11_REG_OFFSET 0xe0

Definition at line 575 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_11_REG_RESVAL

#define PINMUX_MIO_PAD_ATTR_11_REG_RESVAL 0x0u

Definition at line 576 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_11_SCHMITT_EN_11_BIT

#define PINMUX_MIO_PAD_ATTR_11_SCHMITT_EN_11_BIT 5

Definition at line 582 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_FIELD

#define PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_MASK, .index = PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_OFFSET })

Definition at line 587 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_MASK

#define PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_MASK 0x3u

Definition at line 585 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_OFFSET

#define PINMUX_MIO_PAD_ATTR_11_SLEW_RATE_11_OFFSET 16

Definition at line 586 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_11_VIRTUAL_OD_EN_11_BIT

#define PINMUX_MIO_PAD_ATTR_11_VIRTUAL_OD_EN_11_BIT 1

Definition at line 578 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_FIELD

#define PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_MASK, .index = PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_OFFSET })

Definition at line 391 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_MASK

#define PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_MASK 0xfu

Definition at line 389 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_OFFSET

#define PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_OFFSET 20

Definition at line 390 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_1_INPUT_DISABLE_1_BIT

#define PINMUX_MIO_PAD_ATTR_1_INPUT_DISABLE_1_BIT 7

Definition at line 384 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_1_INVERT_1_BIT

#define PINMUX_MIO_PAD_ATTR_1_INVERT_1_BIT 0

Definition at line 377 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_1_KEEPER_EN_1_BIT

#define PINMUX_MIO_PAD_ATTR_1_KEEPER_EN_1_BIT 4

Definition at line 381 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_1_OD_EN_1_BIT

#define PINMUX_MIO_PAD_ATTR_1_OD_EN_1_BIT 6

Definition at line 383 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_1_PULL_EN_1_BIT

#define PINMUX_MIO_PAD_ATTR_1_PULL_EN_1_BIT 2

Definition at line 379 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_1_PULL_SELECT_1_BIT

#define PINMUX_MIO_PAD_ATTR_1_PULL_SELECT_1_BIT 3

Definition at line 380 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_1_REG_OFFSET

#define PINMUX_MIO_PAD_ATTR_1_REG_OFFSET 0xb8

Definition at line 375 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_1_REG_RESVAL

#define PINMUX_MIO_PAD_ATTR_1_REG_RESVAL 0x0u

Definition at line 376 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_1_SCHMITT_EN_1_BIT

#define PINMUX_MIO_PAD_ATTR_1_SCHMITT_EN_1_BIT 5

Definition at line 382 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_FIELD

#define PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_MASK, .index = PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_OFFSET })

Definition at line 387 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_MASK

#define PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_MASK 0x3u

Definition at line 385 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_OFFSET

#define PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_OFFSET 16

Definition at line 386 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_1_VIRTUAL_OD_EN_1_BIT

#define PINMUX_MIO_PAD_ATTR_1_VIRTUAL_OD_EN_1_BIT 1

Definition at line 378 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_FIELD

#define PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_MASK, .index = PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_OFFSET })

Definition at line 411 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_MASK

#define PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_MASK 0xfu

Definition at line 409 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_OFFSET

#define PINMUX_MIO_PAD_ATTR_2_DRIVE_STRENGTH_2_OFFSET 20

Definition at line 410 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_2_INPUT_DISABLE_2_BIT

#define PINMUX_MIO_PAD_ATTR_2_INPUT_DISABLE_2_BIT 7

Definition at line 404 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_2_INVERT_2_BIT

#define PINMUX_MIO_PAD_ATTR_2_INVERT_2_BIT 0

Definition at line 397 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_2_KEEPER_EN_2_BIT

#define PINMUX_MIO_PAD_ATTR_2_KEEPER_EN_2_BIT 4

Definition at line 401 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_2_OD_EN_2_BIT

#define PINMUX_MIO_PAD_ATTR_2_OD_EN_2_BIT 6

Definition at line 403 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_2_PULL_EN_2_BIT

#define PINMUX_MIO_PAD_ATTR_2_PULL_EN_2_BIT 2

Definition at line 399 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_2_PULL_SELECT_2_BIT

#define PINMUX_MIO_PAD_ATTR_2_PULL_SELECT_2_BIT 3

Definition at line 400 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_2_REG_OFFSET

#define PINMUX_MIO_PAD_ATTR_2_REG_OFFSET 0xbc

Definition at line 395 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_2_REG_RESVAL

#define PINMUX_MIO_PAD_ATTR_2_REG_RESVAL 0x0u

Definition at line 396 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_2_SCHMITT_EN_2_BIT

#define PINMUX_MIO_PAD_ATTR_2_SCHMITT_EN_2_BIT 5

Definition at line 402 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_FIELD

#define PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_MASK, .index = PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_OFFSET })

Definition at line 407 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_MASK

#define PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_MASK 0x3u

Definition at line 405 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_OFFSET

#define PINMUX_MIO_PAD_ATTR_2_SLEW_RATE_2_OFFSET 16

Definition at line 406 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_2_VIRTUAL_OD_EN_2_BIT

#define PINMUX_MIO_PAD_ATTR_2_VIRTUAL_OD_EN_2_BIT 1

Definition at line 398 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_FIELD

#define PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_MASK, .index = PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_OFFSET })

Definition at line 431 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_MASK

#define PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_MASK 0xfu

Definition at line 429 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_OFFSET

#define PINMUX_MIO_PAD_ATTR_3_DRIVE_STRENGTH_3_OFFSET 20

Definition at line 430 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_3_INPUT_DISABLE_3_BIT

#define PINMUX_MIO_PAD_ATTR_3_INPUT_DISABLE_3_BIT 7

Definition at line 424 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_3_INVERT_3_BIT

#define PINMUX_MIO_PAD_ATTR_3_INVERT_3_BIT 0

Definition at line 417 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_3_KEEPER_EN_3_BIT

#define PINMUX_MIO_PAD_ATTR_3_KEEPER_EN_3_BIT 4

Definition at line 421 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_3_OD_EN_3_BIT

#define PINMUX_MIO_PAD_ATTR_3_OD_EN_3_BIT 6

Definition at line 423 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_3_PULL_EN_3_BIT

#define PINMUX_MIO_PAD_ATTR_3_PULL_EN_3_BIT 2

Definition at line 419 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_3_PULL_SELECT_3_BIT

#define PINMUX_MIO_PAD_ATTR_3_PULL_SELECT_3_BIT 3

Definition at line 420 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_3_REG_OFFSET

#define PINMUX_MIO_PAD_ATTR_3_REG_OFFSET 0xc0

Definition at line 415 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_3_REG_RESVAL

#define PINMUX_MIO_PAD_ATTR_3_REG_RESVAL 0x0u

Definition at line 416 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_3_SCHMITT_EN_3_BIT

#define PINMUX_MIO_PAD_ATTR_3_SCHMITT_EN_3_BIT 5

Definition at line 422 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_FIELD

#define PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_MASK, .index = PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_OFFSET })

Definition at line 427 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_MASK

#define PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_MASK 0x3u

Definition at line 425 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_OFFSET

#define PINMUX_MIO_PAD_ATTR_3_SLEW_RATE_3_OFFSET 16

Definition at line 426 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_3_VIRTUAL_OD_EN_3_BIT

#define PINMUX_MIO_PAD_ATTR_3_VIRTUAL_OD_EN_3_BIT 1

Definition at line 418 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_FIELD

#define PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_MASK, .index = PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_OFFSET })

Definition at line 451 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_MASK

#define PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_MASK 0xfu

Definition at line 449 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_OFFSET

#define PINMUX_MIO_PAD_ATTR_4_DRIVE_STRENGTH_4_OFFSET 20

Definition at line 450 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_4_INPUT_DISABLE_4_BIT

#define PINMUX_MIO_PAD_ATTR_4_INPUT_DISABLE_4_BIT 7

Definition at line 444 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_4_INVERT_4_BIT

#define PINMUX_MIO_PAD_ATTR_4_INVERT_4_BIT 0

Definition at line 437 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_4_KEEPER_EN_4_BIT

#define PINMUX_MIO_PAD_ATTR_4_KEEPER_EN_4_BIT 4

Definition at line 441 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_4_OD_EN_4_BIT

#define PINMUX_MIO_PAD_ATTR_4_OD_EN_4_BIT 6

Definition at line 443 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_4_PULL_EN_4_BIT

#define PINMUX_MIO_PAD_ATTR_4_PULL_EN_4_BIT 2

Definition at line 439 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_4_PULL_SELECT_4_BIT

#define PINMUX_MIO_PAD_ATTR_4_PULL_SELECT_4_BIT 3

Definition at line 440 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_4_REG_OFFSET

#define PINMUX_MIO_PAD_ATTR_4_REG_OFFSET 0xc4

Definition at line 435 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_4_REG_RESVAL

#define PINMUX_MIO_PAD_ATTR_4_REG_RESVAL 0x0u

Definition at line 436 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_4_SCHMITT_EN_4_BIT

#define PINMUX_MIO_PAD_ATTR_4_SCHMITT_EN_4_BIT 5

Definition at line 442 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_FIELD

#define PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_MASK, .index = PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_OFFSET })

Definition at line 447 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_MASK

#define PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_MASK 0x3u

Definition at line 445 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_OFFSET

#define PINMUX_MIO_PAD_ATTR_4_SLEW_RATE_4_OFFSET 16

Definition at line 446 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_4_VIRTUAL_OD_EN_4_BIT

#define PINMUX_MIO_PAD_ATTR_4_VIRTUAL_OD_EN_4_BIT 1

Definition at line 438 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_FIELD

#define PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_MASK, .index = PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_OFFSET })

Definition at line 471 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_MASK

#define PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_MASK 0xfu

Definition at line 469 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_OFFSET

#define PINMUX_MIO_PAD_ATTR_5_DRIVE_STRENGTH_5_OFFSET 20

Definition at line 470 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_5_INPUT_DISABLE_5_BIT

#define PINMUX_MIO_PAD_ATTR_5_INPUT_DISABLE_5_BIT 7

Definition at line 464 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_5_INVERT_5_BIT

#define PINMUX_MIO_PAD_ATTR_5_INVERT_5_BIT 0

Definition at line 457 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_5_KEEPER_EN_5_BIT

#define PINMUX_MIO_PAD_ATTR_5_KEEPER_EN_5_BIT 4

Definition at line 461 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_5_OD_EN_5_BIT

#define PINMUX_MIO_PAD_ATTR_5_OD_EN_5_BIT 6

Definition at line 463 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_5_PULL_EN_5_BIT

#define PINMUX_MIO_PAD_ATTR_5_PULL_EN_5_BIT 2

Definition at line 459 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_5_PULL_SELECT_5_BIT

#define PINMUX_MIO_PAD_ATTR_5_PULL_SELECT_5_BIT 3

Definition at line 460 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_5_REG_OFFSET

#define PINMUX_MIO_PAD_ATTR_5_REG_OFFSET 0xc8

Definition at line 455 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_5_REG_RESVAL

#define PINMUX_MIO_PAD_ATTR_5_REG_RESVAL 0x0u

Definition at line 456 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_5_SCHMITT_EN_5_BIT

#define PINMUX_MIO_PAD_ATTR_5_SCHMITT_EN_5_BIT 5

Definition at line 462 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_FIELD

#define PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_MASK, .index = PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_OFFSET })

Definition at line 467 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_MASK

#define PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_MASK 0x3u

Definition at line 465 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_OFFSET

#define PINMUX_MIO_PAD_ATTR_5_SLEW_RATE_5_OFFSET 16

Definition at line 466 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_5_VIRTUAL_OD_EN_5_BIT

#define PINMUX_MIO_PAD_ATTR_5_VIRTUAL_OD_EN_5_BIT 1

Definition at line 458 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_FIELD

#define PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_MASK, .index = PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_OFFSET })

Definition at line 491 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_MASK

#define PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_MASK 0xfu

Definition at line 489 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_OFFSET

#define PINMUX_MIO_PAD_ATTR_6_DRIVE_STRENGTH_6_OFFSET 20

Definition at line 490 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_6_INPUT_DISABLE_6_BIT

#define PINMUX_MIO_PAD_ATTR_6_INPUT_DISABLE_6_BIT 7

Definition at line 484 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_6_INVERT_6_BIT

#define PINMUX_MIO_PAD_ATTR_6_INVERT_6_BIT 0

Definition at line 477 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_6_KEEPER_EN_6_BIT

#define PINMUX_MIO_PAD_ATTR_6_KEEPER_EN_6_BIT 4

Definition at line 481 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_6_OD_EN_6_BIT

#define PINMUX_MIO_PAD_ATTR_6_OD_EN_6_BIT 6

Definition at line 483 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_6_PULL_EN_6_BIT

#define PINMUX_MIO_PAD_ATTR_6_PULL_EN_6_BIT 2

Definition at line 479 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_6_PULL_SELECT_6_BIT

#define PINMUX_MIO_PAD_ATTR_6_PULL_SELECT_6_BIT 3

Definition at line 480 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_6_REG_OFFSET

#define PINMUX_MIO_PAD_ATTR_6_REG_OFFSET 0xcc

Definition at line 475 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_6_REG_RESVAL

#define PINMUX_MIO_PAD_ATTR_6_REG_RESVAL 0x0u

Definition at line 476 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_6_SCHMITT_EN_6_BIT

#define PINMUX_MIO_PAD_ATTR_6_SCHMITT_EN_6_BIT 5

Definition at line 482 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_FIELD

#define PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_MASK, .index = PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_OFFSET })

Definition at line 487 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_MASK

#define PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_MASK 0x3u

Definition at line 485 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_OFFSET

#define PINMUX_MIO_PAD_ATTR_6_SLEW_RATE_6_OFFSET 16

Definition at line 486 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_6_VIRTUAL_OD_EN_6_BIT

#define PINMUX_MIO_PAD_ATTR_6_VIRTUAL_OD_EN_6_BIT 1

Definition at line 478 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_FIELD

#define PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_MASK, .index = PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_OFFSET })

Definition at line 511 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_MASK

#define PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_MASK 0xfu

Definition at line 509 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_OFFSET

#define PINMUX_MIO_PAD_ATTR_7_DRIVE_STRENGTH_7_OFFSET 20

Definition at line 510 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_7_INPUT_DISABLE_7_BIT

#define PINMUX_MIO_PAD_ATTR_7_INPUT_DISABLE_7_BIT 7

Definition at line 504 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_7_INVERT_7_BIT

#define PINMUX_MIO_PAD_ATTR_7_INVERT_7_BIT 0

Definition at line 497 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_7_KEEPER_EN_7_BIT

#define PINMUX_MIO_PAD_ATTR_7_KEEPER_EN_7_BIT 4

Definition at line 501 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_7_OD_EN_7_BIT

#define PINMUX_MIO_PAD_ATTR_7_OD_EN_7_BIT 6

Definition at line 503 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_7_PULL_EN_7_BIT

#define PINMUX_MIO_PAD_ATTR_7_PULL_EN_7_BIT 2

Definition at line 499 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_7_PULL_SELECT_7_BIT

#define PINMUX_MIO_PAD_ATTR_7_PULL_SELECT_7_BIT 3

Definition at line 500 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_7_REG_OFFSET

#define PINMUX_MIO_PAD_ATTR_7_REG_OFFSET 0xd0

Definition at line 495 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_7_REG_RESVAL

#define PINMUX_MIO_PAD_ATTR_7_REG_RESVAL 0x0u

Definition at line 496 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_7_SCHMITT_EN_7_BIT

#define PINMUX_MIO_PAD_ATTR_7_SCHMITT_EN_7_BIT 5

Definition at line 502 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_FIELD

#define PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_MASK, .index = PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_OFFSET })

Definition at line 507 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_MASK

#define PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_MASK 0x3u

Definition at line 505 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_OFFSET

#define PINMUX_MIO_PAD_ATTR_7_SLEW_RATE_7_OFFSET 16

Definition at line 506 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_7_VIRTUAL_OD_EN_7_BIT

#define PINMUX_MIO_PAD_ATTR_7_VIRTUAL_OD_EN_7_BIT 1

Definition at line 498 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_FIELD

#define PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_MASK, .index = PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_OFFSET })

Definition at line 531 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_MASK

#define PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_MASK 0xfu

Definition at line 529 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_OFFSET

#define PINMUX_MIO_PAD_ATTR_8_DRIVE_STRENGTH_8_OFFSET 20

Definition at line 530 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_8_INPUT_DISABLE_8_BIT

#define PINMUX_MIO_PAD_ATTR_8_INPUT_DISABLE_8_BIT 7

Definition at line 524 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_8_INVERT_8_BIT

#define PINMUX_MIO_PAD_ATTR_8_INVERT_8_BIT 0

Definition at line 517 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_8_KEEPER_EN_8_BIT

#define PINMUX_MIO_PAD_ATTR_8_KEEPER_EN_8_BIT 4

Definition at line 521 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_8_OD_EN_8_BIT

#define PINMUX_MIO_PAD_ATTR_8_OD_EN_8_BIT 6

Definition at line 523 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_8_PULL_EN_8_BIT

#define PINMUX_MIO_PAD_ATTR_8_PULL_EN_8_BIT 2

Definition at line 519 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_8_PULL_SELECT_8_BIT

#define PINMUX_MIO_PAD_ATTR_8_PULL_SELECT_8_BIT 3

Definition at line 520 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_8_REG_OFFSET

#define PINMUX_MIO_PAD_ATTR_8_REG_OFFSET 0xd4

Definition at line 515 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_8_REG_RESVAL

#define PINMUX_MIO_PAD_ATTR_8_REG_RESVAL 0x0u

Definition at line 516 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_8_SCHMITT_EN_8_BIT

#define PINMUX_MIO_PAD_ATTR_8_SCHMITT_EN_8_BIT 5

Definition at line 522 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_FIELD

#define PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_MASK, .index = PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_OFFSET })

Definition at line 527 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_MASK

#define PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_MASK 0x3u

Definition at line 525 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_OFFSET

#define PINMUX_MIO_PAD_ATTR_8_SLEW_RATE_8_OFFSET 16

Definition at line 526 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_8_VIRTUAL_OD_EN_8_BIT

#define PINMUX_MIO_PAD_ATTR_8_VIRTUAL_OD_EN_8_BIT 1

Definition at line 518 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_FIELD

#define PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_MASK, .index = PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_OFFSET })

Definition at line 551 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_MASK

#define PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_MASK 0xfu

Definition at line 549 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_OFFSET

#define PINMUX_MIO_PAD_ATTR_9_DRIVE_STRENGTH_9_OFFSET 20

Definition at line 550 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_9_INPUT_DISABLE_9_BIT

#define PINMUX_MIO_PAD_ATTR_9_INPUT_DISABLE_9_BIT 7

Definition at line 544 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_9_INVERT_9_BIT

#define PINMUX_MIO_PAD_ATTR_9_INVERT_9_BIT 0

Definition at line 537 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_9_KEEPER_EN_9_BIT

#define PINMUX_MIO_PAD_ATTR_9_KEEPER_EN_9_BIT 4

Definition at line 541 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_9_OD_EN_9_BIT

#define PINMUX_MIO_PAD_ATTR_9_OD_EN_9_BIT 6

Definition at line 543 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_9_PULL_EN_9_BIT

#define PINMUX_MIO_PAD_ATTR_9_PULL_EN_9_BIT 2

Definition at line 539 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_9_PULL_SELECT_9_BIT

#define PINMUX_MIO_PAD_ATTR_9_PULL_SELECT_9_BIT 3

Definition at line 540 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_9_REG_OFFSET

#define PINMUX_MIO_PAD_ATTR_9_REG_OFFSET 0xd8

Definition at line 535 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_9_REG_RESVAL

#define PINMUX_MIO_PAD_ATTR_9_REG_RESVAL 0x0u

Definition at line 536 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_9_SCHMITT_EN_9_BIT

#define PINMUX_MIO_PAD_ATTR_9_SCHMITT_EN_9_BIT 5

Definition at line 542 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_FIELD

#define PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_MASK, .index = PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_OFFSET })

Definition at line 547 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_MASK

#define PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_MASK 0x3u

Definition at line 545 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_OFFSET

#define PINMUX_MIO_PAD_ATTR_9_SLEW_RATE_9_OFFSET 16

Definition at line 546 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_9_VIRTUAL_OD_EN_9_BIT

#define PINMUX_MIO_PAD_ATTR_9_VIRTUAL_OD_EN_9_BIT 1

Definition at line 538 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_DRIVE_STRENGTH_FIELD_WIDTH

#define PINMUX_MIO_PAD_ATTR_DRIVE_STRENGTH_FIELD_WIDTH 4

Definition at line 349 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_INPUT_DISABLE_FIELD_WIDTH

#define PINMUX_MIO_PAD_ATTR_INPUT_DISABLE_FIELD_WIDTH 1

Definition at line 347 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_INVERT_FIELD_WIDTH

#define PINMUX_MIO_PAD_ATTR_INVERT_FIELD_WIDTH 1

Definition at line 340 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_KEEPER_EN_FIELD_WIDTH

#define PINMUX_MIO_PAD_ATTR_KEEPER_EN_FIELD_WIDTH 1

Definition at line 344 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_MULTIREG_COUNT

#define PINMUX_MIO_PAD_ATTR_MULTIREG_COUNT 12

Definition at line 350 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_OD_EN_FIELD_WIDTH

#define PINMUX_MIO_PAD_ATTR_OD_EN_FIELD_WIDTH 1

Definition at line 346 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_PULL_EN_FIELD_WIDTH

#define PINMUX_MIO_PAD_ATTR_PULL_EN_FIELD_WIDTH 1

Definition at line 342 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_PULL_SELECT_FIELD_WIDTH

#define PINMUX_MIO_PAD_ATTR_PULL_SELECT_FIELD_WIDTH 1

Definition at line 343 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_0_EN_0_BIT

#define PINMUX_MIO_PAD_ATTR_REGWEN_0_EN_0_BIT 0

Definition at line 282 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_0_REG_OFFSET

#define PINMUX_MIO_PAD_ATTR_REGWEN_0_REG_OFFSET 0x84

Definition at line 280 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_0_REG_RESVAL

#define PINMUX_MIO_PAD_ATTR_REGWEN_0_REG_RESVAL 0x1u

Definition at line 281 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_10_EN_10_BIT

#define PINMUX_MIO_PAD_ATTR_REGWEN_10_EN_10_BIT 0

Definition at line 332 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_10_REG_OFFSET

#define PINMUX_MIO_PAD_ATTR_REGWEN_10_REG_OFFSET 0xac

Definition at line 330 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_10_REG_RESVAL

#define PINMUX_MIO_PAD_ATTR_REGWEN_10_REG_RESVAL 0x1u

Definition at line 331 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_11_EN_11_BIT

#define PINMUX_MIO_PAD_ATTR_REGWEN_11_EN_11_BIT 0

Definition at line 337 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_11_REG_OFFSET

#define PINMUX_MIO_PAD_ATTR_REGWEN_11_REG_OFFSET 0xb0

Definition at line 335 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_11_REG_RESVAL

#define PINMUX_MIO_PAD_ATTR_REGWEN_11_REG_RESVAL 0x1u

Definition at line 336 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_1_EN_1_BIT

#define PINMUX_MIO_PAD_ATTR_REGWEN_1_EN_1_BIT 0

Definition at line 287 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_1_REG_OFFSET

#define PINMUX_MIO_PAD_ATTR_REGWEN_1_REG_OFFSET 0x88

Definition at line 285 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_1_REG_RESVAL

#define PINMUX_MIO_PAD_ATTR_REGWEN_1_REG_RESVAL 0x1u

Definition at line 286 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_2_EN_2_BIT

#define PINMUX_MIO_PAD_ATTR_REGWEN_2_EN_2_BIT 0

Definition at line 292 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_2_REG_OFFSET

#define PINMUX_MIO_PAD_ATTR_REGWEN_2_REG_OFFSET 0x8c

Definition at line 290 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_2_REG_RESVAL

#define PINMUX_MIO_PAD_ATTR_REGWEN_2_REG_RESVAL 0x1u

Definition at line 291 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_3_EN_3_BIT

#define PINMUX_MIO_PAD_ATTR_REGWEN_3_EN_3_BIT 0

Definition at line 297 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_3_REG_OFFSET

#define PINMUX_MIO_PAD_ATTR_REGWEN_3_REG_OFFSET 0x90

Definition at line 295 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_3_REG_RESVAL

#define PINMUX_MIO_PAD_ATTR_REGWEN_3_REG_RESVAL 0x1u

Definition at line 296 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_4_EN_4_BIT

#define PINMUX_MIO_PAD_ATTR_REGWEN_4_EN_4_BIT 0

Definition at line 302 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_4_REG_OFFSET

#define PINMUX_MIO_PAD_ATTR_REGWEN_4_REG_OFFSET 0x94

Definition at line 300 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_4_REG_RESVAL

#define PINMUX_MIO_PAD_ATTR_REGWEN_4_REG_RESVAL 0x1u

Definition at line 301 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_5_EN_5_BIT

#define PINMUX_MIO_PAD_ATTR_REGWEN_5_EN_5_BIT 0

Definition at line 307 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_5_REG_OFFSET

#define PINMUX_MIO_PAD_ATTR_REGWEN_5_REG_OFFSET 0x98

Definition at line 305 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_5_REG_RESVAL

#define PINMUX_MIO_PAD_ATTR_REGWEN_5_REG_RESVAL 0x1u

Definition at line 306 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_6_EN_6_BIT

#define PINMUX_MIO_PAD_ATTR_REGWEN_6_EN_6_BIT 0

Definition at line 312 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_6_REG_OFFSET

#define PINMUX_MIO_PAD_ATTR_REGWEN_6_REG_OFFSET 0x9c

Definition at line 310 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_6_REG_RESVAL

#define PINMUX_MIO_PAD_ATTR_REGWEN_6_REG_RESVAL 0x1u

Definition at line 311 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_7_EN_7_BIT

#define PINMUX_MIO_PAD_ATTR_REGWEN_7_EN_7_BIT 0

Definition at line 317 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_7_REG_OFFSET

#define PINMUX_MIO_PAD_ATTR_REGWEN_7_REG_OFFSET 0xa0

Definition at line 315 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_7_REG_RESVAL

#define PINMUX_MIO_PAD_ATTR_REGWEN_7_REG_RESVAL 0x1u

Definition at line 316 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_8_EN_8_BIT

#define PINMUX_MIO_PAD_ATTR_REGWEN_8_EN_8_BIT 0

Definition at line 322 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_8_REG_OFFSET

#define PINMUX_MIO_PAD_ATTR_REGWEN_8_REG_OFFSET 0xa4

Definition at line 320 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_8_REG_RESVAL

#define PINMUX_MIO_PAD_ATTR_REGWEN_8_REG_RESVAL 0x1u

Definition at line 321 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_9_EN_9_BIT

#define PINMUX_MIO_PAD_ATTR_REGWEN_9_EN_9_BIT 0

Definition at line 327 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_9_REG_OFFSET

#define PINMUX_MIO_PAD_ATTR_REGWEN_9_REG_OFFSET 0xa8

Definition at line 325 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_9_REG_RESVAL

#define PINMUX_MIO_PAD_ATTR_REGWEN_9_REG_RESVAL 0x1u

Definition at line 326 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_EN_FIELD_WIDTH

#define PINMUX_MIO_PAD_ATTR_REGWEN_EN_FIELD_WIDTH 1

Definition at line 276 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_REGWEN_MULTIREG_COUNT

#define PINMUX_MIO_PAD_ATTR_REGWEN_MULTIREG_COUNT 12

Definition at line 277 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_SCHMITT_EN_FIELD_WIDTH

#define PINMUX_MIO_PAD_ATTR_SCHMITT_EN_FIELD_WIDTH 1

Definition at line 345 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_SLEW_RATE_FIELD_WIDTH

#define PINMUX_MIO_PAD_ATTR_SLEW_RATE_FIELD_WIDTH 2

Definition at line 348 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_ATTR_VIRTUAL_OD_EN_FIELD_WIDTH

#define PINMUX_MIO_PAD_ATTR_VIRTUAL_OD_EN_FIELD_WIDTH 1

Definition at line 341 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_0_EN_0_BIT

#define PINMUX_MIO_PAD_SLEEP_EN_0_EN_0_BIT 0

Definition at line 2531 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_0_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_EN_0_REG_OFFSET 0x360

Definition at line 2529 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_0_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_EN_0_REG_RESVAL 0x0u

Definition at line 2530 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_10_EN_10_BIT

#define PINMUX_MIO_PAD_SLEEP_EN_10_EN_10_BIT 0

Definition at line 2581 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_10_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_EN_10_REG_OFFSET 0x388

Definition at line 2579 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_10_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_EN_10_REG_RESVAL 0x0u

Definition at line 2580 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_11_EN_11_BIT

#define PINMUX_MIO_PAD_SLEEP_EN_11_EN_11_BIT 0

Definition at line 2586 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_11_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_EN_11_REG_OFFSET 0x38c

Definition at line 2584 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_11_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_EN_11_REG_RESVAL 0x0u

Definition at line 2585 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_1_EN_1_BIT

#define PINMUX_MIO_PAD_SLEEP_EN_1_EN_1_BIT 0

Definition at line 2536 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_1_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_EN_1_REG_OFFSET 0x364

Definition at line 2534 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_1_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_EN_1_REG_RESVAL 0x0u

Definition at line 2535 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_2_EN_2_BIT

#define PINMUX_MIO_PAD_SLEEP_EN_2_EN_2_BIT 0

Definition at line 2541 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_2_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_EN_2_REG_OFFSET 0x368

Definition at line 2539 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_2_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_EN_2_REG_RESVAL 0x0u

Definition at line 2540 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_3_EN_3_BIT

#define PINMUX_MIO_PAD_SLEEP_EN_3_EN_3_BIT 0

Definition at line 2546 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_3_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_EN_3_REG_OFFSET 0x36c

Definition at line 2544 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_3_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_EN_3_REG_RESVAL 0x0u

Definition at line 2545 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_4_EN_4_BIT

#define PINMUX_MIO_PAD_SLEEP_EN_4_EN_4_BIT 0

Definition at line 2551 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_4_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_EN_4_REG_OFFSET 0x370

Definition at line 2549 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_4_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_EN_4_REG_RESVAL 0x0u

Definition at line 2550 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_5_EN_5_BIT

#define PINMUX_MIO_PAD_SLEEP_EN_5_EN_5_BIT 0

Definition at line 2556 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_5_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_EN_5_REG_OFFSET 0x374

Definition at line 2554 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_5_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_EN_5_REG_RESVAL 0x0u

Definition at line 2555 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_6_EN_6_BIT

#define PINMUX_MIO_PAD_SLEEP_EN_6_EN_6_BIT 0

Definition at line 2561 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_6_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_EN_6_REG_OFFSET 0x378

Definition at line 2559 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_6_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_EN_6_REG_RESVAL 0x0u

Definition at line 2560 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_7_EN_7_BIT

#define PINMUX_MIO_PAD_SLEEP_EN_7_EN_7_BIT 0

Definition at line 2566 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_7_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_EN_7_REG_OFFSET 0x37c

Definition at line 2564 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_7_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_EN_7_REG_RESVAL 0x0u

Definition at line 2565 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_8_EN_8_BIT

#define PINMUX_MIO_PAD_SLEEP_EN_8_EN_8_BIT 0

Definition at line 2571 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_8_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_EN_8_REG_OFFSET 0x380

Definition at line 2569 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_8_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_EN_8_REG_RESVAL 0x0u

Definition at line 2570 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_9_EN_9_BIT

#define PINMUX_MIO_PAD_SLEEP_EN_9_EN_9_BIT 0

Definition at line 2576 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_9_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_EN_9_REG_OFFSET 0x384

Definition at line 2574 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_9_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_EN_9_REG_RESVAL 0x0u

Definition at line 2575 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_EN_FIELD_WIDTH

#define PINMUX_MIO_PAD_SLEEP_EN_EN_FIELD_WIDTH 1

Definition at line 2525 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_EN_MULTIREG_COUNT

#define PINMUX_MIO_PAD_SLEEP_EN_MULTIREG_COUNT 12

Definition at line 2526 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_FIELD

#define PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_OFFSET })

Definition at line 2597 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_MASK

#define PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_MASK 0x3u

Definition at line 2595 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_OFFSET

#define PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_OFFSET 0

Definition at line 2596 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_HIGH_Z

#define PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_HIGH_Z 0x2

Definition at line 2601 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_KEEP

#define PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_KEEP 0x3

Definition at line 2602 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_TIE_HIGH

#define PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_TIE_HIGH 0x1

Definition at line 2600 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_TIE_LOW

#define PINMUX_MIO_PAD_SLEEP_MODE_0_OUT_0_VALUE_TIE_LOW 0x0

Definition at line 2599 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_0_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_MODE_0_REG_OFFSET 0x390

Definition at line 2593 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_0_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_MODE_0_REG_RESVAL 0x2u

Definition at line 2594 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_10_OUT_10_FIELD

#define PINMUX_MIO_PAD_SLEEP_MODE_10_OUT_10_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_10_OUT_10_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_10_OUT_10_OFFSET })

Definition at line 2681 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_10_OUT_10_MASK

#define PINMUX_MIO_PAD_SLEEP_MODE_10_OUT_10_MASK 0x3u

Definition at line 2679 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_10_OUT_10_OFFSET

#define PINMUX_MIO_PAD_SLEEP_MODE_10_OUT_10_OFFSET 0

Definition at line 2680 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_10_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_MODE_10_REG_OFFSET 0x3b8

Definition at line 2677 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_10_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_MODE_10_REG_RESVAL 0x2u

Definition at line 2678 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_11_OUT_11_FIELD

#define PINMUX_MIO_PAD_SLEEP_MODE_11_OUT_11_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_11_OUT_11_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_11_OUT_11_OFFSET })

Definition at line 2689 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_11_OUT_11_MASK

#define PINMUX_MIO_PAD_SLEEP_MODE_11_OUT_11_MASK 0x3u

Definition at line 2687 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_11_OUT_11_OFFSET

#define PINMUX_MIO_PAD_SLEEP_MODE_11_OUT_11_OFFSET 0

Definition at line 2688 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_11_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_MODE_11_REG_OFFSET 0x3bc

Definition at line 2685 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_11_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_MODE_11_REG_RESVAL 0x2u

Definition at line 2686 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_1_OUT_1_FIELD

#define PINMUX_MIO_PAD_SLEEP_MODE_1_OUT_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_1_OUT_1_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_1_OUT_1_OFFSET })

Definition at line 2609 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_1_OUT_1_MASK

#define PINMUX_MIO_PAD_SLEEP_MODE_1_OUT_1_MASK 0x3u

Definition at line 2607 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_1_OUT_1_OFFSET

#define PINMUX_MIO_PAD_SLEEP_MODE_1_OUT_1_OFFSET 0

Definition at line 2608 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_1_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_MODE_1_REG_OFFSET 0x394

Definition at line 2605 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_1_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_MODE_1_REG_RESVAL 0x2u

Definition at line 2606 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_2_OUT_2_FIELD

#define PINMUX_MIO_PAD_SLEEP_MODE_2_OUT_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_2_OUT_2_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_2_OUT_2_OFFSET })

Definition at line 2617 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_2_OUT_2_MASK

#define PINMUX_MIO_PAD_SLEEP_MODE_2_OUT_2_MASK 0x3u

Definition at line 2615 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_2_OUT_2_OFFSET

#define PINMUX_MIO_PAD_SLEEP_MODE_2_OUT_2_OFFSET 0

Definition at line 2616 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_2_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_MODE_2_REG_OFFSET 0x398

Definition at line 2613 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_2_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_MODE_2_REG_RESVAL 0x2u

Definition at line 2614 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_3_OUT_3_FIELD

#define PINMUX_MIO_PAD_SLEEP_MODE_3_OUT_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_3_OUT_3_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_3_OUT_3_OFFSET })

Definition at line 2625 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_3_OUT_3_MASK

#define PINMUX_MIO_PAD_SLEEP_MODE_3_OUT_3_MASK 0x3u

Definition at line 2623 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_3_OUT_3_OFFSET

#define PINMUX_MIO_PAD_SLEEP_MODE_3_OUT_3_OFFSET 0

Definition at line 2624 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_3_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_MODE_3_REG_OFFSET 0x39c

Definition at line 2621 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_3_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_MODE_3_REG_RESVAL 0x2u

Definition at line 2622 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_4_OUT_4_FIELD

#define PINMUX_MIO_PAD_SLEEP_MODE_4_OUT_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_4_OUT_4_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_4_OUT_4_OFFSET })

Definition at line 2633 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_4_OUT_4_MASK

#define PINMUX_MIO_PAD_SLEEP_MODE_4_OUT_4_MASK 0x3u

Definition at line 2631 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_4_OUT_4_OFFSET

#define PINMUX_MIO_PAD_SLEEP_MODE_4_OUT_4_OFFSET 0

Definition at line 2632 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_4_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_MODE_4_REG_OFFSET 0x3a0

Definition at line 2629 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_4_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_MODE_4_REG_RESVAL 0x2u

Definition at line 2630 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_5_OUT_5_FIELD

#define PINMUX_MIO_PAD_SLEEP_MODE_5_OUT_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_5_OUT_5_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_5_OUT_5_OFFSET })

Definition at line 2641 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_5_OUT_5_MASK

#define PINMUX_MIO_PAD_SLEEP_MODE_5_OUT_5_MASK 0x3u

Definition at line 2639 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_5_OUT_5_OFFSET

#define PINMUX_MIO_PAD_SLEEP_MODE_5_OUT_5_OFFSET 0

Definition at line 2640 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_5_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_MODE_5_REG_OFFSET 0x3a4

Definition at line 2637 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_5_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_MODE_5_REG_RESVAL 0x2u

Definition at line 2638 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_6_OUT_6_FIELD

#define PINMUX_MIO_PAD_SLEEP_MODE_6_OUT_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_6_OUT_6_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_6_OUT_6_OFFSET })

Definition at line 2649 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_6_OUT_6_MASK

#define PINMUX_MIO_PAD_SLEEP_MODE_6_OUT_6_MASK 0x3u

Definition at line 2647 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_6_OUT_6_OFFSET

#define PINMUX_MIO_PAD_SLEEP_MODE_6_OUT_6_OFFSET 0

Definition at line 2648 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_6_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_MODE_6_REG_OFFSET 0x3a8

Definition at line 2645 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_6_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_MODE_6_REG_RESVAL 0x2u

Definition at line 2646 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_7_OUT_7_FIELD

#define PINMUX_MIO_PAD_SLEEP_MODE_7_OUT_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_7_OUT_7_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_7_OUT_7_OFFSET })

Definition at line 2657 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_7_OUT_7_MASK

#define PINMUX_MIO_PAD_SLEEP_MODE_7_OUT_7_MASK 0x3u

Definition at line 2655 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_7_OUT_7_OFFSET

#define PINMUX_MIO_PAD_SLEEP_MODE_7_OUT_7_OFFSET 0

Definition at line 2656 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_7_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_MODE_7_REG_OFFSET 0x3ac

Definition at line 2653 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_7_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_MODE_7_REG_RESVAL 0x2u

Definition at line 2654 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_8_OUT_8_FIELD

#define PINMUX_MIO_PAD_SLEEP_MODE_8_OUT_8_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_8_OUT_8_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_8_OUT_8_OFFSET })

Definition at line 2665 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_8_OUT_8_MASK

#define PINMUX_MIO_PAD_SLEEP_MODE_8_OUT_8_MASK 0x3u

Definition at line 2663 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_8_OUT_8_OFFSET

#define PINMUX_MIO_PAD_SLEEP_MODE_8_OUT_8_OFFSET 0

Definition at line 2664 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_8_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_MODE_8_REG_OFFSET 0x3b0

Definition at line 2661 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_8_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_MODE_8_REG_RESVAL 0x2u

Definition at line 2662 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_9_OUT_9_FIELD

#define PINMUX_MIO_PAD_SLEEP_MODE_9_OUT_9_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PAD_SLEEP_MODE_9_OUT_9_MASK, .index = PINMUX_MIO_PAD_SLEEP_MODE_9_OUT_9_OFFSET })

Definition at line 2673 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_9_OUT_9_MASK

#define PINMUX_MIO_PAD_SLEEP_MODE_9_OUT_9_MASK 0x3u

Definition at line 2671 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_9_OUT_9_OFFSET

#define PINMUX_MIO_PAD_SLEEP_MODE_9_OUT_9_OFFSET 0

Definition at line 2672 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_9_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_MODE_9_REG_OFFSET 0x3b4

Definition at line 2669 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_9_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_MODE_9_REG_RESVAL 0x2u

Definition at line 2670 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_MULTIREG_COUNT

#define PINMUX_MIO_PAD_SLEEP_MODE_MULTIREG_COUNT 12

Definition at line 2590 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_MODE_OUT_FIELD_WIDTH

#define PINMUX_MIO_PAD_SLEEP_MODE_OUT_FIELD_WIDTH 2

Definition at line 2589 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_0_EN_0_BIT

#define PINMUX_MIO_PAD_SLEEP_REGWEN_0_EN_0_BIT 0

Definition at line 2467 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_0_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_REGWEN_0_REG_OFFSET 0x330

Definition at line 2465 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_0_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_REGWEN_0_REG_RESVAL 0x1u

Definition at line 2466 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_10_EN_10_BIT

#define PINMUX_MIO_PAD_SLEEP_REGWEN_10_EN_10_BIT 0

Definition at line 2517 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_10_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_REGWEN_10_REG_OFFSET 0x358

Definition at line 2515 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_10_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_REGWEN_10_REG_RESVAL 0x1u

Definition at line 2516 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_11_EN_11_BIT

#define PINMUX_MIO_PAD_SLEEP_REGWEN_11_EN_11_BIT 0

Definition at line 2522 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_11_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_REGWEN_11_REG_OFFSET 0x35c

Definition at line 2520 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_11_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_REGWEN_11_REG_RESVAL 0x1u

Definition at line 2521 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_1_EN_1_BIT

#define PINMUX_MIO_PAD_SLEEP_REGWEN_1_EN_1_BIT 0

Definition at line 2472 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_1_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_REGWEN_1_REG_OFFSET 0x334

Definition at line 2470 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_1_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_REGWEN_1_REG_RESVAL 0x1u

Definition at line 2471 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_2_EN_2_BIT

#define PINMUX_MIO_PAD_SLEEP_REGWEN_2_EN_2_BIT 0

Definition at line 2477 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_2_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_REGWEN_2_REG_OFFSET 0x338

Definition at line 2475 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_2_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_REGWEN_2_REG_RESVAL 0x1u

Definition at line 2476 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_3_EN_3_BIT

#define PINMUX_MIO_PAD_SLEEP_REGWEN_3_EN_3_BIT 0

Definition at line 2482 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_3_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_REGWEN_3_REG_OFFSET 0x33c

Definition at line 2480 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_3_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_REGWEN_3_REG_RESVAL 0x1u

Definition at line 2481 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_4_EN_4_BIT

#define PINMUX_MIO_PAD_SLEEP_REGWEN_4_EN_4_BIT 0

Definition at line 2487 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_4_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_REGWEN_4_REG_OFFSET 0x340

Definition at line 2485 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_4_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_REGWEN_4_REG_RESVAL 0x1u

Definition at line 2486 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_5_EN_5_BIT

#define PINMUX_MIO_PAD_SLEEP_REGWEN_5_EN_5_BIT 0

Definition at line 2492 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_5_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_REGWEN_5_REG_OFFSET 0x344

Definition at line 2490 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_5_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_REGWEN_5_REG_RESVAL 0x1u

Definition at line 2491 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_6_EN_6_BIT

#define PINMUX_MIO_PAD_SLEEP_REGWEN_6_EN_6_BIT 0

Definition at line 2497 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_6_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_REGWEN_6_REG_OFFSET 0x348

Definition at line 2495 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_6_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_REGWEN_6_REG_RESVAL 0x1u

Definition at line 2496 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_7_EN_7_BIT

#define PINMUX_MIO_PAD_SLEEP_REGWEN_7_EN_7_BIT 0

Definition at line 2502 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_7_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_REGWEN_7_REG_OFFSET 0x34c

Definition at line 2500 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_7_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_REGWEN_7_REG_RESVAL 0x1u

Definition at line 2501 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_8_EN_8_BIT

#define PINMUX_MIO_PAD_SLEEP_REGWEN_8_EN_8_BIT 0

Definition at line 2507 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_8_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_REGWEN_8_REG_OFFSET 0x350

Definition at line 2505 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_8_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_REGWEN_8_REG_RESVAL 0x1u

Definition at line 2506 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_9_EN_9_BIT

#define PINMUX_MIO_PAD_SLEEP_REGWEN_9_EN_9_BIT 0

Definition at line 2512 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_9_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_REGWEN_9_REG_OFFSET 0x354

Definition at line 2510 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_9_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_REGWEN_9_REG_RESVAL 0x1u

Definition at line 2511 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_EN_FIELD_WIDTH

#define PINMUX_MIO_PAD_SLEEP_REGWEN_EN_FIELD_WIDTH 1

Definition at line 2461 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_REGWEN_MULTIREG_COUNT

#define PINMUX_MIO_PAD_SLEEP_REGWEN_MULTIREG_COUNT 12

Definition at line 2462 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_STATUS_EN_0_BIT

#define PINMUX_MIO_PAD_SLEEP_STATUS_EN_0_BIT 0

Definition at line 2446 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_STATUS_EN_10_BIT

#define PINMUX_MIO_PAD_SLEEP_STATUS_EN_10_BIT 10

Definition at line 2456 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_STATUS_EN_11_BIT

#define PINMUX_MIO_PAD_SLEEP_STATUS_EN_11_BIT 11

Definition at line 2457 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_STATUS_EN_1_BIT

#define PINMUX_MIO_PAD_SLEEP_STATUS_EN_1_BIT 1

Definition at line 2447 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_STATUS_EN_2_BIT

#define PINMUX_MIO_PAD_SLEEP_STATUS_EN_2_BIT 2

Definition at line 2448 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_STATUS_EN_3_BIT

#define PINMUX_MIO_PAD_SLEEP_STATUS_EN_3_BIT 3

Definition at line 2449 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_STATUS_EN_4_BIT

#define PINMUX_MIO_PAD_SLEEP_STATUS_EN_4_BIT 4

Definition at line 2450 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_STATUS_EN_5_BIT

#define PINMUX_MIO_PAD_SLEEP_STATUS_EN_5_BIT 5

Definition at line 2451 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_STATUS_EN_6_BIT

#define PINMUX_MIO_PAD_SLEEP_STATUS_EN_6_BIT 6

Definition at line 2452 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_STATUS_EN_7_BIT

#define PINMUX_MIO_PAD_SLEEP_STATUS_EN_7_BIT 7

Definition at line 2453 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_STATUS_EN_8_BIT

#define PINMUX_MIO_PAD_SLEEP_STATUS_EN_8_BIT 8

Definition at line 2454 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_STATUS_EN_9_BIT

#define PINMUX_MIO_PAD_SLEEP_STATUS_EN_9_BIT 9

Definition at line 2455 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_STATUS_EN_FIELD_WIDTH

#define PINMUX_MIO_PAD_SLEEP_STATUS_EN_FIELD_WIDTH 1

Definition at line 2440 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_STATUS_MULTIREG_COUNT

#define PINMUX_MIO_PAD_SLEEP_STATUS_MULTIREG_COUNT 1

Definition at line 2441 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_STATUS_REG_OFFSET

#define PINMUX_MIO_PAD_SLEEP_STATUS_REG_OFFSET 0x32c

Definition at line 2444 of file pinmux_regs.h.

◆ PINMUX_MIO_PAD_SLEEP_STATUS_REG_RESVAL

#define PINMUX_MIO_PAD_SLEEP_STATUS_REG_RESVAL 0x0u

Definition at line 2445 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_0_IN_0_FIELD

#define PINMUX_MIO_PERIPH_INSEL_0_IN_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_0_IN_0_MASK, .index = PINMUX_MIO_PERIPH_INSEL_0_IN_0_OFFSET })

Definition at line 83 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_0_IN_0_MASK

#define PINMUX_MIO_PERIPH_INSEL_0_IN_0_MASK 0xfu

Definition at line 81 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_0_IN_0_OFFSET

#define PINMUX_MIO_PERIPH_INSEL_0_IN_0_OFFSET 0

Definition at line 82 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_0_REG_OFFSET

#define PINMUX_MIO_PERIPH_INSEL_0_REG_OFFSET 0x14

Definition at line 79 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_0_REG_RESVAL

#define PINMUX_MIO_PERIPH_INSEL_0_REG_RESVAL 0x0u

Definition at line 80 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_1_IN_1_FIELD

#define PINMUX_MIO_PERIPH_INSEL_1_IN_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_1_IN_1_MASK, .index = PINMUX_MIO_PERIPH_INSEL_1_IN_1_OFFSET })

Definition at line 91 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_1_IN_1_MASK

#define PINMUX_MIO_PERIPH_INSEL_1_IN_1_MASK 0xfu

Definition at line 89 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_1_IN_1_OFFSET

#define PINMUX_MIO_PERIPH_INSEL_1_IN_1_OFFSET 0

Definition at line 90 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_1_REG_OFFSET

#define PINMUX_MIO_PERIPH_INSEL_1_REG_OFFSET 0x18

Definition at line 87 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_1_REG_RESVAL

#define PINMUX_MIO_PERIPH_INSEL_1_REG_RESVAL 0x0u

Definition at line 88 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_2_IN_2_FIELD

#define PINMUX_MIO_PERIPH_INSEL_2_IN_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_2_IN_2_MASK, .index = PINMUX_MIO_PERIPH_INSEL_2_IN_2_OFFSET })

Definition at line 99 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_2_IN_2_MASK

#define PINMUX_MIO_PERIPH_INSEL_2_IN_2_MASK 0xfu

Definition at line 97 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_2_IN_2_OFFSET

#define PINMUX_MIO_PERIPH_INSEL_2_IN_2_OFFSET 0

Definition at line 98 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_2_REG_OFFSET

#define PINMUX_MIO_PERIPH_INSEL_2_REG_OFFSET 0x1c

Definition at line 95 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_2_REG_RESVAL

#define PINMUX_MIO_PERIPH_INSEL_2_REG_RESVAL 0x0u

Definition at line 96 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_3_IN_3_FIELD

#define PINMUX_MIO_PERIPH_INSEL_3_IN_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_MIO_PERIPH_INSEL_3_IN_3_MASK, .index = PINMUX_MIO_PERIPH_INSEL_3_IN_3_OFFSET })

Definition at line 107 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_3_IN_3_MASK

#define PINMUX_MIO_PERIPH_INSEL_3_IN_3_MASK 0xfu

Definition at line 105 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_3_IN_3_OFFSET

#define PINMUX_MIO_PERIPH_INSEL_3_IN_3_OFFSET 0

Definition at line 106 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_3_REG_OFFSET

#define PINMUX_MIO_PERIPH_INSEL_3_REG_OFFSET 0x20

Definition at line 103 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_3_REG_RESVAL

#define PINMUX_MIO_PERIPH_INSEL_3_REG_RESVAL 0x0u

Definition at line 104 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_IN_FIELD_WIDTH

#define PINMUX_MIO_PERIPH_INSEL_IN_FIELD_WIDTH 4

Definition at line 75 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_MULTIREG_COUNT

#define PINMUX_MIO_PERIPH_INSEL_MULTIREG_COUNT 4

Definition at line 76 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_REGWEN_0_EN_0_BIT

#define PINMUX_MIO_PERIPH_INSEL_REGWEN_0_EN_0_BIT 0

Definition at line 56 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_REGWEN_0_REG_OFFSET

#define PINMUX_MIO_PERIPH_INSEL_REGWEN_0_REG_OFFSET 0x4

Definition at line 54 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_REGWEN_0_REG_RESVAL

#define PINMUX_MIO_PERIPH_INSEL_REGWEN_0_REG_RESVAL 0x1u

Definition at line 55 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_REGWEN_1_EN_1_BIT

#define PINMUX_MIO_PERIPH_INSEL_REGWEN_1_EN_1_BIT 0

Definition at line 61 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_REGWEN_1_REG_OFFSET

#define PINMUX_MIO_PERIPH_INSEL_REGWEN_1_REG_OFFSET 0x8

Definition at line 59 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_REGWEN_1_REG_RESVAL

#define PINMUX_MIO_PERIPH_INSEL_REGWEN_1_REG_RESVAL 0x1u

Definition at line 60 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_REGWEN_2_EN_2_BIT

#define PINMUX_MIO_PERIPH_INSEL_REGWEN_2_EN_2_BIT 0

Definition at line 66 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_REGWEN_2_REG_OFFSET

#define PINMUX_MIO_PERIPH_INSEL_REGWEN_2_REG_OFFSET 0xc

Definition at line 64 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_REGWEN_2_REG_RESVAL

#define PINMUX_MIO_PERIPH_INSEL_REGWEN_2_REG_RESVAL 0x1u

Definition at line 65 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_REGWEN_3_EN_3_BIT

#define PINMUX_MIO_PERIPH_INSEL_REGWEN_3_EN_3_BIT 0

Definition at line 71 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_REGWEN_3_REG_OFFSET

#define PINMUX_MIO_PERIPH_INSEL_REGWEN_3_REG_OFFSET 0x10

Definition at line 69 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_REGWEN_3_REG_RESVAL

#define PINMUX_MIO_PERIPH_INSEL_REGWEN_3_REG_RESVAL 0x1u

Definition at line 70 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_REGWEN_EN_FIELD_WIDTH

#define PINMUX_MIO_PERIPH_INSEL_REGWEN_EN_FIELD_WIDTH 1

Definition at line 50 of file pinmux_regs.h.

◆ PINMUX_MIO_PERIPH_INSEL_REGWEN_MULTIREG_COUNT

#define PINMUX_MIO_PERIPH_INSEL_REGWEN_MULTIREG_COUNT 4

Definition at line 51 of file pinmux_regs.h.

◆ PINMUX_PARAM_N_DIO_PADS

#define PINMUX_PARAM_N_DIO_PADS 73

Definition at line 29 of file pinmux_regs.h.

◆ PINMUX_PARAM_N_MIO_PADS

#define PINMUX_PARAM_N_MIO_PADS 12

Definition at line 26 of file pinmux_regs.h.

◆ PINMUX_PARAM_N_MIO_PERIPH_IN

#define PINMUX_PARAM_N_MIO_PERIPH_IN 4

Definition at line 20 of file pinmux_regs.h.

◆ PINMUX_PARAM_N_MIO_PERIPH_OUT

#define PINMUX_PARAM_N_MIO_PERIPH_OUT 5

Definition at line 23 of file pinmux_regs.h.

◆ PINMUX_PARAM_N_WKUP_DETECT

#define PINMUX_PARAM_N_WKUP_DETECT 8

Definition at line 32 of file pinmux_regs.h.

◆ PINMUX_PARAM_NUM_ALERTS

#define PINMUX_PARAM_NUM_ALERTS 1

Definition at line 38 of file pinmux_regs.h.

◆ PINMUX_PARAM_REG_WIDTH

#define PINMUX_PARAM_REG_WIDTH 32

Definition at line 41 of file pinmux_regs.h.

◆ PINMUX_PARAM_WKUP_CNT_WIDTH

#define PINMUX_PARAM_WKUP_CNT_WIDTH 8

Definition at line 35 of file pinmux_regs.h.

◆ PINMUX_WKUP_CAUSE_CAUSE_0_BIT

#define PINMUX_WKUP_CAUSE_CAUSE_0_BIT 0

Definition at line 4437 of file pinmux_regs.h.

◆ PINMUX_WKUP_CAUSE_CAUSE_1_BIT

#define PINMUX_WKUP_CAUSE_CAUSE_1_BIT 1

Definition at line 4438 of file pinmux_regs.h.

◆ PINMUX_WKUP_CAUSE_CAUSE_2_BIT

#define PINMUX_WKUP_CAUSE_CAUSE_2_BIT 2

Definition at line 4439 of file pinmux_regs.h.

◆ PINMUX_WKUP_CAUSE_CAUSE_3_BIT

#define PINMUX_WKUP_CAUSE_CAUSE_3_BIT 3

Definition at line 4440 of file pinmux_regs.h.

◆ PINMUX_WKUP_CAUSE_CAUSE_4_BIT

#define PINMUX_WKUP_CAUSE_CAUSE_4_BIT 4

Definition at line 4441 of file pinmux_regs.h.

◆ PINMUX_WKUP_CAUSE_CAUSE_5_BIT

#define PINMUX_WKUP_CAUSE_CAUSE_5_BIT 5

Definition at line 4442 of file pinmux_regs.h.

◆ PINMUX_WKUP_CAUSE_CAUSE_6_BIT

#define PINMUX_WKUP_CAUSE_CAUSE_6_BIT 6

Definition at line 4443 of file pinmux_regs.h.

◆ PINMUX_WKUP_CAUSE_CAUSE_7_BIT

#define PINMUX_WKUP_CAUSE_CAUSE_7_BIT 7

Definition at line 4444 of file pinmux_regs.h.

◆ PINMUX_WKUP_CAUSE_CAUSE_FIELD_WIDTH

#define PINMUX_WKUP_CAUSE_CAUSE_FIELD_WIDTH 1

Definition at line 4431 of file pinmux_regs.h.

◆ PINMUX_WKUP_CAUSE_MULTIREG_COUNT

#define PINMUX_WKUP_CAUSE_MULTIREG_COUNT 1

Definition at line 4432 of file pinmux_regs.h.

◆ PINMUX_WKUP_CAUSE_REG_OFFSET

#define PINMUX_WKUP_CAUSE_REG_OFFSET 0x7d8

Definition at line 4435 of file pinmux_regs.h.

◆ PINMUX_WKUP_CAUSE_REG_RESVAL

#define PINMUX_WKUP_CAUSE_REG_RESVAL 0x0u

Definition at line 4436 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_0_FILTER_0_BIT

#define PINMUX_WKUP_DETECTOR_0_FILTER_0_BIT 3

Definition at line 4221 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_0_MIODIO_0_BIT

#define PINMUX_WKUP_DETECTOR_0_MIODIO_0_BIT 4

Definition at line 4222 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_0_MODE_0_FIELD

#define PINMUX_WKUP_DETECTOR_0_MODE_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_0_MODE_0_MASK, .index = PINMUX_WKUP_DETECTOR_0_MODE_0_OFFSET })

Definition at line 4214 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_0_MODE_0_MASK

#define PINMUX_WKUP_DETECTOR_0_MODE_0_MASK 0x7u

Definition at line 4212 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_0_MODE_0_OFFSET

#define PINMUX_WKUP_DETECTOR_0_MODE_0_OFFSET 0

Definition at line 4213 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_EDGE

#define PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_EDGE 0x2

Definition at line 4218 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_NEGEDGE

#define PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_NEGEDGE 0x1

Definition at line 4217 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_POSEDGE

#define PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_POSEDGE 0x0

Definition at line 4216 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_TIMEDHIGH

#define PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_TIMEDHIGH 0x3

Definition at line 4219 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_TIMEDLOW

#define PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_TIMEDLOW 0x4

Definition at line 4220 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_0_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_0_REG_OFFSET 0x778

Definition at line 4210 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_0_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_0_REG_RESVAL 0x0u

Definition at line 4211 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_1_FILTER_1_BIT

#define PINMUX_WKUP_DETECTOR_1_FILTER_1_BIT 3

Definition at line 4231 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_1_MIODIO_1_BIT

#define PINMUX_WKUP_DETECTOR_1_MIODIO_1_BIT 4

Definition at line 4232 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_1_MODE_1_FIELD

#define PINMUX_WKUP_DETECTOR_1_MODE_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_1_MODE_1_MASK, .index = PINMUX_WKUP_DETECTOR_1_MODE_1_OFFSET })

Definition at line 4229 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_1_MODE_1_MASK

#define PINMUX_WKUP_DETECTOR_1_MODE_1_MASK 0x7u

Definition at line 4227 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_1_MODE_1_OFFSET

#define PINMUX_WKUP_DETECTOR_1_MODE_1_OFFSET 0

Definition at line 4228 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_1_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_1_REG_OFFSET 0x77c

Definition at line 4225 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_1_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_1_REG_RESVAL 0x0u

Definition at line 4226 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_2_FILTER_2_BIT

#define PINMUX_WKUP_DETECTOR_2_FILTER_2_BIT 3

Definition at line 4241 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_2_MIODIO_2_BIT

#define PINMUX_WKUP_DETECTOR_2_MIODIO_2_BIT 4

Definition at line 4242 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_2_MODE_2_FIELD

#define PINMUX_WKUP_DETECTOR_2_MODE_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_2_MODE_2_MASK, .index = PINMUX_WKUP_DETECTOR_2_MODE_2_OFFSET })

Definition at line 4239 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_2_MODE_2_MASK

#define PINMUX_WKUP_DETECTOR_2_MODE_2_MASK 0x7u

Definition at line 4237 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_2_MODE_2_OFFSET

#define PINMUX_WKUP_DETECTOR_2_MODE_2_OFFSET 0

Definition at line 4238 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_2_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_2_REG_OFFSET 0x780

Definition at line 4235 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_2_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_2_REG_RESVAL 0x0u

Definition at line 4236 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_3_FILTER_3_BIT

#define PINMUX_WKUP_DETECTOR_3_FILTER_3_BIT 3

Definition at line 4251 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_3_MIODIO_3_BIT

#define PINMUX_WKUP_DETECTOR_3_MIODIO_3_BIT 4

Definition at line 4252 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_3_MODE_3_FIELD

#define PINMUX_WKUP_DETECTOR_3_MODE_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_3_MODE_3_MASK, .index = PINMUX_WKUP_DETECTOR_3_MODE_3_OFFSET })

Definition at line 4249 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_3_MODE_3_MASK

#define PINMUX_WKUP_DETECTOR_3_MODE_3_MASK 0x7u

Definition at line 4247 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_3_MODE_3_OFFSET

#define PINMUX_WKUP_DETECTOR_3_MODE_3_OFFSET 0

Definition at line 4248 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_3_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_3_REG_OFFSET 0x784

Definition at line 4245 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_3_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_3_REG_RESVAL 0x0u

Definition at line 4246 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_4_FILTER_4_BIT

#define PINMUX_WKUP_DETECTOR_4_FILTER_4_BIT 3

Definition at line 4261 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_4_MIODIO_4_BIT

#define PINMUX_WKUP_DETECTOR_4_MIODIO_4_BIT 4

Definition at line 4262 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_4_MODE_4_FIELD

#define PINMUX_WKUP_DETECTOR_4_MODE_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_4_MODE_4_MASK, .index = PINMUX_WKUP_DETECTOR_4_MODE_4_OFFSET })

Definition at line 4259 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_4_MODE_4_MASK

#define PINMUX_WKUP_DETECTOR_4_MODE_4_MASK 0x7u

Definition at line 4257 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_4_MODE_4_OFFSET

#define PINMUX_WKUP_DETECTOR_4_MODE_4_OFFSET 0

Definition at line 4258 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_4_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_4_REG_OFFSET 0x788

Definition at line 4255 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_4_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_4_REG_RESVAL 0x0u

Definition at line 4256 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_5_FILTER_5_BIT

#define PINMUX_WKUP_DETECTOR_5_FILTER_5_BIT 3

Definition at line 4271 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_5_MIODIO_5_BIT

#define PINMUX_WKUP_DETECTOR_5_MIODIO_5_BIT 4

Definition at line 4272 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_5_MODE_5_FIELD

#define PINMUX_WKUP_DETECTOR_5_MODE_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_5_MODE_5_MASK, .index = PINMUX_WKUP_DETECTOR_5_MODE_5_OFFSET })

Definition at line 4269 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_5_MODE_5_MASK

#define PINMUX_WKUP_DETECTOR_5_MODE_5_MASK 0x7u

Definition at line 4267 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_5_MODE_5_OFFSET

#define PINMUX_WKUP_DETECTOR_5_MODE_5_OFFSET 0

Definition at line 4268 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_5_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_5_REG_OFFSET 0x78c

Definition at line 4265 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_5_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_5_REG_RESVAL 0x0u

Definition at line 4266 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_6_FILTER_6_BIT

#define PINMUX_WKUP_DETECTOR_6_FILTER_6_BIT 3

Definition at line 4281 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_6_MIODIO_6_BIT

#define PINMUX_WKUP_DETECTOR_6_MIODIO_6_BIT 4

Definition at line 4282 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_6_MODE_6_FIELD

#define PINMUX_WKUP_DETECTOR_6_MODE_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_6_MODE_6_MASK, .index = PINMUX_WKUP_DETECTOR_6_MODE_6_OFFSET })

Definition at line 4279 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_6_MODE_6_MASK

#define PINMUX_WKUP_DETECTOR_6_MODE_6_MASK 0x7u

Definition at line 4277 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_6_MODE_6_OFFSET

#define PINMUX_WKUP_DETECTOR_6_MODE_6_OFFSET 0

Definition at line 4278 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_6_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_6_REG_OFFSET 0x790

Definition at line 4275 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_6_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_6_REG_RESVAL 0x0u

Definition at line 4276 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_7_FILTER_7_BIT

#define PINMUX_WKUP_DETECTOR_7_FILTER_7_BIT 3

Definition at line 4291 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_7_MIODIO_7_BIT

#define PINMUX_WKUP_DETECTOR_7_MIODIO_7_BIT 4

Definition at line 4292 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_7_MODE_7_FIELD

#define PINMUX_WKUP_DETECTOR_7_MODE_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_7_MODE_7_MASK, .index = PINMUX_WKUP_DETECTOR_7_MODE_7_OFFSET })

Definition at line 4289 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_7_MODE_7_MASK

#define PINMUX_WKUP_DETECTOR_7_MODE_7_MASK 0x7u

Definition at line 4287 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_7_MODE_7_OFFSET

#define PINMUX_WKUP_DETECTOR_7_MODE_7_OFFSET 0

Definition at line 4288 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_7_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_7_REG_OFFSET 0x794

Definition at line 4285 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_7_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_7_REG_RESVAL 0x0u

Definition at line 4286 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_0_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_CNT_TH_0_REG_OFFSET 0x798

Definition at line 4299 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_0_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_CNT_TH_0_REG_RESVAL 0x0u

Definition at line 4300 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_0_TH_0_FIELD

#define PINMUX_WKUP_DETECTOR_CNT_TH_0_TH_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_0_TH_0_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_0_TH_0_OFFSET })

Definition at line 4303 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_0_TH_0_MASK

#define PINMUX_WKUP_DETECTOR_CNT_TH_0_TH_0_MASK 0xffu

Definition at line 4301 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_0_TH_0_OFFSET

#define PINMUX_WKUP_DETECTOR_CNT_TH_0_TH_0_OFFSET 0

Definition at line 4302 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_1_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_CNT_TH_1_REG_OFFSET 0x79c

Definition at line 4307 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_1_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_CNT_TH_1_REG_RESVAL 0x0u

Definition at line 4308 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_1_TH_1_FIELD

#define PINMUX_WKUP_DETECTOR_CNT_TH_1_TH_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_1_TH_1_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_1_TH_1_OFFSET })

Definition at line 4311 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_1_TH_1_MASK

#define PINMUX_WKUP_DETECTOR_CNT_TH_1_TH_1_MASK 0xffu

Definition at line 4309 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_1_TH_1_OFFSET

#define PINMUX_WKUP_DETECTOR_CNT_TH_1_TH_1_OFFSET 0

Definition at line 4310 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_2_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_CNT_TH_2_REG_OFFSET 0x7a0

Definition at line 4315 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_2_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_CNT_TH_2_REG_RESVAL 0x0u

Definition at line 4316 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_2_TH_2_FIELD

#define PINMUX_WKUP_DETECTOR_CNT_TH_2_TH_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_2_TH_2_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_2_TH_2_OFFSET })

Definition at line 4319 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_2_TH_2_MASK

#define PINMUX_WKUP_DETECTOR_CNT_TH_2_TH_2_MASK 0xffu

Definition at line 4317 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_2_TH_2_OFFSET

#define PINMUX_WKUP_DETECTOR_CNT_TH_2_TH_2_OFFSET 0

Definition at line 4318 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_3_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_CNT_TH_3_REG_OFFSET 0x7a4

Definition at line 4323 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_3_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_CNT_TH_3_REG_RESVAL 0x0u

Definition at line 4324 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_3_TH_3_FIELD

#define PINMUX_WKUP_DETECTOR_CNT_TH_3_TH_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_3_TH_3_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_3_TH_3_OFFSET })

Definition at line 4327 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_3_TH_3_MASK

#define PINMUX_WKUP_DETECTOR_CNT_TH_3_TH_3_MASK 0xffu

Definition at line 4325 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_3_TH_3_OFFSET

#define PINMUX_WKUP_DETECTOR_CNT_TH_3_TH_3_OFFSET 0

Definition at line 4326 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_4_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_CNT_TH_4_REG_OFFSET 0x7a8

Definition at line 4331 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_4_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_CNT_TH_4_REG_RESVAL 0x0u

Definition at line 4332 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_4_TH_4_FIELD

#define PINMUX_WKUP_DETECTOR_CNT_TH_4_TH_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_4_TH_4_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_4_TH_4_OFFSET })

Definition at line 4335 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_4_TH_4_MASK

#define PINMUX_WKUP_DETECTOR_CNT_TH_4_TH_4_MASK 0xffu

Definition at line 4333 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_4_TH_4_OFFSET

#define PINMUX_WKUP_DETECTOR_CNT_TH_4_TH_4_OFFSET 0

Definition at line 4334 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_5_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_CNT_TH_5_REG_OFFSET 0x7ac

Definition at line 4339 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_5_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_CNT_TH_5_REG_RESVAL 0x0u

Definition at line 4340 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_5_TH_5_FIELD

#define PINMUX_WKUP_DETECTOR_CNT_TH_5_TH_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_5_TH_5_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_5_TH_5_OFFSET })

Definition at line 4343 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_5_TH_5_MASK

#define PINMUX_WKUP_DETECTOR_CNT_TH_5_TH_5_MASK 0xffu

Definition at line 4341 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_5_TH_5_OFFSET

#define PINMUX_WKUP_DETECTOR_CNT_TH_5_TH_5_OFFSET 0

Definition at line 4342 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_6_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_CNT_TH_6_REG_OFFSET 0x7b0

Definition at line 4347 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_6_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_CNT_TH_6_REG_RESVAL 0x0u

Definition at line 4348 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_6_TH_6_FIELD

#define PINMUX_WKUP_DETECTOR_CNT_TH_6_TH_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_6_TH_6_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_6_TH_6_OFFSET })

Definition at line 4351 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_6_TH_6_MASK

#define PINMUX_WKUP_DETECTOR_CNT_TH_6_TH_6_MASK 0xffu

Definition at line 4349 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_6_TH_6_OFFSET

#define PINMUX_WKUP_DETECTOR_CNT_TH_6_TH_6_OFFSET 0

Definition at line 4350 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_7_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_CNT_TH_7_REG_OFFSET 0x7b4

Definition at line 4355 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_7_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_CNT_TH_7_REG_RESVAL 0x0u

Definition at line 4356 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_7_TH_7_FIELD

#define PINMUX_WKUP_DETECTOR_CNT_TH_7_TH_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_CNT_TH_7_TH_7_MASK, .index = PINMUX_WKUP_DETECTOR_CNT_TH_7_TH_7_OFFSET })

Definition at line 4359 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_7_TH_7_MASK

#define PINMUX_WKUP_DETECTOR_CNT_TH_7_TH_7_MASK 0xffu

Definition at line 4357 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_7_TH_7_OFFSET

#define PINMUX_WKUP_DETECTOR_CNT_TH_7_TH_7_OFFSET 0

Definition at line 4358 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_MULTIREG_COUNT

#define PINMUX_WKUP_DETECTOR_CNT_TH_MULTIREG_COUNT 8

Definition at line 4296 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_CNT_TH_TH_FIELD_WIDTH

#define PINMUX_WKUP_DETECTOR_CNT_TH_TH_FIELD_WIDTH 8

Definition at line 4295 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_EN_0_EN_0_BIT

#define PINMUX_WKUP_DETECTOR_EN_0_EN_0_BIT 0

Definition at line 4166 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_EN_0_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_EN_0_REG_OFFSET 0x758

Definition at line 4164 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_EN_0_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_EN_0_REG_RESVAL 0x0u

Definition at line 4165 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_EN_1_EN_1_BIT

#define PINMUX_WKUP_DETECTOR_EN_1_EN_1_BIT 0

Definition at line 4171 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_EN_1_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_EN_1_REG_OFFSET 0x75c

Definition at line 4169 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_EN_1_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_EN_1_REG_RESVAL 0x0u

Definition at line 4170 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_EN_2_EN_2_BIT

#define PINMUX_WKUP_DETECTOR_EN_2_EN_2_BIT 0

Definition at line 4176 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_EN_2_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_EN_2_REG_OFFSET 0x760

Definition at line 4174 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_EN_2_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_EN_2_REG_RESVAL 0x0u

Definition at line 4175 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_EN_3_EN_3_BIT

#define PINMUX_WKUP_DETECTOR_EN_3_EN_3_BIT 0

Definition at line 4181 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_EN_3_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_EN_3_REG_OFFSET 0x764

Definition at line 4179 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_EN_3_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_EN_3_REG_RESVAL 0x0u

Definition at line 4180 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_EN_4_EN_4_BIT

#define PINMUX_WKUP_DETECTOR_EN_4_EN_4_BIT 0

Definition at line 4186 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_EN_4_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_EN_4_REG_OFFSET 0x768

Definition at line 4184 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_EN_4_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_EN_4_REG_RESVAL 0x0u

Definition at line 4185 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_EN_5_EN_5_BIT

#define PINMUX_WKUP_DETECTOR_EN_5_EN_5_BIT 0

Definition at line 4191 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_EN_5_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_EN_5_REG_OFFSET 0x76c

Definition at line 4189 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_EN_5_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_EN_5_REG_RESVAL 0x0u

Definition at line 4190 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_EN_6_EN_6_BIT

#define PINMUX_WKUP_DETECTOR_EN_6_EN_6_BIT 0

Definition at line 4196 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_EN_6_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_EN_6_REG_OFFSET 0x770

Definition at line 4194 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_EN_6_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_EN_6_REG_RESVAL 0x0u

Definition at line 4195 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_EN_7_EN_7_BIT

#define PINMUX_WKUP_DETECTOR_EN_7_EN_7_BIT 0

Definition at line 4201 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_EN_7_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_EN_7_REG_OFFSET 0x774

Definition at line 4199 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_EN_7_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_EN_7_REG_RESVAL 0x0u

Definition at line 4200 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_EN_EN_FIELD_WIDTH

#define PINMUX_WKUP_DETECTOR_EN_EN_FIELD_WIDTH 1

Definition at line 4160 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_EN_MULTIREG_COUNT

#define PINMUX_WKUP_DETECTOR_EN_MULTIREG_COUNT 8

Definition at line 4161 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_FILTER_FIELD_WIDTH

#define PINMUX_WKUP_DETECTOR_FILTER_FIELD_WIDTH 1

Definition at line 4205 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_MIODIO_FIELD_WIDTH

#define PINMUX_WKUP_DETECTOR_MIODIO_FIELD_WIDTH 1

Definition at line 4206 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_MODE_FIELD_WIDTH

#define PINMUX_WKUP_DETECTOR_MODE_FIELD_WIDTH 3

Definition at line 4204 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_MULTIREG_COUNT

#define PINMUX_WKUP_DETECTOR_MULTIREG_COUNT 8

Definition at line 4207 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_0_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_PADSEL_0_REG_OFFSET 0x7b8

Definition at line 4367 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_0_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_PADSEL_0_REG_RESVAL 0x0u

Definition at line 4368 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_0_SEL_0_FIELD

#define PINMUX_WKUP_DETECTOR_PADSEL_0_SEL_0_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_0_SEL_0_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_0_SEL_0_OFFSET })

Definition at line 4371 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_0_SEL_0_MASK

#define PINMUX_WKUP_DETECTOR_PADSEL_0_SEL_0_MASK 0x7fu

Definition at line 4369 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_0_SEL_0_OFFSET

#define PINMUX_WKUP_DETECTOR_PADSEL_0_SEL_0_OFFSET 0

Definition at line 4370 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_1_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_PADSEL_1_REG_OFFSET 0x7bc

Definition at line 4375 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_1_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_PADSEL_1_REG_RESVAL 0x0u

Definition at line 4376 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_1_SEL_1_FIELD

#define PINMUX_WKUP_DETECTOR_PADSEL_1_SEL_1_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_1_SEL_1_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_1_SEL_1_OFFSET })

Definition at line 4379 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_1_SEL_1_MASK

#define PINMUX_WKUP_DETECTOR_PADSEL_1_SEL_1_MASK 0x7fu

Definition at line 4377 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_1_SEL_1_OFFSET

#define PINMUX_WKUP_DETECTOR_PADSEL_1_SEL_1_OFFSET 0

Definition at line 4378 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_2_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_PADSEL_2_REG_OFFSET 0x7c0

Definition at line 4383 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_2_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_PADSEL_2_REG_RESVAL 0x0u

Definition at line 4384 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_2_SEL_2_FIELD

#define PINMUX_WKUP_DETECTOR_PADSEL_2_SEL_2_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_2_SEL_2_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_2_SEL_2_OFFSET })

Definition at line 4387 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_2_SEL_2_MASK

#define PINMUX_WKUP_DETECTOR_PADSEL_2_SEL_2_MASK 0x7fu

Definition at line 4385 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_2_SEL_2_OFFSET

#define PINMUX_WKUP_DETECTOR_PADSEL_2_SEL_2_OFFSET 0

Definition at line 4386 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_3_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_PADSEL_3_REG_OFFSET 0x7c4

Definition at line 4391 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_3_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_PADSEL_3_REG_RESVAL 0x0u

Definition at line 4392 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_3_SEL_3_FIELD

#define PINMUX_WKUP_DETECTOR_PADSEL_3_SEL_3_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_3_SEL_3_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_3_SEL_3_OFFSET })

Definition at line 4395 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_3_SEL_3_MASK

#define PINMUX_WKUP_DETECTOR_PADSEL_3_SEL_3_MASK 0x7fu

Definition at line 4393 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_3_SEL_3_OFFSET

#define PINMUX_WKUP_DETECTOR_PADSEL_3_SEL_3_OFFSET 0

Definition at line 4394 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_4_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_PADSEL_4_REG_OFFSET 0x7c8

Definition at line 4399 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_4_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_PADSEL_4_REG_RESVAL 0x0u

Definition at line 4400 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_4_SEL_4_FIELD

#define PINMUX_WKUP_DETECTOR_PADSEL_4_SEL_4_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_4_SEL_4_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_4_SEL_4_OFFSET })

Definition at line 4403 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_4_SEL_4_MASK

#define PINMUX_WKUP_DETECTOR_PADSEL_4_SEL_4_MASK 0x7fu

Definition at line 4401 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_4_SEL_4_OFFSET

#define PINMUX_WKUP_DETECTOR_PADSEL_4_SEL_4_OFFSET 0

Definition at line 4402 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_5_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_PADSEL_5_REG_OFFSET 0x7cc

Definition at line 4407 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_5_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_PADSEL_5_REG_RESVAL 0x0u

Definition at line 4408 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_5_SEL_5_FIELD

#define PINMUX_WKUP_DETECTOR_PADSEL_5_SEL_5_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_5_SEL_5_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_5_SEL_5_OFFSET })

Definition at line 4411 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_5_SEL_5_MASK

#define PINMUX_WKUP_DETECTOR_PADSEL_5_SEL_5_MASK 0x7fu

Definition at line 4409 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_5_SEL_5_OFFSET

#define PINMUX_WKUP_DETECTOR_PADSEL_5_SEL_5_OFFSET 0

Definition at line 4410 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_6_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_PADSEL_6_REG_OFFSET 0x7d0

Definition at line 4415 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_6_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_PADSEL_6_REG_RESVAL 0x0u

Definition at line 4416 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_6_SEL_6_FIELD

#define PINMUX_WKUP_DETECTOR_PADSEL_6_SEL_6_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_6_SEL_6_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_6_SEL_6_OFFSET })

Definition at line 4419 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_6_SEL_6_MASK

#define PINMUX_WKUP_DETECTOR_PADSEL_6_SEL_6_MASK 0x7fu

Definition at line 4417 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_6_SEL_6_OFFSET

#define PINMUX_WKUP_DETECTOR_PADSEL_6_SEL_6_OFFSET 0

Definition at line 4418 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_7_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_PADSEL_7_REG_OFFSET 0x7d4

Definition at line 4423 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_7_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_PADSEL_7_REG_RESVAL 0x0u

Definition at line 4424 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_7_SEL_7_FIELD

#define PINMUX_WKUP_DETECTOR_PADSEL_7_SEL_7_FIELD ((bitfield_field32_t) { .mask = PINMUX_WKUP_DETECTOR_PADSEL_7_SEL_7_MASK, .index = PINMUX_WKUP_DETECTOR_PADSEL_7_SEL_7_OFFSET })

Definition at line 4427 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_7_SEL_7_MASK

#define PINMUX_WKUP_DETECTOR_PADSEL_7_SEL_7_MASK 0x7fu

Definition at line 4425 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_7_SEL_7_OFFSET

#define PINMUX_WKUP_DETECTOR_PADSEL_7_SEL_7_OFFSET 0

Definition at line 4426 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_MULTIREG_COUNT

#define PINMUX_WKUP_DETECTOR_PADSEL_MULTIREG_COUNT 8

Definition at line 4364 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_PADSEL_SEL_FIELD_WIDTH

#define PINMUX_WKUP_DETECTOR_PADSEL_SEL_FIELD_WIDTH 7

Definition at line 4363 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_REGWEN_0_EN_0_BIT

#define PINMUX_WKUP_DETECTOR_REGWEN_0_EN_0_BIT 0

Definition at line 4122 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_REGWEN_0_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_REGWEN_0_REG_OFFSET 0x738

Definition at line 4120 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_REGWEN_0_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_REGWEN_0_REG_RESVAL 0x1u

Definition at line 4121 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_REGWEN_1_EN_1_BIT

#define PINMUX_WKUP_DETECTOR_REGWEN_1_EN_1_BIT 0

Definition at line 4127 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_REGWEN_1_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_REGWEN_1_REG_OFFSET 0x73c

Definition at line 4125 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_REGWEN_1_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_REGWEN_1_REG_RESVAL 0x1u

Definition at line 4126 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_REGWEN_2_EN_2_BIT

#define PINMUX_WKUP_DETECTOR_REGWEN_2_EN_2_BIT 0

Definition at line 4132 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_REGWEN_2_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_REGWEN_2_REG_OFFSET 0x740

Definition at line 4130 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_REGWEN_2_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_REGWEN_2_REG_RESVAL 0x1u

Definition at line 4131 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_REGWEN_3_EN_3_BIT

#define PINMUX_WKUP_DETECTOR_REGWEN_3_EN_3_BIT 0

Definition at line 4137 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_REGWEN_3_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_REGWEN_3_REG_OFFSET 0x744

Definition at line 4135 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_REGWEN_3_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_REGWEN_3_REG_RESVAL 0x1u

Definition at line 4136 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_REGWEN_4_EN_4_BIT

#define PINMUX_WKUP_DETECTOR_REGWEN_4_EN_4_BIT 0

Definition at line 4142 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_REGWEN_4_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_REGWEN_4_REG_OFFSET 0x748

Definition at line 4140 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_REGWEN_4_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_REGWEN_4_REG_RESVAL 0x1u

Definition at line 4141 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_REGWEN_5_EN_5_BIT

#define PINMUX_WKUP_DETECTOR_REGWEN_5_EN_5_BIT 0

Definition at line 4147 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_REGWEN_5_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_REGWEN_5_REG_OFFSET 0x74c

Definition at line 4145 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_REGWEN_5_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_REGWEN_5_REG_RESVAL 0x1u

Definition at line 4146 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_REGWEN_6_EN_6_BIT

#define PINMUX_WKUP_DETECTOR_REGWEN_6_EN_6_BIT 0

Definition at line 4152 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_REGWEN_6_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_REGWEN_6_REG_OFFSET 0x750

Definition at line 4150 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_REGWEN_6_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_REGWEN_6_REG_RESVAL 0x1u

Definition at line 4151 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_REGWEN_7_EN_7_BIT

#define PINMUX_WKUP_DETECTOR_REGWEN_7_EN_7_BIT 0

Definition at line 4157 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_REGWEN_7_REG_OFFSET

#define PINMUX_WKUP_DETECTOR_REGWEN_7_REG_OFFSET 0x754

Definition at line 4155 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_REGWEN_7_REG_RESVAL

#define PINMUX_WKUP_DETECTOR_REGWEN_7_REG_RESVAL 0x1u

Definition at line 4156 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_REGWEN_EN_FIELD_WIDTH

#define PINMUX_WKUP_DETECTOR_REGWEN_EN_FIELD_WIDTH 1

Definition at line 4116 of file pinmux_regs.h.

◆ PINMUX_WKUP_DETECTOR_REGWEN_MULTIREG_COUNT

#define PINMUX_WKUP_DETECTOR_REGWEN_MULTIREG_COUNT 8

Definition at line 4117 of file pinmux_regs.h.

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