gpio_regs.h

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/**
 * @file
 * @brief Generated register defines for gpio
 */
 
// Copyright information found in source file:
// Copyright lowRISC contributors (OpenTitan project).
 
// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#ifndef _GPIO_REG_DEFS_
#define _GPIO_REG_DEFS_
 
#ifdef __cplusplus
extern "C" {
#endif
// Number of I/Os.
#define GPIO_PARAM_NUM_I_OS 32
 
// Number of input period counters.
#define GPIO_PARAM_NUM_INP_PERIOD_COUNTERS 8
 
// Number of alerts
#define GPIO_PARAM_NUM_ALERTS 1
 
// Register width
#define GPIO_PARAM_REG_WIDTH 32
 
// Common Interrupt Offsets
 
// Interrupt State Register
#define GPIO_INTR_STATE_REG_OFFSET 0x0
#define GPIO_INTR_STATE_REG_RESVAL 0x0u
 
// Interrupt Enable Register
#define GPIO_INTR_ENABLE_REG_OFFSET 0x4
#define GPIO_INTR_ENABLE_REG_RESVAL 0x0u
 
// Interrupt Test Register
#define GPIO_INTR_TEST_REG_OFFSET 0x8
#define GPIO_INTR_TEST_REG_RESVAL 0x0u
 
// Alert Test Register
#define GPIO_ALERT_TEST_REG_OFFSET 0xc
#define GPIO_ALERT_TEST_REG_RESVAL 0x0u
#define GPIO_ALERT_TEST_FATAL_FAULT_BIT 0
 
// GPIO Input data read value
#define GPIO_DATA_IN_REG_OFFSET 0x10
#define GPIO_DATA_IN_REG_RESVAL 0x0u
 
// GPIO direct output data write value
#define GPIO_DIRECT_OUT_REG_OFFSET 0x14
#define GPIO_DIRECT_OUT_REG_RESVAL 0x0u
 
// GPIO write data lower with mask.
#define GPIO_MASKED_OUT_LOWER_REG_OFFSET 0x18
#define GPIO_MASKED_OUT_LOWER_REG_RESVAL 0x0u
#define GPIO_MASKED_OUT_LOWER_DATA_MASK 0xffffu
#define GPIO_MASKED_OUT_LOWER_DATA_OFFSET 0
#define GPIO_MASKED_OUT_LOWER_DATA_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_MASKED_OUT_LOWER_DATA_MASK, .index = GPIO_MASKED_OUT_LOWER_DATA_OFFSET })
#define GPIO_MASKED_OUT_LOWER_MASK_MASK 0xffffu
#define GPIO_MASKED_OUT_LOWER_MASK_OFFSET 16
#define GPIO_MASKED_OUT_LOWER_MASK_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_MASKED_OUT_LOWER_MASK_MASK, .index = GPIO_MASKED_OUT_LOWER_MASK_OFFSET })
 
// GPIO write data upper with mask.
#define GPIO_MASKED_OUT_UPPER_REG_OFFSET 0x1c
#define GPIO_MASKED_OUT_UPPER_REG_RESVAL 0x0u
#define GPIO_MASKED_OUT_UPPER_DATA_MASK 0xffffu
#define GPIO_MASKED_OUT_UPPER_DATA_OFFSET 0
#define GPIO_MASKED_OUT_UPPER_DATA_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_MASKED_OUT_UPPER_DATA_MASK, .index = GPIO_MASKED_OUT_UPPER_DATA_OFFSET })
#define GPIO_MASKED_OUT_UPPER_MASK_MASK 0xffffu
#define GPIO_MASKED_OUT_UPPER_MASK_OFFSET 16
#define GPIO_MASKED_OUT_UPPER_MASK_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_MASKED_OUT_UPPER_MASK_MASK, .index = GPIO_MASKED_OUT_UPPER_MASK_OFFSET })
 
// GPIO Output Enable.
#define GPIO_DIRECT_OE_REG_OFFSET 0x20
#define GPIO_DIRECT_OE_REG_RESVAL 0x0u
 
// GPIO write Output Enable lower with mask.
#define GPIO_MASKED_OE_LOWER_REG_OFFSET 0x24
#define GPIO_MASKED_OE_LOWER_REG_RESVAL 0x0u
#define GPIO_MASKED_OE_LOWER_DATA_MASK 0xffffu
#define GPIO_MASKED_OE_LOWER_DATA_OFFSET 0
#define GPIO_MASKED_OE_LOWER_DATA_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_MASKED_OE_LOWER_DATA_MASK, .index = GPIO_MASKED_OE_LOWER_DATA_OFFSET })
#define GPIO_MASKED_OE_LOWER_MASK_MASK 0xffffu
#define GPIO_MASKED_OE_LOWER_MASK_OFFSET 16
#define GPIO_MASKED_OE_LOWER_MASK_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_MASKED_OE_LOWER_MASK_MASK, .index = GPIO_MASKED_OE_LOWER_MASK_OFFSET })
 
// GPIO write Output Enable upper with mask.
#define GPIO_MASKED_OE_UPPER_REG_OFFSET 0x28
#define GPIO_MASKED_OE_UPPER_REG_RESVAL 0x0u
#define GPIO_MASKED_OE_UPPER_DATA_MASK 0xffffu
#define GPIO_MASKED_OE_UPPER_DATA_OFFSET 0
#define GPIO_MASKED_OE_UPPER_DATA_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_MASKED_OE_UPPER_DATA_MASK, .index = GPIO_MASKED_OE_UPPER_DATA_OFFSET })
#define GPIO_MASKED_OE_UPPER_MASK_MASK 0xffffu
#define GPIO_MASKED_OE_UPPER_MASK_OFFSET 16
#define GPIO_MASKED_OE_UPPER_MASK_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_MASKED_OE_UPPER_MASK_MASK, .index = GPIO_MASKED_OE_UPPER_MASK_OFFSET })
 
// GPIO interrupt enable for GPIO, rising edge.
#define GPIO_INTR_CTRL_EN_RISING_REG_OFFSET 0x2c
#define GPIO_INTR_CTRL_EN_RISING_REG_RESVAL 0x0u
 
// GPIO interrupt enable for GPIO, falling edge.
#define GPIO_INTR_CTRL_EN_FALLING_REG_OFFSET 0x30
#define GPIO_INTR_CTRL_EN_FALLING_REG_RESVAL 0x0u
 
// GPIO interrupt enable for GPIO, level high.
#define GPIO_INTR_CTRL_EN_LVLHIGH_REG_OFFSET 0x34
#define GPIO_INTR_CTRL_EN_LVLHIGH_REG_RESVAL 0x0u
 
// GPIO interrupt enable for GPIO, level low.
#define GPIO_INTR_CTRL_EN_LVLLOW_REG_OFFSET 0x38
#define GPIO_INTR_CTRL_EN_LVLLOW_REG_RESVAL 0x0u
 
// filter enable for GPIO input bits.
#define GPIO_CTRL_EN_INPUT_FILTER_REG_OFFSET 0x3c
#define GPIO_CTRL_EN_INPUT_FILTER_REG_RESVAL 0x0u
 
// Indicates whether the data in !!HW_STRAPS_DATA_IN is valid.
#define GPIO_HW_STRAPS_DATA_IN_VALID_REG_OFFSET 0x40
#define GPIO_HW_STRAPS_DATA_IN_VALID_REG_RESVAL 0x0u
#define GPIO_HW_STRAPS_DATA_IN_VALID_HW_STRAPS_DATA_IN_VALID_BIT 0
 
// GPIO input data that was sampled as straps at most once after the block
#define GPIO_HW_STRAPS_DATA_IN_REG_OFFSET 0x44
#define GPIO_HW_STRAPS_DATA_IN_REG_RESVAL 0x0u
 
// Control register of one input period counter. (common parameters)
#define GPIO_INP_PRD_CNT_CTRL_ENABLE_FIELD_WIDTH 1
#define GPIO_INP_PRD_CNT_CTRL_CONTINUOUS_MODE_FIELD_WIDTH 1
#define GPIO_INP_PRD_CNT_CTRL_POLARITY_FIELD_WIDTH 1
#define GPIO_INP_PRD_CNT_CTRL_INPUT_SELECT_FIELD_WIDTH 8
#define GPIO_INP_PRD_CNT_CTRL_PRESCALER_FIELD_WIDTH 8
#define GPIO_INP_PRD_CNT_CTRL_MULTIREG_COUNT 8
 
// Control register of one input period counter.
#define GPIO_INP_PRD_CNT_CTRL_0_REG_OFFSET 0x48
#define GPIO_INP_PRD_CNT_CTRL_0_REG_RESVAL 0x4u
#define GPIO_INP_PRD_CNT_CTRL_0_ENABLE_0_BIT 0
#define GPIO_INP_PRD_CNT_CTRL_0_CONTINUOUS_MODE_0_BIT 1
#define GPIO_INP_PRD_CNT_CTRL_0_POLARITY_0_BIT 2
#define GPIO_INP_PRD_CNT_CTRL_0_INPUT_SELECT_0_MASK 0xffu
#define GPIO_INP_PRD_CNT_CTRL_0_INPUT_SELECT_0_OFFSET 8
#define GPIO_INP_PRD_CNT_CTRL_0_INPUT_SELECT_0_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_INP_PRD_CNT_CTRL_0_INPUT_SELECT_0_MASK, .index = GPIO_INP_PRD_CNT_CTRL_0_INPUT_SELECT_0_OFFSET })
#define GPIO_INP_PRD_CNT_CTRL_0_PRESCALER_0_MASK 0xffu
#define GPIO_INP_PRD_CNT_CTRL_0_PRESCALER_0_OFFSET 16
#define GPIO_INP_PRD_CNT_CTRL_0_PRESCALER_0_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_INP_PRD_CNT_CTRL_0_PRESCALER_0_MASK, .index = GPIO_INP_PRD_CNT_CTRL_0_PRESCALER_0_OFFSET })
 
// Control register of one input period counter.
#define GPIO_INP_PRD_CNT_CTRL_1_REG_OFFSET 0x4c
#define GPIO_INP_PRD_CNT_CTRL_1_REG_RESVAL 0x4u
#define GPIO_INP_PRD_CNT_CTRL_1_ENABLE_1_BIT 0
#define GPIO_INP_PRD_CNT_CTRL_1_CONTINUOUS_MODE_1_BIT 1
#define GPIO_INP_PRD_CNT_CTRL_1_POLARITY_1_BIT 2
#define GPIO_INP_PRD_CNT_CTRL_1_INPUT_SELECT_1_MASK 0xffu
#define GPIO_INP_PRD_CNT_CTRL_1_INPUT_SELECT_1_OFFSET 8
#define GPIO_INP_PRD_CNT_CTRL_1_INPUT_SELECT_1_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_INP_PRD_CNT_CTRL_1_INPUT_SELECT_1_MASK, .index = GPIO_INP_PRD_CNT_CTRL_1_INPUT_SELECT_1_OFFSET })
#define GPIO_INP_PRD_CNT_CTRL_1_PRESCALER_1_MASK 0xffu
#define GPIO_INP_PRD_CNT_CTRL_1_PRESCALER_1_OFFSET 16
#define GPIO_INP_PRD_CNT_CTRL_1_PRESCALER_1_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_INP_PRD_CNT_CTRL_1_PRESCALER_1_MASK, .index = GPIO_INP_PRD_CNT_CTRL_1_PRESCALER_1_OFFSET })
 
// Control register of one input period counter.
#define GPIO_INP_PRD_CNT_CTRL_2_REG_OFFSET 0x50
#define GPIO_INP_PRD_CNT_CTRL_2_REG_RESVAL 0x4u
#define GPIO_INP_PRD_CNT_CTRL_2_ENABLE_2_BIT 0
#define GPIO_INP_PRD_CNT_CTRL_2_CONTINUOUS_MODE_2_BIT 1
#define GPIO_INP_PRD_CNT_CTRL_2_POLARITY_2_BIT 2
#define GPIO_INP_PRD_CNT_CTRL_2_INPUT_SELECT_2_MASK 0xffu
#define GPIO_INP_PRD_CNT_CTRL_2_INPUT_SELECT_2_OFFSET 8
#define GPIO_INP_PRD_CNT_CTRL_2_INPUT_SELECT_2_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_INP_PRD_CNT_CTRL_2_INPUT_SELECT_2_MASK, .index = GPIO_INP_PRD_CNT_CTRL_2_INPUT_SELECT_2_OFFSET })
#define GPIO_INP_PRD_CNT_CTRL_2_PRESCALER_2_MASK 0xffu
#define GPIO_INP_PRD_CNT_CTRL_2_PRESCALER_2_OFFSET 16
#define GPIO_INP_PRD_CNT_CTRL_2_PRESCALER_2_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_INP_PRD_CNT_CTRL_2_PRESCALER_2_MASK, .index = GPIO_INP_PRD_CNT_CTRL_2_PRESCALER_2_OFFSET })
 
// Control register of one input period counter.
#define GPIO_INP_PRD_CNT_CTRL_3_REG_OFFSET 0x54
#define GPIO_INP_PRD_CNT_CTRL_3_REG_RESVAL 0x4u
#define GPIO_INP_PRD_CNT_CTRL_3_ENABLE_3_BIT 0
#define GPIO_INP_PRD_CNT_CTRL_3_CONTINUOUS_MODE_3_BIT 1
#define GPIO_INP_PRD_CNT_CTRL_3_POLARITY_3_BIT 2
#define GPIO_INP_PRD_CNT_CTRL_3_INPUT_SELECT_3_MASK 0xffu
#define GPIO_INP_PRD_CNT_CTRL_3_INPUT_SELECT_3_OFFSET 8
#define GPIO_INP_PRD_CNT_CTRL_3_INPUT_SELECT_3_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_INP_PRD_CNT_CTRL_3_INPUT_SELECT_3_MASK, .index = GPIO_INP_PRD_CNT_CTRL_3_INPUT_SELECT_3_OFFSET })
#define GPIO_INP_PRD_CNT_CTRL_3_PRESCALER_3_MASK 0xffu
#define GPIO_INP_PRD_CNT_CTRL_3_PRESCALER_3_OFFSET 16
#define GPIO_INP_PRD_CNT_CTRL_3_PRESCALER_3_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_INP_PRD_CNT_CTRL_3_PRESCALER_3_MASK, .index = GPIO_INP_PRD_CNT_CTRL_3_PRESCALER_3_OFFSET })
 
// Control register of one input period counter.
#define GPIO_INP_PRD_CNT_CTRL_4_REG_OFFSET 0x58
#define GPIO_INP_PRD_CNT_CTRL_4_REG_RESVAL 0x4u
#define GPIO_INP_PRD_CNT_CTRL_4_ENABLE_4_BIT 0
#define GPIO_INP_PRD_CNT_CTRL_4_CONTINUOUS_MODE_4_BIT 1
#define GPIO_INP_PRD_CNT_CTRL_4_POLARITY_4_BIT 2
#define GPIO_INP_PRD_CNT_CTRL_4_INPUT_SELECT_4_MASK 0xffu
#define GPIO_INP_PRD_CNT_CTRL_4_INPUT_SELECT_4_OFFSET 8
#define GPIO_INP_PRD_CNT_CTRL_4_INPUT_SELECT_4_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_INP_PRD_CNT_CTRL_4_INPUT_SELECT_4_MASK, .index = GPIO_INP_PRD_CNT_CTRL_4_INPUT_SELECT_4_OFFSET })
#define GPIO_INP_PRD_CNT_CTRL_4_PRESCALER_4_MASK 0xffu
#define GPIO_INP_PRD_CNT_CTRL_4_PRESCALER_4_OFFSET 16
#define GPIO_INP_PRD_CNT_CTRL_4_PRESCALER_4_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_INP_PRD_CNT_CTRL_4_PRESCALER_4_MASK, .index = GPIO_INP_PRD_CNT_CTRL_4_PRESCALER_4_OFFSET })
 
// Control register of one input period counter.
#define GPIO_INP_PRD_CNT_CTRL_5_REG_OFFSET 0x5c
#define GPIO_INP_PRD_CNT_CTRL_5_REG_RESVAL 0x4u
#define GPIO_INP_PRD_CNT_CTRL_5_ENABLE_5_BIT 0
#define GPIO_INP_PRD_CNT_CTRL_5_CONTINUOUS_MODE_5_BIT 1
#define GPIO_INP_PRD_CNT_CTRL_5_POLARITY_5_BIT 2
#define GPIO_INP_PRD_CNT_CTRL_5_INPUT_SELECT_5_MASK 0xffu
#define GPIO_INP_PRD_CNT_CTRL_5_INPUT_SELECT_5_OFFSET 8
#define GPIO_INP_PRD_CNT_CTRL_5_INPUT_SELECT_5_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_INP_PRD_CNT_CTRL_5_INPUT_SELECT_5_MASK, .index = GPIO_INP_PRD_CNT_CTRL_5_INPUT_SELECT_5_OFFSET })
#define GPIO_INP_PRD_CNT_CTRL_5_PRESCALER_5_MASK 0xffu
#define GPIO_INP_PRD_CNT_CTRL_5_PRESCALER_5_OFFSET 16
#define GPIO_INP_PRD_CNT_CTRL_5_PRESCALER_5_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_INP_PRD_CNT_CTRL_5_PRESCALER_5_MASK, .index = GPIO_INP_PRD_CNT_CTRL_5_PRESCALER_5_OFFSET })
 
// Control register of one input period counter.
#define GPIO_INP_PRD_CNT_CTRL_6_REG_OFFSET 0x60
#define GPIO_INP_PRD_CNT_CTRL_6_REG_RESVAL 0x4u
#define GPIO_INP_PRD_CNT_CTRL_6_ENABLE_6_BIT 0
#define GPIO_INP_PRD_CNT_CTRL_6_CONTINUOUS_MODE_6_BIT 1
#define GPIO_INP_PRD_CNT_CTRL_6_POLARITY_6_BIT 2
#define GPIO_INP_PRD_CNT_CTRL_6_INPUT_SELECT_6_MASK 0xffu
#define GPIO_INP_PRD_CNT_CTRL_6_INPUT_SELECT_6_OFFSET 8
#define GPIO_INP_PRD_CNT_CTRL_6_INPUT_SELECT_6_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_INP_PRD_CNT_CTRL_6_INPUT_SELECT_6_MASK, .index = GPIO_INP_PRD_CNT_CTRL_6_INPUT_SELECT_6_OFFSET })
#define GPIO_INP_PRD_CNT_CTRL_6_PRESCALER_6_MASK 0xffu
#define GPIO_INP_PRD_CNT_CTRL_6_PRESCALER_6_OFFSET 16
#define GPIO_INP_PRD_CNT_CTRL_6_PRESCALER_6_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_INP_PRD_CNT_CTRL_6_PRESCALER_6_MASK, .index = GPIO_INP_PRD_CNT_CTRL_6_PRESCALER_6_OFFSET })
 
// Control register of one input period counter.
#define GPIO_INP_PRD_CNT_CTRL_7_REG_OFFSET 0x64
#define GPIO_INP_PRD_CNT_CTRL_7_REG_RESVAL 0x4u
#define GPIO_INP_PRD_CNT_CTRL_7_ENABLE_7_BIT 0
#define GPIO_INP_PRD_CNT_CTRL_7_CONTINUOUS_MODE_7_BIT 1
#define GPIO_INP_PRD_CNT_CTRL_7_POLARITY_7_BIT 2
#define GPIO_INP_PRD_CNT_CTRL_7_INPUT_SELECT_7_MASK 0xffu
#define GPIO_INP_PRD_CNT_CTRL_7_INPUT_SELECT_7_OFFSET 8
#define GPIO_INP_PRD_CNT_CTRL_7_INPUT_SELECT_7_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_INP_PRD_CNT_CTRL_7_INPUT_SELECT_7_MASK, .index = GPIO_INP_PRD_CNT_CTRL_7_INPUT_SELECT_7_OFFSET })
#define GPIO_INP_PRD_CNT_CTRL_7_PRESCALER_7_MASK 0xffu
#define GPIO_INP_PRD_CNT_CTRL_7_PRESCALER_7_OFFSET 16
#define GPIO_INP_PRD_CNT_CTRL_7_PRESCALER_7_FIELD \
  ((bitfield_field32_t) { .mask = GPIO_INP_PRD_CNT_CTRL_7_PRESCALER_7_MASK, .index = GPIO_INP_PRD_CNT_CTRL_7_PRESCALER_7_OFFSET })
 
// Output value of one input period counter. (common parameters)
#define GPIO_INP_PRD_CNT_VAL_VALUE_FIELD_WIDTH 32
#define GPIO_INP_PRD_CNT_VAL_MULTIREG_COUNT 8
 
// Output value of one input period counter.
#define GPIO_INP_PRD_CNT_VAL_0_REG_OFFSET 0x68
#define GPIO_INP_PRD_CNT_VAL_0_REG_RESVAL 0x0u
 
// Output value of one input period counter.
#define GPIO_INP_PRD_CNT_VAL_1_REG_OFFSET 0x6c
#define GPIO_INP_PRD_CNT_VAL_1_REG_RESVAL 0x0u
 
// Output value of one input period counter.
#define GPIO_INP_PRD_CNT_VAL_2_REG_OFFSET 0x70
#define GPIO_INP_PRD_CNT_VAL_2_REG_RESVAL 0x0u
 
// Output value of one input period counter.
#define GPIO_INP_PRD_CNT_VAL_3_REG_OFFSET 0x74
#define GPIO_INP_PRD_CNT_VAL_3_REG_RESVAL 0x0u
 
// Output value of one input period counter.
#define GPIO_INP_PRD_CNT_VAL_4_REG_OFFSET 0x78
#define GPIO_INP_PRD_CNT_VAL_4_REG_RESVAL 0x0u
 
// Output value of one input period counter.
#define GPIO_INP_PRD_CNT_VAL_5_REG_OFFSET 0x7c
#define GPIO_INP_PRD_CNT_VAL_5_REG_RESVAL 0x0u
 
// Output value of one input period counter.
#define GPIO_INP_PRD_CNT_VAL_6_REG_OFFSET 0x80
#define GPIO_INP_PRD_CNT_VAL_6_REG_RESVAL 0x0u
 
// Output value of one input period counter.
#define GPIO_INP_PRD_CNT_VAL_7_REG_OFFSET 0x84
#define GPIO_INP_PRD_CNT_VAL_7_REG_RESVAL 0x0u
 
#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _GPIO_REG_DEFS_
// End generated register defines for gpio