Software APIs
dt_sram_ctrl.c
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7/**
8 * @file
9 * @brief Device Tables (DT) for IP sram_ctrl and top darjeeling.
10 */
11
12#include "hw/top/dt/dt_sram_ctrl.h"
13
14
15
16/**
17 * Description of instances.
18 */
19typedef struct dt_desc_sram_ctrl {
20 dt_instance_id_t inst_id; /**< Instance ID */
21 uint32_t reg_addr[kDtSramCtrlRegBlockCount]; /**< Base address of each register block */
22 uint32_t mem_addr[kDtSramCtrlMemoryCount]; /**< Base address of each memory */
23 uint32_t mem_size[kDtSramCtrlMemoryCount]; /**< Size in bytes of each memory */
24 /**
25 * Alert ID of the first Alert of this instance.
26 *
27 * This value is undefined if the block is not connected to the Alert Handler.
28 */
30 dt_clock_t clock[kDtSramCtrlClockCount]; /**< Clock signal connected to each clock port */
31 dt_reset_t reset[kDtSramCtrlResetCount]; /**< Reset signal connected to each reset port */
33
34
35
36
37static const dt_desc_sram_ctrl_t sram_ctrl_desc[kDtSramCtrlCount] = {
40 .reg_addr = {
41 [kDtSramCtrlRegBlockRegs] = 0x30500000,
42 },
43 .mem_addr = {
44 [kDtSramCtrlMemoryRam] = 0x30600000,
45 },
46 .mem_size = {
47 [kDtSramCtrlMemoryRam] = 0x1000,
48 },
50 .clock = {
53 },
54 .reset = {
57 },
58 },
59 [kDtSramCtrlMain] = {
61 .reg_addr = {
62 [kDtSramCtrlRegBlockRegs] = 0x211c0000,
63 },
64 .mem_addr = {
65 [kDtSramCtrlMemoryRam] = 0x10000000,
66 },
67 .mem_size = {
68 [kDtSramCtrlMemoryRam] = 0x10000,
69 },
71 .clock = {
74 },
75 .reset = {
78 },
79 },
80 [kDtSramCtrlMbox] = {
82 .reg_addr = {
83 [kDtSramCtrlRegBlockRegs] = 0x211d0000,
84 },
85 .mem_addr = {
86 [kDtSramCtrlMemoryRam] = 0x11000000,
87 },
88 .mem_size = {
89 [kDtSramCtrlMemoryRam] = 0x1000,
90 },
92 .clock = {
95 },
96 .reset = {
99 },
100 },
101};
102
103/**
104 * Return a pointer to the `dt_sram_ctrl_desc_t` structure of the requested
105 * `dt` if it's a valid index. Otherwise, this macro will `return` (i.e. exit
106 * the function) with the provided default value.
107 */
108#define TRY_GET_DT(dt, default) ({ if ((dt) < (dt_sram_ctrl_t)0 || (dt) >= kDtSramCtrlCount) return (default); &sram_ctrl_desc[dt]; })
109
116
121
124 dt_sram_ctrl_reg_block_t reg_block) {
125 // Return a recognizable address in case of wrong argument.
126 return TRY_GET_DT(dt, 0xdeadbeef)->reg_addr[reg_block];
127}
128
132 // Return a recognizable address in case of wrong argument.
133 return TRY_GET_DT(dt, 0xdeadbeef)->mem_addr[mem];
134}
135
139 // Return an empty size in case of wrong argument.
140 return TRY_GET_DT(dt, 0)->mem_size[mem];
141}
142
143
146 dt_sram_ctrl_alert_t alert) {
147 return (dt_alert_id_t)((uint32_t)sram_ctrl_desc[dt].first_alert + (uint32_t)alert);
148}
149
152 dt_alert_id_t alert) {
153 dt_sram_ctrl_alert_t count = kDtSramCtrlAlertCount;
154 if (alert < sram_ctrl_desc[dt].first_alert || alert >= sram_ctrl_desc[dt].first_alert + (dt_alert_id_t)count) {
155 return count;
156 }
157 return (dt_sram_ctrl_alert_t)(alert - sram_ctrl_desc[dt].first_alert);
158}
159
160
161
165 // Return the first clock in case of invalid argument.
166 return TRY_GET_DT(dt, (dt_clock_t)0)->clock[clk];
167}
168
172 const dt_sram_ctrl_reset_t count = kDtSramCtrlResetCount;
173 if (rst >= count) {
174 return kDtResetUnknown;
175 }
176 return TRY_GET_DT(dt, kDtResetUnknown)->reset[rst];
177}
178
179