Software APIs
dt_sram_ctrl.c
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7/**
8 * @file
9 * @brief Device Tables (DT) for IP sram_ctrl and top darjeeling.
10 */
11
12#include "dt/dt_sram_ctrl.h"
13
14
15
16/**
17 * Description of instances.
18 */
19typedef struct dt_desc_sram_ctrl {
20 dt_instance_id_t inst_id; /**< Instance ID */
21 uint32_t base_addr[kDtSramCtrlRegBlockCount]; /**< Base address of each register block */
22 /**
23 * Alert ID of the first Alert of this instance.
24 *
25 * This value is undefined if the block is not connected to the Alert Handler.
26 */
28 dt_clock_t clock[kDtSramCtrlClockCount]; /**< Clock signal connected to each clock port */
29 dt_reset_t reset[kDtSramCtrlResetCount]; /**< Reset signal connected to each reset port */
31
32
33
34
35static const dt_desc_sram_ctrl_t sram_ctrl_desc[kDtSramCtrlCount] = {
38 .base_addr = {
39 [kDtSramCtrlRegBlockRegs] = 0x30500000,
40 [kDtSramCtrlRegBlockRam] = 0x30600000,
41 },
43 .clock = {
46 },
47 .reset = {
50 },
51 },
52 [kDtSramCtrlMain] = {
54 .base_addr = {
55 [kDtSramCtrlRegBlockRegs] = 0x211c0000,
56 [kDtSramCtrlRegBlockRam] = 0x10000000,
57 },
59 .clock = {
62 },
63 .reset = {
66 },
67 },
68 [kDtSramCtrlMbox] = {
70 .base_addr = {
71 [kDtSramCtrlRegBlockRegs] = 0x211d0000,
72 [kDtSramCtrlRegBlockRam] = 0x11000000,
73 },
75 .clock = {
78 },
79 .reset = {
82 },
83 },
84};
85
86/**
87 * Return a pointer to the `dt_sram_ctrl_desc_t` structure of the requested
88 * `dt` if it's a valid index. Otherwise, this macro will `return` (i.e. exit
89 * the function) with the provided default value.
90 */
91#define TRY_GET_DT(dt, default) ({ if ((dt) < (dt_sram_ctrl_t)0 || (dt) >= kDtSramCtrlCount) return (default); &sram_ctrl_desc[dt]; })
92
99
104
107 dt_sram_ctrl_reg_block_t reg_block) {
108 // Return a recognizable address in case of wrong argument.
109 return TRY_GET_DT(dt, 0xdeadbeef)->base_addr[reg_block];
110}
111
112
115 dt_sram_ctrl_alert_t alert) {
116 return (dt_alert_id_t)((uint32_t)sram_ctrl_desc[dt].first_alert + (uint32_t)alert);
117}
118
121 dt_alert_id_t alert) {
122 dt_sram_ctrl_alert_t count = kDtSramCtrlAlertCount;
123 if (alert < sram_ctrl_desc[dt].first_alert || alert >= sram_ctrl_desc[dt].first_alert + (dt_alert_id_t)count) {
124 return count;
125 }
126 return (dt_sram_ctrl_alert_t)(alert - sram_ctrl_desc[dt].first_alert);
127}
128
129
130
134 // Return the first clock in case of invalid argument.
135 return TRY_GET_DT(dt, (dt_clock_t)0)->clock[clk];
136}
137
141 const dt_sram_ctrl_reset_t count = kDtSramCtrlResetCount;
142 if (rst >= count) {
143 return kDtResetUnknown;
144 }
145 return TRY_GET_DT(dt, kDtResetUnknown)->reset[rst];
146}
147
148