Software APIs
dt_rstmgr.c
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// Copyright lowRISC contributors (OpenTitan project).
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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//
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// Device table API auto-generated by `dtgen`
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/**
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* @file
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* @brief Device Tables (DT) for IP rstmgr and top darjeeling.
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*/
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#include "hw/top/dt/dt_rstmgr.h"
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#include "
dt_aon_timer.h
"
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#include "
dt_soc_proxy.h
"
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/**
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* Description of instances.
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*/
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typedef
struct
dt_desc_rstmgr
{
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dt_instance_id_t
inst_id
;
/**< Instance ID */
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uint32_t
reg_addr
[kDtRstmgrRegBlockCount];
/**< Base address of each register block */
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uint32_t
mem_addr
[kDtRstmgrMemoryCount];
/**< Base address of each memory */
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uint32_t
mem_size
[kDtRstmgrMemoryCount];
/**< Size in bytes of each memory */
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/**
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* Alert ID of the first Alert of this instance.
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*
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* This value is undefined if the block is not connected to the Alert Handler.
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*/
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top_darjeeling_alert_id_t
first_alert
;
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dt_clock_t
clock
[kDtRstmgrClockCount];
/**< Clock signal connected to each clock port */
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dt_reset_t
reset
[kDtRstmgrResetCount];
/**< Reset signal connected to each reset port */
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struct
{
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dt_reset_t
sw_rst[3];
/**< List of software resets, in the order of the register fields */
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dt_rstmgr_reset_req_src_t
hw_req[5];
/**< List of hardware reset requests, in the order of the register fields */
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}
rstmgr_ext
;
/**< Extension */
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}
dt_desc_rstmgr_t
;
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static
const
dt_desc_rstmgr_t
rstmgr_desc[kDtRstmgrCount] = {
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[
kDtRstmgrAon
] = {
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.inst_id =
kDtInstanceIdRstmgrAon
,
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.reg_addr = {
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[kDtRstmgrRegBlockCore] = 0x30410000,
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},
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.mem_addr = {
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},
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.mem_size = {
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},
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.first_alert =
kTopDarjeelingAlertIdRstmgrAonFatalFault
,
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.clock = {
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[
kDtRstmgrClockClk
] =
kDtClockIoDiv4
,
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[
kDtRstmgrClockPor
] =
kDtClockIoDiv4
,
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[
kDtRstmgrClockAon
] =
kDtClockAon
,
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[
kDtRstmgrClockMain
] =
kDtClockMain
,
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[
kDtRstmgrClockIo
] =
kDtClockIo
,
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[
kDtRstmgrClockIoDiv2
] =
kDtClockIoDiv2
,
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[
kDtRstmgrClockIoDiv4
] =
kDtClockIoDiv4
,
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},
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.reset = {
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[
kDtRstmgrResetRst
] =
kDtResetLcIoDiv4
,
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[
kDtRstmgrResetPor
] =
kDtResetPorIoDiv4
,
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},
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.rstmgr_ext = {
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.sw_rst = {
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[0] =
kDtResetSpiDevice
,
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[1] =
kDtResetSpiHost0
,
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[2] =
kDtResetI2c0
,
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},
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.hw_req = {
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[0] = {
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.inst_id =
kDtInstanceIdAonTimerAon
,
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.reset_req =
kDtAonTimerResetReqAonTimer
,
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},
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[1] = {
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.inst_id =
kDtInstanceIdSocProxy
,
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.reset_req =
kDtSocProxyResetReqExternal
,
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},
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[2] = {
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.inst_id =
kDtInstanceIdPwrmgrAon
,
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.reset_req = 0,
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},
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[3] = {
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.inst_id =
kDtInstanceIdAlertHandler
,
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.reset_req = 0,
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},
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[4] = {
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.inst_id =
kDtInstanceIdRvDm
,
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.reset_req = 0,
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},
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},
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},
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},
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};
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/**
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* Return a pointer to the `dt_rstmgr_desc_t` structure of the requested
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* `dt` if it's a valid index. Otherwise, this macro will `return` (i.e. exit
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* the function) with the provided default value.
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*/
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#define TRY_GET_DT(dt, default) ({ if ((dt) < (dt_rstmgr_t)0 || (dt) >= kDtRstmgrCount) return (default); &rstmgr_desc[dt]; })
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dt_rstmgr_t
dt_rstmgr_from_instance_id
(
dt_instance_id_t
inst_id) {
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if
(inst_id >=
kDtInstanceIdRstmgrAon
&& inst_id <=
kDtInstanceIdRstmgrAon
) {
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return
(
dt_rstmgr_t
)(inst_id -
kDtInstanceIdRstmgrAon
);
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}
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return
(
dt_rstmgr_t
)0;
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}
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dt_instance_id_t
dt_rstmgr_instance_id
(
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dt_rstmgr_t
dt) {
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return
TRY_GET_DT
(dt,
kDtInstanceIdUnknown
)->inst_id;
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}
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uint32_t
dt_rstmgr_reg_block
(
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dt_rstmgr_t
dt,
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dt_rstmgr_reg_block_t
reg_block) {
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// Return a recognizable address in case of wrong argument.
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return
TRY_GET_DT
(dt, 0xdeadbeef)->reg_addr[reg_block];
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}
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uint32_t
dt_rstmgr_memory_base
(
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dt_rstmgr_t
dt,
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dt_rstmgr_memory_t
mem) {
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// Return a recognizable address in case of wrong argument.
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return
TRY_GET_DT
(dt, 0xdeadbeef)->mem_addr[mem];
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}
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uint32_t
dt_rstmgr_memory_size
(
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dt_rstmgr_t
dt,
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dt_rstmgr_memory_t
mem) {
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// Return an empty size in case of wrong argument.
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return
TRY_GET_DT
(dt, 0)->mem_size[mem];
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}
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dt_alert_id_t
dt_rstmgr_alert_to_alert_id
(
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dt_rstmgr_t
dt,
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dt_rstmgr_alert_t
alert) {
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return
(
dt_alert_id_t
)((uint32_t)rstmgr_desc[dt].first_alert + (uint32_t)alert);
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}
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dt_rstmgr_alert_t
dt_rstmgr_alert_from_alert_id
(
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dt_rstmgr_t
dt,
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dt_alert_id_t
alert) {
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dt_rstmgr_alert_t
count = kDtRstmgrAlertCount;
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if
(alert < rstmgr_desc[dt].first_alert || alert >= rstmgr_desc[dt].first_alert + (
dt_alert_id_t
)count) {
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return
count;
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}
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return
(
dt_rstmgr_alert_t
)(alert - rstmgr_desc[dt].first_alert);
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}
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dt_clock_t
dt_rstmgr_clock
(
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dt_rstmgr_t
dt,
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dt_rstmgr_clock_t
clk) {
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// Return the first clock in case of invalid argument.
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return
TRY_GET_DT
(dt, (
dt_clock_t
)0)->clock[clk];
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}
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dt_reset_t
dt_rstmgr_reset
(
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dt_rstmgr_t
dt,
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dt_rstmgr_reset_t
rst) {
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const
dt_rstmgr_reset_t
count = kDtRstmgrResetCount;
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if
(rst >= count) {
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return
kDtResetUnknown
;
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}
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return
TRY_GET_DT
(dt,
kDtResetUnknown
)->reset[rst];
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}
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size_t
dt_rstmgr_sw_reset_count
(
dt_rstmgr_t
dt) {
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return
3;
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}
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dt_reset_t
dt_rstmgr_sw_reset
(
dt_rstmgr_t
dt,
size_t
idx) {
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if
(idx >= 3) {
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return
kDtResetUnknown
;
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}
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return
TRY_GET_DT
(dt,
kDtResetUnknown
)->rstmgr_ext.sw_rst[idx];
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}
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size_t
dt_rstmgr_hw_reset_req_src_count
(
dt_rstmgr_t
dt) {
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return
5;
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}
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dt_rstmgr_reset_req_src_t
dt_rstmgr_hw_reset_req_src
(
dt_rstmgr_t
dt,
size_t
idx) {
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dt_rstmgr_reset_req_src_t
invalid_req = {
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.inst_id =
kDtInstanceIdUnknown
,
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.reset_req =
kDtResetUnknown
,
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};
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if
(idx >= 5) {
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return
invalid_req;
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}
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return
TRY_GET_DT
(dt, invalid_req)->rstmgr_ext.hw_req[idx];
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}
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(darjeeling)
hw
top
dt
dt_rstmgr.c
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