dt_otp_ctrl.c

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// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Device table API auto-generated by `dtgen`
 
/**
 * @file
 * @brief Device Tables (DT) for IP otp_ctrl and top darjeeling.
 */
 
#include "dt/dt_otp_ctrl.h"
 
 
#include "otp_ctrl_regs.h"
 
 
/**
 * Description of instances.
 */
typedef struct dt_desc_otp_ctrl {
  dt_instance_id_t inst_id; /**< Instance ID */
  uint32_t base_addr[kDtOtpCtrlRegBlockCount]; /**< Base address of each register block */
  /**
   * PLIC ID of the first IRQ of this instance
   * 
   * This can be `kDtPlicIrqIdNone` if the block is not connected to the PLIC.
   */
  top_darjeeling_plic_irq_id_t first_irq;
  /**
   * Alert ID of the first Alert of this instance.
   * 
   * This value is undefined if the block is not connected to the Alert Handler.
   */
  top_darjeeling_alert_id_t first_alert;
  dt_clock_t clock[kDtOtpCtrlClockCount]; /**< Clock signal connected to each clock port */
  dt_reset_t reset[kDtOtpCtrlResetCount]; /**< Reset signal connected to each reset port */
  struct {
    dt_otp_partition_info_t info[15]; /**< List of SW readable OTP partitions */
  } sw_readable_partitions; /**< Extension */
} dt_desc_otp_ctrl_t;
 
 
 
 
static const dt_desc_otp_ctrl_t otp_ctrl_desc[kDtOtpCtrlCount] = {
  [kDtOtpCtrl] = {
    .inst_id = kDtInstanceIdOtpCtrl,
    .base_addr = {
      [kDtOtpCtrlRegBlockCore] = 0x30130000,
    },
    .first_irq = kTopDarjeelingPlicIrqIdOtpCtrlOtpOperationDone,
    .first_alert = kTopDarjeelingAlertIdOtpCtrlFatalMacroError,
    .clock = {
      [kDtOtpCtrlClockClk] = kDtClockIoDiv4,
      [kDtOtpCtrlClockEdn] = kDtClockMain,
    },
    .reset = {
      [kDtOtpCtrlResetRst] = kDtResetLcIoDiv4,
      [kDtOtpCtrlResetEdn] = kDtResetLc,
    },
    .sw_readable_partitions = {
      .info = {
        [kOtpPartitionVendorTest] = {
          .start_addr = OTP_CTRL_PARAM_VENDOR_TEST_OFFSET,
          .size = OTP_CTRL_PARAM_VENDOR_TEST_SIZE - OTP_CTRL_PARAM_VENDOR_TEST_DIGEST_SIZE,
          .digest_addr = OTP_CTRL_VENDOR_TEST_DIGEST_0_REG_OFFSET,
          .align_mask = 0x3,
        },
        [kOtpPartitionCreatorSwCfg] = {
          .start_addr = OTP_CTRL_PARAM_CREATOR_SW_CFG_OFFSET,
          .size = OTP_CTRL_PARAM_CREATOR_SW_CFG_SIZE - OTP_CTRL_PARAM_CREATOR_SW_CFG_DIGEST_SIZE,
          .digest_addr = OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_REG_OFFSET,
          .align_mask = 0x3,
        },
        [kOtpPartitionOwnerSwCfg] = {
          .start_addr = OTP_CTRL_PARAM_OWNER_SW_CFG_OFFSET,
          .size = OTP_CTRL_PARAM_OWNER_SW_CFG_SIZE - OTP_CTRL_PARAM_OWNER_SW_CFG_DIGEST_SIZE,
          .digest_addr = OTP_CTRL_OWNER_SW_CFG_DIGEST_0_REG_OFFSET,
          .align_mask = 0x3,
        },
        [kOtpPartitionRotCreatorAuth] = {
          .start_addr = OTP_CTRL_PARAM_ROT_CREATOR_AUTH_OFFSET,
          .size = OTP_CTRL_PARAM_ROT_CREATOR_AUTH_SIZE - OTP_CTRL_PARAM_ROT_CREATOR_AUTH_DIGEST_SIZE,
          .digest_addr = OTP_CTRL_ROT_CREATOR_AUTH_DIGEST_0_REG_OFFSET,
          .align_mask = 0x3,
        },
        [kOtpPartitionRotOwnerAuthSlot0] = {
          .start_addr = OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_OFFSET,
          .size = OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_SIZE - OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT0_DIGEST_SIZE,
          .digest_addr = OTP_CTRL_ROT_OWNER_AUTH_SLOT0_DIGEST_0_REG_OFFSET,
          .align_mask = 0x3,
        },
        [kOtpPartitionRotOwnerAuthSlot1] = {
          .start_addr = OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_OFFSET,
          .size = OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_SIZE - OTP_CTRL_PARAM_ROT_OWNER_AUTH_SLOT1_DIGEST_SIZE,
          .digest_addr = OTP_CTRL_ROT_OWNER_AUTH_SLOT1_DIGEST_0_REG_OFFSET,
          .align_mask = 0x3,
        },
        [kOtpPartitionPlatIntegAuthSlot0] = {
          .start_addr = OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_OFFSET,
          .size = OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_SIZE - OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT0_DIGEST_SIZE,
          .digest_addr = OTP_CTRL_PLAT_INTEG_AUTH_SLOT0_DIGEST_0_REG_OFFSET,
          .align_mask = 0x3,
        },
        [kOtpPartitionPlatIntegAuthSlot1] = {
          .start_addr = OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_OFFSET,
          .size = OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_SIZE - OTP_CTRL_PARAM_PLAT_INTEG_AUTH_SLOT1_DIGEST_SIZE,
          .digest_addr = OTP_CTRL_PLAT_INTEG_AUTH_SLOT1_DIGEST_0_REG_OFFSET,
          .align_mask = 0x3,
        },
        [kOtpPartitionPlatOwnerAuthSlot0] = {
          .start_addr = OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_OFFSET,
          .size = OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_SIZE - OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT0_DIGEST_SIZE,
          .digest_addr = OTP_CTRL_PLAT_OWNER_AUTH_SLOT0_DIGEST_0_REG_OFFSET,
          .align_mask = 0x3,
        },
        [kOtpPartitionPlatOwnerAuthSlot1] = {
          .start_addr = OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_OFFSET,
          .size = OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_SIZE - OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT1_DIGEST_SIZE,
          .digest_addr = OTP_CTRL_PLAT_OWNER_AUTH_SLOT1_DIGEST_0_REG_OFFSET,
          .align_mask = 0x3,
        },
        [kOtpPartitionPlatOwnerAuthSlot2] = {
          .start_addr = OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_OFFSET,
          .size = OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_SIZE - OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT2_DIGEST_SIZE,
          .digest_addr = OTP_CTRL_PLAT_OWNER_AUTH_SLOT2_DIGEST_0_REG_OFFSET,
          .align_mask = 0x3,
        },
        [kOtpPartitionPlatOwnerAuthSlot3] = {
          .start_addr = OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_OFFSET,
          .size = OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_SIZE - OTP_CTRL_PARAM_PLAT_OWNER_AUTH_SLOT3_DIGEST_SIZE,
          .digest_addr = OTP_CTRL_PLAT_OWNER_AUTH_SLOT3_DIGEST_0_REG_OFFSET,
          .align_mask = 0x3,
        },
        [kOtpPartitionRomPatch] = {
          .start_addr = OTP_CTRL_PARAM_ROM_PATCH_OFFSET,
          .size = OTP_CTRL_PARAM_ROM_PATCH_SIZE - OTP_CTRL_PARAM_ROM_PATCH_DIGEST_SIZE,
          .digest_addr = OTP_CTRL_ROM_PATCH_DIGEST_0_REG_OFFSET,
          .align_mask = 0x3,
        },
        [kOtpPartitionHwCfg0] = {
          .start_addr = OTP_CTRL_PARAM_HW_CFG0_OFFSET,
          .size = OTP_CTRL_PARAM_HW_CFG0_SIZE - OTP_CTRL_PARAM_HW_CFG0_DIGEST_SIZE,
          .digest_addr = OTP_CTRL_HW_CFG0_DIGEST_0_REG_OFFSET,
          .align_mask = 0x3,
        },
        [kOtpPartitionHwCfg1] = {
          .start_addr = OTP_CTRL_PARAM_HW_CFG1_OFFSET,
          .size = OTP_CTRL_PARAM_HW_CFG1_SIZE - OTP_CTRL_PARAM_HW_CFG1_DIGEST_SIZE,
          .digest_addr = OTP_CTRL_HW_CFG1_DIGEST_0_REG_OFFSET,
          .align_mask = 0x3,
        },
      },
    },
  },
};
 
/**
 * Return a pointer to the `dt_otp_ctrl_desc_t` structure of the requested
 * `dt` if it's a valid index. Otherwise, this macro will `return` (i.e. exit
 * the function) with the provided default value.
 */
#define TRY_GET_DT(dt, default)   ({     if ((dt) < (dt_otp_ctrl_t)0 || (dt) >= kDtOtpCtrlCount)       return (default);     &otp_ctrl_desc[dt];   })
 
dt_otp_ctrl_t dt_otp_ctrl_from_instance_id(dt_instance_id_t inst_id) {
  if (inst_id >= kDtInstanceIdOtpCtrl && inst_id <= kDtInstanceIdOtpCtrl) {
    return (dt_otp_ctrl_t)(inst_id - kDtInstanceIdOtpCtrl);
  }
  return (dt_otp_ctrl_t)0;
}
 
dt_instance_id_t dt_otp_ctrl_instance_id(
    dt_otp_ctrl_t dt) {
  return TRY_GET_DT(dt, kDtInstanceIdUnknown)->inst_id;
}
 
uint32_t dt_otp_ctrl_reg_block(
    dt_otp_ctrl_t dt,
    dt_otp_ctrl_reg_block_t reg_block) {
  // Return a recognizable address in case of wrong argument.
  return TRY_GET_DT(dt, 0xdeadbeef)->base_addr[reg_block];
}
 
dt_plic_irq_id_t dt_otp_ctrl_irq_to_plic_id(
    dt_otp_ctrl_t dt,
    dt_otp_ctrl_irq_t irq) {
  dt_plic_irq_id_t first_irq = TRY_GET_DT(dt, kDtPlicIrqIdNone)->first_irq;
  if (first_irq == kDtPlicIrqIdNone) {
    return kDtPlicIrqIdNone;
  }
  return (dt_plic_irq_id_t)((uint32_t)first_irq + (uint32_t)irq);
}
 
dt_otp_ctrl_irq_t dt_otp_ctrl_irq_from_plic_id(
    dt_otp_ctrl_t dt,
    dt_plic_irq_id_t irq) {
  dt_otp_ctrl_irq_t count = kDtOtpCtrlIrqCount;
  dt_plic_irq_id_t first_irq = TRY_GET_DT(dt, count)->first_irq;
  if (first_irq == kDtPlicIrqIdNone) {
    return count;
  }
  if (irq < first_irq || irq >= first_irq + (dt_plic_irq_id_t)count) {
    return count;
  }
  return (dt_otp_ctrl_irq_t)(irq - first_irq);
}
 
 
dt_alert_id_t dt_otp_ctrl_alert_to_alert_id(
    dt_otp_ctrl_t dt,
    dt_otp_ctrl_alert_t alert) {
  return (dt_alert_id_t)((uint32_t)otp_ctrl_desc[dt].first_alert + (uint32_t)alert);
}
 
dt_otp_ctrl_alert_t dt_otp_ctrl_alert_from_alert_id(
    dt_otp_ctrl_t dt,
    dt_alert_id_t alert) {
  dt_otp_ctrl_alert_t count = kDtOtpCtrlAlertCount;
  if (alert < otp_ctrl_desc[dt].first_alert || alert >= otp_ctrl_desc[dt].first_alert + (dt_alert_id_t)count) {
    return count;
  }
  return (dt_otp_ctrl_alert_t)(alert - otp_ctrl_desc[dt].first_alert);
}
 
 
 
dt_clock_t dt_otp_ctrl_clock(
    dt_otp_ctrl_t dt,
    dt_otp_ctrl_clock_t clk) {
  // Return the first clock in case of invalid argument.
  return TRY_GET_DT(dt, (dt_clock_t)0)->clock[clk];
}
 
dt_reset_t dt_otp_ctrl_reset(
    dt_otp_ctrl_t dt,
    dt_otp_ctrl_reset_t rst) {
  const dt_otp_ctrl_reset_t count = kDtOtpCtrlResetCount;
  if (rst >= count) {
    return kDtResetUnknown;
  }
  return TRY_GET_DT(dt, kDtResetUnknown)->reset[rst];
}
 
 
 
 
dt_otp_partition_info_t
dt_otp_ctrl_sw_readable_partition(dt_otp_ctrl_t dt, otp_partition_t partition) {
  dt_otp_partition_info_t invalid_part =  {
   .start_addr = 0xdeadbeef,
   .size = 0x0,
   .digest_addr = 0xdeadbeef,
   .align_mask = 0x0,
 };
  return TRY_GET_DT(dt, invalid_part)->sw_readable_partitions.info[partition];
}