Software APIs
dt_otbn.c
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7/**
8 * @file
9 * @brief Device Tables (DT) for IP otbn and top darjeeling.
10 */
11
12#include "hw/top/dt/dt_otbn.h"
13
14
15
16/**
17 * Description of instances.
18 */
19typedef struct dt_desc_otbn {
20 dt_instance_id_t inst_id; /**< Instance ID */
21 uint32_t reg_addr[kDtOtbnRegBlockCount]; /**< Base address of each register block */
22 uint32_t mem_addr[kDtOtbnMemoryCount]; /**< Base address of each memory */
23 uint32_t mem_size[kDtOtbnMemoryCount]; /**< Size in bytes of each memory */
24 /**
25 * PLIC ID of the first IRQ of this instance
26 *
27 * This can be `kDtPlicIrqIdNone` if the block is not connected to the PLIC.
28 */
30 /**
31 * Alert ID of the first Alert of this instance.
32 *
33 * This value is undefined if the block is not connected to the Alert Handler.
34 */
36 dt_clock_t clock[kDtOtbnClockCount]; /**< Clock signal connected to each clock port */
37 dt_reset_t reset[kDtOtbnResetCount]; /**< Reset signal connected to each reset port */
39
40
41
42
43static const dt_desc_otbn_t otbn_desc[kDtOtbnCount] = {
44 [kDtOtbn] = {
45 .inst_id = kDtInstanceIdOtbn,
46 .reg_addr = {
47 [kDtOtbnRegBlockCore] = 0x21130000,
48 },
49 .mem_addr = {
50 },
51 .mem_size = {
52 },
54 .first_alert = kTopDarjeelingAlertIdOtbnFatal,
55 .clock = {
59 },
60 .reset = {
64 },
65 },
66};
67
68/**
69 * Return a pointer to the `dt_otbn_desc_t` structure of the requested
70 * `dt` if it's a valid index. Otherwise, this macro will `return` (i.e. exit
71 * the function) with the provided default value.
72 */
73#define TRY_GET_DT(dt, default) ({ if ((dt) < (dt_otbn_t)0 || (dt) >= kDtOtbnCount) return (default); &otbn_desc[dt]; })
74
76 if (inst_id >= kDtInstanceIdOtbn && inst_id <= kDtInstanceIdOtbn) {
77 return (dt_otbn_t)(inst_id - kDtInstanceIdOtbn);
78 }
79 return (dt_otbn_t)0;
80}
81
86
88 dt_otbn_t dt,
89 dt_otbn_reg_block_t reg_block) {
90 // Return a recognizable address in case of wrong argument.
91 return TRY_GET_DT(dt, 0xdeadbeef)->reg_addr[reg_block];
92}
93
95 dt_otbn_t dt,
96 dt_otbn_memory_t mem) {
97 // Return a recognizable address in case of wrong argument.
98 return TRY_GET_DT(dt, 0xdeadbeef)->mem_addr[mem];
99}
100
102 dt_otbn_t dt,
103 dt_otbn_memory_t mem) {
104 // Return an empty size in case of wrong argument.
105 return TRY_GET_DT(dt, 0)->mem_size[mem];
106}
107
109 dt_otbn_t dt,
110 dt_otbn_irq_t irq) {
111 dt_plic_irq_id_t first_irq = TRY_GET_DT(dt, kDtPlicIrqIdNone)->first_irq;
112 if (first_irq == kDtPlicIrqIdNone) {
113 return kDtPlicIrqIdNone;
114 }
115 return (dt_plic_irq_id_t)((uint32_t)first_irq + (uint32_t)irq);
116}
117
119 dt_otbn_t dt,
120 dt_plic_irq_id_t irq) {
121 dt_otbn_irq_t count = kDtOtbnIrqCount;
122 dt_plic_irq_id_t first_irq = TRY_GET_DT(dt, count)->first_irq;
123 if (first_irq == kDtPlicIrqIdNone) {
124 return count;
125 }
126 if (irq < first_irq || irq >= first_irq + (dt_plic_irq_id_t)count) {
127 return count;
128 }
129 return (dt_otbn_irq_t)(irq - first_irq);
130}
131
132
134 dt_otbn_t dt,
135 dt_otbn_alert_t alert) {
136 return (dt_alert_id_t)((uint32_t)otbn_desc[dt].first_alert + (uint32_t)alert);
137}
138
140 dt_otbn_t dt,
141 dt_alert_id_t alert) {
142 dt_otbn_alert_t count = kDtOtbnAlertCount;
143 if (alert < otbn_desc[dt].first_alert || alert >= otbn_desc[dt].first_alert + (dt_alert_id_t)count) {
144 return count;
145 }
146 return (dt_otbn_alert_t)(alert - otbn_desc[dt].first_alert);
147}
148
149
150
152 dt_otbn_t dt,
153 dt_otbn_clock_t clk) {
154 // Return the first clock in case of invalid argument.
155 return TRY_GET_DT(dt, (dt_clock_t)0)->clock[clk];
156}
157
159 dt_otbn_t dt,
160 dt_otbn_reset_t rst) {
161 const dt_otbn_reset_t count = kDtOtbnResetCount;
162 if (rst >= count) {
163 return kDtResetUnknown;
164 }
165 return TRY_GET_DT(dt, kDtResetUnknown)->reset[rst];
166}
167
168