dt_clkmgr.c

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// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Device table API auto-generated by `dtgen`
 
/**
 * @file
 * @brief Device Tables (DT) for IP clkmgr and top darjeeling.
 */
 
#include "dt/dt_clkmgr.h"
 
 
 
/**
 * Description of instances.
 */
typedef struct dt_desc_clkmgr {
  dt_instance_id_t inst_id; /**< Instance ID */
  uint32_t base_addr[kDtClkmgrRegBlockCount]; /**< Base address of each register block */
  /**
   * Alert ID of the first Alert of this instance.
   * 
   * This value is undefined if the block is not connected to the Alert Handler.
   */
  top_darjeeling_alert_id_t first_alert;
  dt_clock_t clock[kDtClkmgrClockCount]; /**< Clock signal connected to each clock port */
  dt_reset_t reset[kDtClkmgrResetCount]; /**< Reset signal connected to each reset port */
  struct {
    dt_instance_id_t sw_clks[2]; /**< List of gateable clocks, in the order of the register fields */
    dt_instance_id_t hint_clks[4]; /**< List of hintable clocks, in the order of the register fields */
  } ext; /**< Extension */
} dt_desc_clkmgr_t;
 
 
 
 
static const dt_desc_clkmgr_t clkmgr_desc[kDtClkmgrCount] = {
  [kDtClkmgrAon] = {
    .inst_id = kDtInstanceIdClkmgrAon,
    .base_addr = {
      [kDtClkmgrRegBlockCore] = 0x30420000,
    },
    .first_alert = kTopDarjeelingAlertIdClkmgrAonRecovFault,
    .clock = {
      [kDtClkmgrClockClk] = kDtClockIoDiv4,
      [kDtClkmgrClockMain] = kDtClockMain,
      [kDtClkmgrClockIo] = kDtClockIo,
      [kDtClkmgrClockAon] = kDtClockAon,
    },
    .reset = {
      [kDtClkmgrResetRst] = kDtResetLcIoDiv4,
      [kDtClkmgrResetAon] = kDtResetLcAon,
      [kDtClkmgrResetIo] = kDtResetLcIo,
      [kDtClkmgrResetIoDiv2] = kDtResetLcIoDiv2,
      [kDtClkmgrResetIoDiv4] = kDtResetLcIoDiv4,
      [kDtClkmgrResetMain] = kDtResetLc,
      [kDtClkmgrResetRoot] = kDtResetPorIoDiv4,
      [kDtClkmgrResetRootIo] = kDtResetPorIo,
      [kDtClkmgrResetRootIoDiv2] = kDtResetPorIoDiv2,
      [kDtClkmgrResetRootIoDiv4] = kDtResetPorIoDiv4,
      [kDtClkmgrResetRootMain] = kDtResetPor,
    },
    .ext = {
      .sw_clks = {
        [0] = kDtInstanceIdUart0,
        [1] = kDtInstanceIdSpiDevice,
      },
      .hint_clks = {
        [0] = kDtInstanceIdAes,
        [1] = kDtInstanceIdHmac,
        [2] = kDtInstanceIdKmac,
        [3] = kDtInstanceIdOtbn,
      },
    },
  },
};
 
/**
 * Return a pointer to the `dt_clkmgr_desc_t` structure of the requested
 * `dt` if it's a valid index. Otherwise, this macro will `return` (i.e. exit
 * the function) with the provided default value.
 */
#define TRY_GET_DT(dt, default)   ({     if ((dt) < (dt_clkmgr_t)0 || (dt) >= kDtClkmgrCount)       return (default);     &clkmgr_desc[dt];   })
 
dt_clkmgr_t dt_clkmgr_from_instance_id(dt_instance_id_t inst_id) {
  if (inst_id >= kDtInstanceIdClkmgrAon && inst_id <= kDtInstanceIdClkmgrAon) {
    return (dt_clkmgr_t)(inst_id - kDtInstanceIdClkmgrAon);
  }
  return (dt_clkmgr_t)0;
}
 
dt_instance_id_t dt_clkmgr_instance_id(
    dt_clkmgr_t dt) {
  return TRY_GET_DT(dt, kDtInstanceIdUnknown)->inst_id;
}
 
uint32_t dt_clkmgr_reg_block(
    dt_clkmgr_t dt,
    dt_clkmgr_reg_block_t reg_block) {
  // Return a recognizable address in case of wrong argument.
  return TRY_GET_DT(dt, 0xdeadbeef)->base_addr[reg_block];
}
 
 
dt_alert_id_t dt_clkmgr_alert_to_alert_id(
    dt_clkmgr_t dt,
    dt_clkmgr_alert_t alert) {
  return (dt_alert_id_t)((uint32_t)clkmgr_desc[dt].first_alert + (uint32_t)alert);
}
 
dt_clkmgr_alert_t dt_clkmgr_alert_from_alert_id(
    dt_clkmgr_t dt,
    dt_alert_id_t alert) {
  dt_clkmgr_alert_t count = kDtClkmgrAlertCount;
  if (alert < clkmgr_desc[dt].first_alert || alert >= clkmgr_desc[dt].first_alert + (dt_alert_id_t)count) {
    return count;
  }
  return (dt_clkmgr_alert_t)(alert - clkmgr_desc[dt].first_alert);
}
 
 
 
dt_clock_t dt_clkmgr_clock(
    dt_clkmgr_t dt,
    dt_clkmgr_clock_t clk) {
  // Return the first clock in case of invalid argument.
  return TRY_GET_DT(dt, (dt_clock_t)0)->clock[clk];
}
 
dt_reset_t dt_clkmgr_reset(
    dt_clkmgr_t dt,
    dt_clkmgr_reset_t rst) {
  const dt_clkmgr_reset_t count = kDtClkmgrResetCount;
  if (rst >= count) {
    return kDtResetUnknown;
  }
  return TRY_GET_DT(dt, kDtResetUnknown)->reset[rst];
}
 
 
size_t dt_clkmgr_gateable_clock_count(dt_clkmgr_t dt) {
  return 2;
}
 
dt_instance_id_t dt_clkmgr_gateable_clock(dt_clkmgr_t dt, size_t idx) {
  return TRY_GET_DT(dt, kDtInstanceIdUnknown)->ext.sw_clks[idx];
}
 
size_t dt_clkmgr_hintable_clock_count(dt_clkmgr_t dt) {
  return 4;
}
 
dt_instance_id_t dt_clkmgr_hintable_clock(dt_clkmgr_t dt, size_t idx) {
  return TRY_GET_DT(dt, kDtInstanceIdUnknown)->ext.hint_clks[idx];
}