dt_api.h

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// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Device table API auto-generated by `dtgen`
 
#ifndef OPENTITAN_TOP_DARJEELING_DT_API_H_
#define OPENTITAN_TOP_DARJEELING_DT_API_H_
 
/**
 * @file
 * @brief Device Tables (DT) API for top darjeeling
 *
 * This file contains the type definitions and global functions of the DT.
 *
 * The DT models the chip as a collection of instances. Each instance has
 * a type (the IP block) and a number of attributes such as I/Os, IRQs
 * and so on. The DT also provides top-specific lists of global resources
 * such as I/O pads, clocks and interrupts.
 */
 
#include <stddef.h>
#include <stdint.h>
#include "hw/top_darjeeling/sw/autogen/top_darjeeling.h"
 
/**
 * List of device types.
 *
 * Device types are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_device_type {
  kDtDeviceTypeUnknown = 0, /**< Instance of unknown type */
  kDtDeviceTypeAcRangeCheck = 1, /**< instance of ac_range_check */
  kDtDeviceTypeAes = 2, /**< instance of aes */
  kDtDeviceTypeAlertHandler = 3, /**< instance of alert_handler */
  kDtDeviceTypeAonTimer = 4, /**< instance of aon_timer */
  kDtDeviceTypeAst = 5, /**< instance of ast */
  kDtDeviceTypeClkmgr = 6, /**< instance of clkmgr */
  kDtDeviceTypeCsrng = 7, /**< instance of csrng */
  kDtDeviceTypeDma = 8, /**< instance of dma */
  kDtDeviceTypeEdn = 9, /**< instance of edn */
  kDtDeviceTypeGpio = 10, /**< instance of gpio */
  kDtDeviceTypeHmac = 11, /**< instance of hmac */
  kDtDeviceTypeI2c = 12, /**< instance of i2c */
  kDtDeviceTypeKeymgrDpe = 13, /**< instance of keymgr_dpe */
  kDtDeviceTypeKmac = 14, /**< instance of kmac */
  kDtDeviceTypeLcCtrl = 15, /**< instance of lc_ctrl */
  kDtDeviceTypeMbx = 16, /**< instance of mbx */
  kDtDeviceTypeOtbn = 17, /**< instance of otbn */
  kDtDeviceTypeOtpCtrl = 18, /**< instance of otp_ctrl */
  kDtDeviceTypeOtpMacro = 19, /**< instance of otp_macro */
  kDtDeviceTypePinmux = 20, /**< instance of pinmux */
  kDtDeviceTypePwrmgr = 21, /**< instance of pwrmgr */
  kDtDeviceTypeRaclCtrl = 22, /**< instance of racl_ctrl */
  kDtDeviceTypeRomCtrl = 23, /**< instance of rom_ctrl */
  kDtDeviceTypeRstmgr = 24, /**< instance of rstmgr */
  kDtDeviceTypeRvCoreIbex = 25, /**< instance of rv_core_ibex */
  kDtDeviceTypeRvDm = 26, /**< instance of rv_dm */
  kDtDeviceTypeRvPlic = 27, /**< instance of rv_plic */
  kDtDeviceTypeRvTimer = 28, /**< instance of rv_timer */
  kDtDeviceTypeSocDbgCtrl = 29, /**< instance of soc_dbg_ctrl */
  kDtDeviceTypeSocProxy = 30, /**< instance of soc_proxy */
  kDtDeviceTypeSpiDevice = 31, /**< instance of spi_device */
  kDtDeviceTypeSpiHost = 32, /**< instance of spi_host */
  kDtDeviceTypeSramCtrl = 33, /**< instance of sram_ctrl */
  kDtDeviceTypeUart = 34, /**< instance of uart */
  kDtDeviceTypeCount = 35, /**< \internal Number of instance types */
} dt_device_type_t;
 
/**
 * List of instance IDs.
 *
 * Instance IDs are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_instance_id {
  kDtInstanceIdUnknown = 0, /**< Unknown instance */
  kDtInstanceIdAcRangeCheck = 1, /**< instance ac_range_check of ac_range_check */
  kDtInstanceIdAes = 2, /**< instance aes of aes */
  kDtInstanceIdAlertHandler = 3, /**< instance alert_handler of alert_handler */
  kDtInstanceIdAonTimerAon = 4, /**< instance aon_timer_aon of aon_timer */
  kDtInstanceIdAst = 5, /**< instance ast of ast */
  kDtInstanceIdClkmgrAon = 6, /**< instance clkmgr_aon of clkmgr */
  kDtInstanceIdCsrng = 7, /**< instance csrng of csrng */
  kDtInstanceIdDma = 8, /**< instance dma of dma */
  kDtInstanceIdEdn0 = 9, /**< instance edn0 of edn */
  kDtInstanceIdEdn1 = 10, /**< instance edn1 of edn */
  kDtInstanceIdGpio = 11, /**< instance gpio of gpio */
  kDtInstanceIdHmac = 12, /**< instance hmac of hmac */
  kDtInstanceIdI2c0 = 13, /**< instance i2c0 of i2c */
  kDtInstanceIdKeymgrDpe = 14, /**< instance keymgr_dpe of keymgr_dpe */
  kDtInstanceIdKmac = 15, /**< instance kmac of kmac */
  kDtInstanceIdLcCtrl = 16, /**< instance lc_ctrl of lc_ctrl */
  kDtInstanceIdMbx0 = 17, /**< instance mbx0 of mbx */
  kDtInstanceIdMbx1 = 18, /**< instance mbx1 of mbx */
  kDtInstanceIdMbx2 = 19, /**< instance mbx2 of mbx */
  kDtInstanceIdMbx3 = 20, /**< instance mbx3 of mbx */
  kDtInstanceIdMbx4 = 21, /**< instance mbx4 of mbx */
  kDtInstanceIdMbx5 = 22, /**< instance mbx5 of mbx */
  kDtInstanceIdMbx6 = 23, /**< instance mbx6 of mbx */
  kDtInstanceIdMbxJtag = 24, /**< instance mbx_jtag of mbx */
  kDtInstanceIdMbxPcie0 = 25, /**< instance mbx_pcie0 of mbx */
  kDtInstanceIdMbxPcie1 = 26, /**< instance mbx_pcie1 of mbx */
  kDtInstanceIdOtbn = 27, /**< instance otbn of otbn */
  kDtInstanceIdOtpCtrl = 28, /**< instance otp_ctrl of otp_ctrl */
  kDtInstanceIdOtpMacro = 29, /**< instance otp_macro of otp_macro */
  kDtInstanceIdPinmuxAon = 30, /**< instance pinmux_aon of pinmux */
  kDtInstanceIdPwrmgrAon = 31, /**< instance pwrmgr_aon of pwrmgr */
  kDtInstanceIdRaclCtrl = 32, /**< instance racl_ctrl of racl_ctrl */
  kDtInstanceIdRomCtrl0 = 33, /**< instance rom_ctrl0 of rom_ctrl */
  kDtInstanceIdRomCtrl1 = 34, /**< instance rom_ctrl1 of rom_ctrl */
  kDtInstanceIdRstmgrAon = 35, /**< instance rstmgr_aon of rstmgr */
  kDtInstanceIdRvCoreIbex = 36, /**< instance rv_core_ibex of rv_core_ibex */
  kDtInstanceIdRvDm = 37, /**< instance rv_dm of rv_dm */
  kDtInstanceIdRvPlic = 38, /**< instance rv_plic of rv_plic */
  kDtInstanceIdRvTimer = 39, /**< instance rv_timer of rv_timer */
  kDtInstanceIdSocDbgCtrl = 40, /**< instance soc_dbg_ctrl of soc_dbg_ctrl */
  kDtInstanceIdSocProxy = 41, /**< instance soc_proxy of soc_proxy */
  kDtInstanceIdSpiDevice = 42, /**< instance spi_device of spi_device */
  kDtInstanceIdSpiHost0 = 43, /**< instance spi_host0 of spi_host */
  kDtInstanceIdSramCtrlRetAon = 44, /**< instance sram_ctrl_ret_aon of sram_ctrl */
  kDtInstanceIdSramCtrlMain = 45, /**< instance sram_ctrl_main of sram_ctrl */
  kDtInstanceIdSramCtrlMbox = 46, /**< instance sram_ctrl_mbox of sram_ctrl */
  kDtInstanceIdUart0 = 47, /**< instance uart0 of uart */
  kDtInstanceIdCount = 48, /**< \internal Number of instance IDs */
} dt_instance_id_t;
 
/**
 * Get the instance type of a device instance.
 *
 * For example the instance type of `kDtUart0` is `kDtInstanceTypeUart`.
 *
 * @param id An instance ID.
 * @return The instance type, or `kDtInstanceIdUnknown` if the ID is not valid.
 */
dt_device_type_t dt_device_type(dt_instance_id_t id);
 
/** PLIC IRQ ID type.
 *
 * This type represents a raw IRQ ID from the PLIC.
 *
 * This is an alias to the top's `plic_irq_id_t` type for backward compatibility
 * with existing code.
 */
typedef top_darjeeling_plic_irq_id_t dt_plic_irq_id_t;
 
/** PLIC IRQ ID for no interrupt. */
static const dt_plic_irq_id_t kDtPlicIrqIdNone=kTopDarjeelingPlicIrqIdNone;
 
/**
 * Get the instance ID for a given PLIC IRQ ID.
 *
 * For example, on earlgrey, the instance ID of `kTopEarlgreyPlicIrqIdUart0TxWatermark`
 * is `kDtInstanceIdUart0`. One can then use the type specific function to retrieve the
 * IRQ name, for example `dt_uart_irq_from_plic_id` for the UART.
 *
 * @param irq A PLIC ID.
 * @return The instance ID, or `kDtInstanceIdUnknown` if the PLIC ID is not valid.
 */
dt_instance_id_t dt_plic_id_to_instance_id(dt_plic_irq_id_t irq);
 
/**
 * Alert ID type.
 *
 * This type represents a raw alert ID from the Alert Handler.
 *
 * This is an alias to the top's `alert_id_t` type for backward compatability
 * with existing code.
 */
typedef top_darjeeling_alert_id_t dt_alert_id_t;
 
/** Number of alerts. */
enum {
  /** Total number of alert IDs. */
  kDtAlertCount = kTopDarjeelingAlertIdLast + 1,
};
 
/**
 * Get the instance ID for a given alert ID.
 *
 * For example, on earlgrey, the instance ID of `kTopEarlgreyAlertIdUart0FatalFault` is
 * `kDtInstanceIdUart0`. One can then use the type specific function to retrieve the
 * alert name, for example `dt_uart_alert_from_alert_id` for the UART.
 *
 * @param alert An alert ID.
 * @return The instance ID, or `kDtInstanceIdUnknown` if the alert ID is not valid.
 */
dt_instance_id_t dt_alert_id_to_instance_id(dt_alert_id_t alert);
 
/**
 * List of clocks.
 *
 * Clocks are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_clock {
  kDtClockMain = 0, /**< clock main */
  kDtClockIo = 1, /**< clock io */
  kDtClockAon = 2, /**< clock aon */
  kDtClockIoDiv2 = 3, /**< clock io_div2 */
  kDtClockIoDiv4 = 4, /**< clock io_div4 */
  kDtClockCount = 5, /**< \internal Number of clocks */
} dt_clock_t;
 
/**
 * Get the frequency of a clock.
 *
 * @param clk A clock ID.
 * @return Clock frequency in Hz.
 */
uint32_t dt_clock_frequency(dt_clock_t clk);
 
/**
 * List of resets.
 *
 * Resets are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_reset {
  kDtResetUnknown = 0, /**< Unknown reset */
  kDtResetPorAon = 1, /**< Reset node por_aon */
  kDtResetLcSrc = 2, /**< Reset node lc_src */
  kDtResetSysSrc = 3, /**< Reset node sys_src */
  kDtResetPor = 4, /**< Reset node por */
  kDtResetPorIo = 5, /**< Reset node por_io */
  kDtResetPorIoDiv2 = 6, /**< Reset node por_io_div2 */
  kDtResetPorIoDiv4 = 7, /**< Reset node por_io_div4 */
  kDtResetLc = 8, /**< Reset node lc */
  kDtResetLcAon = 9, /**< Reset node lc_aon */
  kDtResetLcIo = 10, /**< Reset node lc_io */
  kDtResetLcIoDiv2 = 11, /**< Reset node lc_io_div2 */
  kDtResetLcIoDiv4 = 12, /**< Reset node lc_io_div4 */
  kDtResetSys = 13, /**< Reset node sys */
  kDtResetSysIoDiv4 = 14, /**< Reset node sys_io_div4 */
  kDtResetSpiDevice = 15, /**< Reset node spi_device */
  kDtResetSpiHost0 = 16, /**< Reset node spi_host0 */
  kDtResetI2c0 = 17, /**< Reset node i2c0 */
  kDtResetCount = 18, /**< \internal Number of resets */
} dt_reset_t;
 
/**
 * List of pads names.
 */
typedef enum dt_pad {
  kDtPadMio0 = 0, /**< Muxed IO pad */
  kDtPadMio1 = 1, /**< Muxed IO pad */
  kDtPadMio2 = 2, /**< Muxed IO pad */
  kDtPadMio3 = 3, /**< Muxed IO pad */
  kDtPadMio4 = 4, /**< Muxed IO pad */
  kDtPadMio5 = 5, /**< Muxed IO pad */
  kDtPadMio6 = 6, /**< Muxed IO pad */
  kDtPadMio7 = 7, /**< Muxed IO pad */
  kDtPadMio8 = 8, /**< Muxed IO pad */
  kDtPadMio9 = 9, /**< Muxed IO pad */
  kDtPadMio10 = 10, /**< Muxed IO pad */
  kDtPadMio11 = 11, /**< Muxed IO pad */
  kDtPadSpiHost0Sd0 = 12, /**< SPI host data */
  kDtPadSpiHost0Sd1 = 13, /**< SPI host data */
  kDtPadSpiHost0Sd2 = 14, /**< SPI host data */
  kDtPadSpiHost0Sd3 = 15, /**< SPI host data */
  kDtPadSpiDeviceSd0 = 16, /**< SPI device data */
  kDtPadSpiDeviceSd1 = 17, /**< SPI device data */
  kDtPadSpiDeviceSd2 = 18, /**< SPI device data */
  kDtPadSpiDeviceSd3 = 19, /**< SPI device data */
  kDtPadI2c0Scl = 20, /**< I2C clock */
  kDtPadI2c0Sda = 21, /**< I2C data */
  kDtPadGpioGpio0 = 22, /**< GPIO pad */
  kDtPadGpioGpio1 = 23, /**< GPIO pad */
  kDtPadGpioGpio2 = 24, /**< GPIO pad */
  kDtPadGpioGpio3 = 25, /**< GPIO pad */
  kDtPadGpioGpio4 = 26, /**< GPIO pad */
  kDtPadGpioGpio5 = 27, /**< GPIO pad */
  kDtPadGpioGpio6 = 28, /**< GPIO pad */
  kDtPadGpioGpio7 = 29, /**< GPIO pad */
  kDtPadGpioGpio8 = 30, /**< GPIO pad */
  kDtPadGpioGpio9 = 31, /**< GPIO pad */
  kDtPadGpioGpio10 = 32, /**< GPIO pad */
  kDtPadGpioGpio11 = 33, /**< GPIO pad */
  kDtPadGpioGpio12 = 34, /**< GPIO pad */
  kDtPadGpioGpio13 = 35, /**< GPIO pad */
  kDtPadGpioGpio14 = 36, /**< GPIO pad */
  kDtPadGpioGpio15 = 37, /**< GPIO pad */
  kDtPadGpioGpio16 = 38, /**< GPIO pad */
  kDtPadGpioGpio17 = 39, /**< GPIO pad */
  kDtPadGpioGpio18 = 40, /**< GPIO pad */
  kDtPadGpioGpio19 = 41, /**< GPIO pad */
  kDtPadGpioGpio20 = 42, /**< GPIO pad */
  kDtPadGpioGpio21 = 43, /**< GPIO pad */
  kDtPadGpioGpio22 = 44, /**< GPIO pad */
  kDtPadGpioGpio23 = 45, /**< GPIO pad */
  kDtPadGpioGpio24 = 46, /**< GPIO pad */
  kDtPadGpioGpio25 = 47, /**< GPIO pad */
  kDtPadGpioGpio26 = 48, /**< GPIO pad */
  kDtPadGpioGpio27 = 49, /**< GPIO pad */
  kDtPadGpioGpio28 = 50, /**< GPIO pad */
  kDtPadGpioGpio29 = 51, /**< GPIO pad */
  kDtPadGpioGpio30 = 52, /**< GPIO pad */
  kDtPadGpioGpio31 = 53, /**< GPIO pad */
  kDtPadSpiDeviceSck = 54, /**< SPI device clock */
  kDtPadSpiDeviceCsb = 55, /**< SPI device chip select */
  kDtPadSpiDeviceTpmCsb = 56, /**< SPI device TPM chip select */
  kDtPadUart0Rx = 57, /**< UART receive */
  kDtPadSocProxySocGpi0 = 58, /**< SoC general purpose input */
  kDtPadSocProxySocGpi1 = 59, /**< SoC general purpose input */
  kDtPadSocProxySocGpi2 = 60, /**< SoC general purpose input */
  kDtPadSocProxySocGpi3 = 61, /**< SoC general purpose input */
  kDtPadSocProxySocGpi4 = 62, /**< SoC general purpose input */
  kDtPadSocProxySocGpi5 = 63, /**< SoC general purpose input */
  kDtPadSocProxySocGpi6 = 64, /**< SoC general purpose input */
  kDtPadSocProxySocGpi7 = 65, /**< SoC general purpose input */
  kDtPadSocProxySocGpi8 = 66, /**< SoC general purpose input */
  kDtPadSocProxySocGpi9 = 67, /**< SoC general purpose input */
  kDtPadSocProxySocGpi10 = 68, /**< SoC general purpose input */
  kDtPadSocProxySocGpi11 = 69, /**< SoC general purpose input */
  kDtPadSpiHost0Sck = 70, /**< SPI host clock */
  kDtPadSpiHost0Csb = 71, /**< SPI host chip select */
  kDtPadUart0Tx = 72, /**< UART transmit */
  kDtPadSocProxySocGpo0 = 73, /**< SoC general purpose output */
  kDtPadSocProxySocGpo1 = 74, /**< SoC general purpose output */
  kDtPadSocProxySocGpo2 = 75, /**< SoC general purpose output */
  kDtPadSocProxySocGpo3 = 76, /**< SoC general purpose output */
  kDtPadSocProxySocGpo4 = 77, /**< SoC general purpose output */
  kDtPadSocProxySocGpo5 = 78, /**< SoC general purpose output */
  kDtPadSocProxySocGpo6 = 79, /**< SoC general purpose output */
  kDtPadSocProxySocGpo7 = 80, /**< SoC general purpose output */
  kDtPadSocProxySocGpo8 = 81, /**< SoC general purpose output */
  kDtPadSocProxySocGpo9 = 82, /**< SoC general purpose output */
  kDtPadSocProxySocGpo10 = 83, /**< SoC general purpose output */
  kDtPadSocProxySocGpo11 = 84, /**< SoC general purpose output */
  kDtPadCount = 85, /**< \internal Number of pads */
} dt_pad_t;
 
/**
 * Pinmux types.
 *
 * These types are aliases to top-level types for backward compatibility
 * with existing code.
 */
typedef top_darjeeling_pinmux_peripheral_in_t dt_pinmux_peripheral_in_t;
typedef top_darjeeling_pinmux_insel_t dt_pinmux_insel_t;
typedef top_darjeeling_pinmux_outsel_t dt_pinmux_outsel_t;
typedef top_darjeeling_pinmux_mio_out_t dt_pinmux_mio_out_t;
typedef top_darjeeling_direct_pads_t dt_pinmux_direct_pad_t;
typedef top_darjeeling_muxed_pads_t  dt_pinmux_muxed_pad_t;
 
/** Type of peripheral I/O. */
typedef enum dt_periph_io_type {
  /** This peripheral I/O is connected to a muxed IO (MIO). */
  kDtPeriphIoTypeMio,
  /** This peripheral I/O is connected to a direct IO (DIO). */
  kDtPeriphIoTypeDio,
  /** This peripheral I/O is not connected to either a MIO or a DIO. */
  kDtPeriphIoTypeUnspecified,
} dt_periph_io_type_t;
 
 
/** Direction of a peripheral I/O. */
typedef enum dt_periph_io_dir {
  /** This peripheral I/O is an input. */
  kDtPeriphIoDirIn,
  /** This peripheral I/O is an output */
  kDtPeriphIoDirOut,
  /** This peripheral I/O is an input-output */
  kDtPeriphIoDirInout,
} dt_periph_io_dir_t;
 
/** Peripheral I/O description.
 *
 * A `dt_periph_io_t` represents a HW IP block peripheral I/O, which can be an input, output or both.
 * Importantly, this only represents how the block peripheral I/O is wired, i.e.
 * whether it is connected a MIO or a direct IO on the pinmux, and the relevant information necessary to
 * configure it.
 *
 * **Note:** The fields of this structure are internal, use the dt_periph_io_* functions to access them.
 */
typedef struct dt_periph_io {
  struct {
    dt_periph_io_type_t type; /**< Peripheral I/O type */
    dt_periph_io_dir_t dir; /**< Peripheral I/O direction */
    /**
     * For `kDtPeriphIoTypeMio`: peripheral input number. This is the index of the MIO_PERIPH_INSEL register
     * that controls this peripheral I/O.
     * 
     * For `kDtPeriphIoTypeDio`: DIO pad number. This is the index of the various DIO_PAD_* registers
     * that control this peripheral I/O.
     */
    uint16_t periph_input_or_direct_pad;
    /**
     * For `kDtPeriphIoTypeMio`: peripheral output number. This is the value to put in the MIO_OUTSEL registers
     * to connect an output to this peripheral I/O. For `kDtPeriphIoTypeDio`: the pad index (`dt_pad_t`) to which this I/O is connected.
     */
    uint16_t outsel_or_dt_pad;
  } __internal; /**< Private fields */
} dt_periph_io_t;
 
 
/** Tie constantly to zero. */
static const dt_pinmux_outsel_t kDtPinmuxOutselConstantZero = kTopDarjeelingPinmuxOutselConstantZero;
 
/** Tie constantly to one. */
static const dt_pinmux_outsel_t kDtPinmuxOutselConstantOne = kTopDarjeelingPinmuxOutselConstantOne;
 
/** Tie constantly to high-Z. */
static const dt_pinmux_outsel_t kDtPinmuxOutselConstantHighZ = kTopDarjeelingPinmuxOutselConstantHighZ;
 
/* Peripheral I/O that is constantly tied to high-Z (output only) */
extern const dt_periph_io_t kDtPeriphIoConstantHighZ;
 
/* Peripheral I/O that is constantly tied to one (output only) */
extern const dt_periph_io_t kDtPeriphIoConstantZero;
 
/* Peripheral I/O that is constantly tied to zero (output only) */
extern const dt_periph_io_t kDtPeriphIoConstantOne;
 
/**
 * Return the type of a `dt_periph_io_t`.
 *
 * @param periph_io A peripheral I/O description.
 * @return The peripheral I/O type (MIO, DIO, etc).
 */
static inline dt_periph_io_type_t dt_periph_io_type(dt_periph_io_t periph_io) {
  return periph_io.__internal.type;
}
 
/**
 * Return the direction of a `dt_periph_io_t`.
 *
 * @param periph_io A peripheral I/O description.
 * @return The peripheral I/O direction.
 */
static inline dt_periph_io_dir_t dt_periph_io_dir(dt_periph_io_t periph_io) {
  return periph_io.__internal.dir;
}
 
/**
 * Return the peripheral input for an MIO peripheral I/O.
 *
 * This is the index of the `MIO_PERIPH_INSEL` pinmux register that controls this peripheral I/O.
 *
 * @param periph_io A peripheral I/O of type `kDtPeriphIoTypeMio`.
 * @return The peripheral input number of the MIO that this peripheral I/O is connected to.
 *
 * **Note:** This function only makes sense for peripheral I/Os of type `kDtPeriphIoTypeMio` which are
 * inputs (`kDtPeriphIoDirIn`). For any other peripheral I/O, the return value is unspecified.
 */
static inline dt_pinmux_peripheral_in_t dt_periph_io_mio_periph_input(dt_periph_io_t periph_io) {
  return (dt_pinmux_peripheral_in_t)periph_io.__internal.periph_input_or_direct_pad;
}
 
/**
 * Return the outsel for an MIO peripheral I/O.
 *
 * This is the value to put in the `MIO_OUTSEL` pinmux registers to connect a pad to this peripheral I/O.
 *
 * @param periph_io A peripheral I/O of type `kDtPeriphIoTypeMio`.
 * @return The outsel of the MIO that this peripheral I/O is connected to.
 *
 * **Note:** This function only makes sense for peripheral I/Os of type `kDtPeriphIoTypeMio` which are
 * outputs (`kDtPeriphIoDirOut`). For any other peripheral I/O, the return value is unspecified.
 */
static inline dt_pinmux_outsel_t dt_periph_io_mio_outsel(dt_periph_io_t periph_io) {
  return (dt_pinmux_outsel_t)periph_io.__internal.outsel_or_dt_pad;
}
 
/**
 * Return the direct pad number of a DIO peripheral I/O.
 *
 * This is the index of the various `DIO_PAD_*` pinmux registers that control this peripheral I/O.
 *
 * @param periph_io A peripheral I/O of type `kDtPeriphIoTypeDio`.
 * @return The direct pad number of the DIO that this peripheral I/O is connected to.
 *
 * **Note:** This function only makes sense for peripheral I/Os of type `kDtPeriphIoTypeDio` which are
 * either outputs or inouts. For any other peripheral I/O type, the return value is unspecified.
 */
static inline dt_pinmux_direct_pad_t dt_periph_io_dio_pad_index(dt_periph_io_t periph_io) {
  return (dt_pinmux_direct_pad_t)periph_io.__internal.periph_input_or_direct_pad;
}
 
/**
 * Return the pad of a DIO peripheral I/O.
 *
 * @param periph_io A peripheral I/O of type `kDtPeriphIoTypeDio`.
 * @return The pad to which this peripheral I/O is connected to.
 *
 * **Note:** This function only makes sense for peripheral I/Os of type `kDtPeriphIoTypeDio` which are
 * either outputs or inouts. For any other peripheral I/O type, the return value is unspecified.
 */
static inline dt_pad_t dt_periph_io_dio_pad(dt_periph_io_t periph_io) {
  return (dt_pad_t)periph_io.__internal.outsel_or_dt_pad;
}
 
/** Type of a pad. */
typedef enum dt_pad_type {
  /** This pad is a muxed IO (MIO). */
  kDtPadTypeMio,
  /** This pad is a direct IO (DIO). */
  kDtPadTypeDio,
  /** This pad is not an MIO or a DIO. */
  kDtPadTypeUnspecified,
} dt_pad_type_t;
 
/**
 * Return the type of a `dt_pad_t`.
 *
 * @param pad A pad description.
 * @return The pad type (MIO, DIO, etc).
 */
dt_pad_type_t dt_pad_type(dt_pad_t pad);
 
/**
 * Return the pad out number for an MIO pad.
 *
 * This is the index of the `MIO_OUT` registers that control this pad
 * (or the output part of this pad).
 *
 * @param pad A pad of type `kDtPadTypeMio`.
 * @return The pad out number of the MIO.
 *
 * **Note:** This function only makes sense for pads of type `kDtPadTypeMio` which are
 * either inputs or inouts. For any other pad, the return value is unspecified.
 */
dt_pinmux_mio_out_t dt_pad_mio_out(dt_pad_t pad);
 
/**
 * Return the pad out number for an MIO pad.
 *
 * This is the index of the `MIO_PAD` registers that control this pad
 * (or the output part of this pad).
 *
 * @param pad A pad of type `kDtPadTypeMio`.
 * @return The pad out number of the MIO.
 *
 * **Note:** This function only makes sense for pads of type `kDtPadTypeMio`.
 * For any other pad, the return value is unspecified.
 */
dt_pinmux_muxed_pad_t dt_pad_mio_pad_index(dt_pad_t pad);
 
/**
 * Return the insel for an MIO pad.
 *
 * This is the value to put in the `MIO_PERIPH_INSEL` registers to connect a peripheral I/O to this pad.
 *
 * @param pad A pad of type `kDtPadTypeMio`.
 * @return The insel of the MIO that this pad is connected to.
 *
 * **Note:** This function only makes sense for pads of type `kDtPadTypeMio`.
 * For any other pad, the return value is unspecified.
 */
dt_pinmux_insel_t dt_pad_mio_insel(dt_pad_t pad);
 
/**
 * Return the direct pad number of a DIO pad.
 *
 * This is the index of the various `DIO_PAD_*` registers that control this pad.
 *
 * @param pad A pad of type `kDtPadTypeDio`.
 * @return The direct pad number of the DID that this pad is connected to.
 *
 * **Note:** This function only makes sense for pads of type `kDtPeriphIoTypeDio` which are
 * either outputs or inouts. For any other pad type, the return value is unspecified.
 */
dt_pinmux_direct_pad_t dt_pad_dio_pad_index(dt_pad_t pad);
 
#endif  // OPENTITAN_TOP_DARJEELING_DT_API_H_