Software APIs
dt_api.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7#ifndef OPENTITAN_TOP_DARJEELING_DT_API_H_
8#define OPENTITAN_TOP_DARJEELING_DT_API_H_
9
10#ifdef __cplusplus
11extern "C" {
12#endif // __cplusplus
13
14/**
15 * @file
16 * @brief Device Tables (DT) API for top darjeeling
17 *
18 * This file contains the type definitions and global functions of the DT.
19 *
20 * The DT models the chip as a collection of instances. Each instance has
21 * a type (the IP block) and a number of attributes such as I/Os, IRQs
22 * and so on. The DT also provides top-specific lists of global resources
23 * such as I/O pads, clocks and interrupts.
24 */
25
26#include <stddef.h>
27#include <stdint.h>
29
30/**
31 * List of device types.
32 *
33 * Device types are guaranteed to be numbered consecutively from 0.
34 */
35typedef enum dt_device_type {
36 kDtDeviceTypeUnknown = 0, /**< Instance of unknown type */
37 kDtDeviceTypeAcRangeCheck = 1, /**< instance of ac_range_check */
38 kDtDeviceTypeAes = 2, /**< instance of aes */
39 kDtDeviceTypeAlertHandler = 3, /**< instance of alert_handler */
40 kDtDeviceTypeAonTimer = 4, /**< instance of aon_timer */
41 kDtDeviceTypeAst = 5, /**< instance of ast */
42 kDtDeviceTypeClkmgr = 6, /**< instance of clkmgr */
43 kDtDeviceTypeCsrng = 7, /**< instance of csrng */
44 kDtDeviceTypeDma = 8, /**< instance of dma */
45 kDtDeviceTypeEdn = 9, /**< instance of edn */
46 kDtDeviceTypeEntropySrc = 10, /**< instance of entropy_src */
47 kDtDeviceTypeGpio = 11, /**< instance of gpio */
48 kDtDeviceTypeHmac = 12, /**< instance of hmac */
49 kDtDeviceTypeI2c = 13, /**< instance of i2c */
50 kDtDeviceTypeKeymgrDpe = 14, /**< instance of keymgr_dpe */
51 kDtDeviceTypeKmac = 15, /**< instance of kmac */
52 kDtDeviceTypeLcCtrl = 16, /**< instance of lc_ctrl */
53 kDtDeviceTypeMbx = 17, /**< instance of mbx */
54 kDtDeviceTypeOtbn = 18, /**< instance of otbn */
55 kDtDeviceTypeOtpCtrl = 19, /**< instance of otp_ctrl */
56 kDtDeviceTypeOtpMacro = 20, /**< instance of otp_macro */
57 kDtDeviceTypePinmux = 21, /**< instance of pinmux */
58 kDtDeviceTypePwrmgr = 22, /**< instance of pwrmgr */
59 kDtDeviceTypeRaclCtrl = 23, /**< instance of racl_ctrl */
60 kDtDeviceTypeRomCtrl = 24, /**< instance of rom_ctrl */
61 kDtDeviceTypeRstmgr = 25, /**< instance of rstmgr */
62 kDtDeviceTypeRvCoreIbex = 26, /**< instance of rv_core_ibex */
63 kDtDeviceTypeRvDm = 27, /**< instance of rv_dm */
64 kDtDeviceTypeRvPlic = 28, /**< instance of rv_plic */
65 kDtDeviceTypeRvTimer = 29, /**< instance of rv_timer */
66 kDtDeviceTypeSocDbgCtrl = 30, /**< instance of soc_dbg_ctrl */
67 kDtDeviceTypeSocProxy = 31, /**< instance of soc_proxy */
68 kDtDeviceTypeSpiDevice = 32, /**< instance of spi_device */
69 kDtDeviceTypeSpiHost = 33, /**< instance of spi_host */
70 kDtDeviceTypeSramCtrl = 34, /**< instance of sram_ctrl */
71 kDtDeviceTypeUart = 35, /**< instance of uart */
72 kDtDeviceTypeCount = 36, /**< \internal Number of instance types */
74
75/**
76 * List of instance IDs.
77 *
78 * Instance IDs are guaranteed to be numbered consecutively from 0.
79 */
80typedef enum dt_instance_id {
81 kDtInstanceIdUnknown = 0, /**< Unknown instance */
82 kDtInstanceIdAcRangeCheck = 1, /**< instance ac_range_check of ac_range_check */
83 kDtInstanceIdAes = 2, /**< instance aes of aes */
84 kDtInstanceIdAlertHandler = 3, /**< instance alert_handler of alert_handler */
85 kDtInstanceIdAonTimerAon = 4, /**< instance aon_timer_aon of aon_timer */
86 kDtInstanceIdAst = 5, /**< instance ast of ast */
87 kDtInstanceIdClkmgrAon = 6, /**< instance clkmgr_aon of clkmgr */
88 kDtInstanceIdCsrng = 7, /**< instance csrng of csrng */
89 kDtInstanceIdDma = 8, /**< instance dma of dma */
90 kDtInstanceIdEdn0 = 9, /**< instance edn0 of edn */
91 kDtInstanceIdEdn1 = 10, /**< instance edn1 of edn */
92 kDtInstanceIdEntropySrc = 11, /**< instance entropy_src of entropy_src */
93 kDtInstanceIdGpio = 12, /**< instance gpio of gpio */
94 kDtInstanceIdHmac = 13, /**< instance hmac of hmac */
95 kDtInstanceIdI2c0 = 14, /**< instance i2c0 of i2c */
96 kDtInstanceIdKeymgrDpe = 15, /**< instance keymgr_dpe of keymgr_dpe */
97 kDtInstanceIdKmac = 16, /**< instance kmac of kmac */
98 kDtInstanceIdLcCtrl = 17, /**< instance lc_ctrl of lc_ctrl */
99 kDtInstanceIdMbx0 = 18, /**< instance mbx0 of mbx */
100 kDtInstanceIdMbx1 = 19, /**< instance mbx1 of mbx */
101 kDtInstanceIdMbx2 = 20, /**< instance mbx2 of mbx */
102 kDtInstanceIdMbx3 = 21, /**< instance mbx3 of mbx */
103 kDtInstanceIdMbx4 = 22, /**< instance mbx4 of mbx */
104 kDtInstanceIdMbx5 = 23, /**< instance mbx5 of mbx */
105 kDtInstanceIdMbx6 = 24, /**< instance mbx6 of mbx */
106 kDtInstanceIdMbxJtag = 25, /**< instance mbx_jtag of mbx */
107 kDtInstanceIdMbxPcie0 = 26, /**< instance mbx_pcie0 of mbx */
108 kDtInstanceIdMbxPcie1 = 27, /**< instance mbx_pcie1 of mbx */
109 kDtInstanceIdOtbn = 28, /**< instance otbn of otbn */
110 kDtInstanceIdOtpCtrl = 29, /**< instance otp_ctrl of otp_ctrl */
111 kDtInstanceIdOtpMacro = 30, /**< instance otp_macro of otp_macro */
112 kDtInstanceIdPinmuxAon = 31, /**< instance pinmux_aon of pinmux */
113 kDtInstanceIdPwrmgrAon = 32, /**< instance pwrmgr_aon of pwrmgr */
114 kDtInstanceIdRaclCtrl = 33, /**< instance racl_ctrl of racl_ctrl */
115 kDtInstanceIdRomCtrl0 = 34, /**< instance rom_ctrl0 of rom_ctrl */
116 kDtInstanceIdRomCtrl1 = 35, /**< instance rom_ctrl1 of rom_ctrl */
117 kDtInstanceIdRstmgrAon = 36, /**< instance rstmgr_aon of rstmgr */
118 kDtInstanceIdRvCoreIbex = 37, /**< instance rv_core_ibex of rv_core_ibex */
119 kDtInstanceIdRvDm = 38, /**< instance rv_dm of rv_dm */
120 kDtInstanceIdRvPlic = 39, /**< instance rv_plic of rv_plic */
121 kDtInstanceIdRvTimer = 40, /**< instance rv_timer of rv_timer */
122 kDtInstanceIdSocDbgCtrl = 41, /**< instance soc_dbg_ctrl of soc_dbg_ctrl */
123 kDtInstanceIdSocProxy = 42, /**< instance soc_proxy of soc_proxy */
124 kDtInstanceIdSpiDevice = 43, /**< instance spi_device of spi_device */
125 kDtInstanceIdSpiHost0 = 44, /**< instance spi_host0 of spi_host */
126 kDtInstanceIdSramCtrlRetAon = 45, /**< instance sram_ctrl_ret_aon of sram_ctrl */
127 kDtInstanceIdSramCtrlMain = 46, /**< instance sram_ctrl_main of sram_ctrl */
128 kDtInstanceIdSramCtrlMbox = 47, /**< instance sram_ctrl_mbox of sram_ctrl */
129 kDtInstanceIdUart0 = 48, /**< instance uart0 of uart */
130 kDtInstanceIdCount = 49, /**< \internal Number of instance IDs */
132
133/**
134 * Get the instance type of a device instance.
135 *
136 * For example the instance type of `kDtUart0` is `kDtInstanceTypeUart`.
137 *
138 * @param id An instance ID.
139 * @return The instance type, or `kDtInstanceIdUnknown` if the ID is not valid.
140 */
142
143/** PLIC IRQ ID type.
144 *
145 * This type represents a raw IRQ ID from the PLIC.
146 *
147 * This is an alias to the top's `plic_irq_id_t` type for backward compatibility
148 * with existing code.
149 */
151
152/** PLIC IRQ ID for no interrupt. */
153static const dt_plic_irq_id_t kDtPlicIrqIdNone = kTopDarjeelingPlicIrqIdNone;
154
155/**
156 * Get the instance ID for a given PLIC IRQ ID.
157 *
158 * For example, on earlgrey, the instance ID of `kTopEarlgreyPlicIrqIdUart0TxWatermark`
159 * is `kDtInstanceIdUart0`. One can then use the type specific function to retrieve the
160 * IRQ name, for example `dt_uart_irq_from_plic_id` for the UART.
161 *
162 * @param irq A PLIC ID.
163 * @return The instance ID, or `kDtInstanceIdUnknown` if the PLIC ID is not valid.
164 */
166
167/**
168 * Alert ID type.
169 *
170 * This type represents a raw alert ID from the Alert Handler.
171 *
172 * This is an alias to the top's `alert_id_t` type for backward compatibility
173 * with existing code.
174 */
176
177/** Number of alerts. */
178enum {
179 /** Total number of alert IDs. */
180 kDtAlertCount = kTopDarjeelingAlertIdLast + 1,
181};
182
183/**
184 * Get the instance ID for a given alert ID.
185 *
186 * For example, on earlgrey, the instance ID of `kTopEarlgreyAlertIdUart0FatalFault` is
187 * `kDtInstanceIdUart0`. One can then use the type specific function to retrieve the
188 * alert name, for example `dt_uart_alert_from_alert_id` for the UART.
189 *
190 * @param alert An alert ID.
191 * @return The instance ID, or `kDtInstanceIdUnknown` if the alert ID is not valid.
192 */
194
195/**
196 * List of clocks.
197 *
198 * Clocks are guaranteed to be numbered consecutively from 0.
199 */
200typedef enum dt_clock {
201 kDtClockMain = 0, /**< clock main */
202 kDtClockIo = 1, /**< clock io */
203 kDtClockAon = 2, /**< clock aon */
204 kDtClockIoDiv2 = 3, /**< clock io_div2 */
205 kDtClockIoDiv4 = 4, /**< clock io_div4 */
206 kDtClockCount = 5, /**< \internal Number of clocks */
208
209/**
210 * Get the frequency of a clock.
211 *
212 * @param clk A clock ID.
213 * @return Clock frequency in Hz.
214 */
216
217/**
218 * List of resets.
219 *
220 * Resets are guaranteed to be numbered consecutively from 0.
221 */
222typedef enum dt_reset {
223 kDtResetUnknown = 0, /**< Unknown reset */
224 kDtResetPorAon = 1, /**< Reset node por_aon */
225 kDtResetLcSrc = 2, /**< Reset node lc_src */
226 kDtResetSysSrc = 3, /**< Reset node sys_src */
227 kDtResetPor = 4, /**< Reset node por */
228 kDtResetPorIo = 5, /**< Reset node por_io */
229 kDtResetPorIoDiv2 = 6, /**< Reset node por_io_div2 */
230 kDtResetPorIoDiv4 = 7, /**< Reset node por_io_div4 */
231 kDtResetLc = 8, /**< Reset node lc */
232 kDtResetLcAon = 9, /**< Reset node lc_aon */
233 kDtResetLcIo = 10, /**< Reset node lc_io */
234 kDtResetLcIoDiv2 = 11, /**< Reset node lc_io_div2 */
235 kDtResetLcIoDiv4 = 12, /**< Reset node lc_io_div4 */
236 kDtResetSys = 13, /**< Reset node sys */
237 kDtResetSysIoDiv4 = 14, /**< Reset node sys_io_div4 */
238 kDtResetSpiDevice = 15, /**< Reset node spi_device */
239 kDtResetSpiHost0 = 16, /**< Reset node spi_host0 */
240 kDtResetI2c0 = 17, /**< Reset node i2c0 */
241 kDtResetCount = 18, /**< \internal Number of resets */
243
244/**
245 * List of pads names.
246 */
247typedef enum dt_pad {
248 kDtPadMio0 = 0, /**< Muxed IO pad */
249 kDtPadMio1 = 1, /**< Muxed IO pad */
250 kDtPadMio2 = 2, /**< Muxed IO pad */
251 kDtPadMio3 = 3, /**< Muxed IO pad */
252 kDtPadMio4 = 4, /**< Muxed IO pad */
253 kDtPadMio5 = 5, /**< Muxed IO pad */
254 kDtPadMio6 = 6, /**< Muxed IO pad */
255 kDtPadMio7 = 7, /**< Muxed IO pad */
256 kDtPadMio8 = 8, /**< Muxed IO pad */
257 kDtPadMio9 = 9, /**< Muxed IO pad */
258 kDtPadMio10 = 10, /**< Muxed IO pad */
259 kDtPadMio11 = 11, /**< Muxed IO pad */
260 kDtPadSpiHost0Sd0 = 12, /**< SPI host data */
261 kDtPadSpiHost0Sd1 = 13, /**< SPI host data */
262 kDtPadSpiHost0Sd2 = 14, /**< SPI host data */
263 kDtPadSpiHost0Sd3 = 15, /**< SPI host data */
264 kDtPadSpiDeviceSd0 = 16, /**< SPI device data */
265 kDtPadSpiDeviceSd1 = 17, /**< SPI device data */
266 kDtPadSpiDeviceSd2 = 18, /**< SPI device data */
267 kDtPadSpiDeviceSd3 = 19, /**< SPI device data */
268 kDtPadI2c0Scl = 20, /**< I2C clock */
269 kDtPadI2c0Sda = 21, /**< I2C data */
270 kDtPadGpioGpio0 = 22, /**< GPIO pad */
271 kDtPadGpioGpio1 = 23, /**< GPIO pad */
272 kDtPadGpioGpio2 = 24, /**< GPIO pad */
273 kDtPadGpioGpio3 = 25, /**< GPIO pad */
274 kDtPadGpioGpio4 = 26, /**< GPIO pad */
275 kDtPadGpioGpio5 = 27, /**< GPIO pad */
276 kDtPadGpioGpio6 = 28, /**< GPIO pad */
277 kDtPadGpioGpio7 = 29, /**< GPIO pad */
278 kDtPadGpioGpio8 = 30, /**< GPIO pad */
279 kDtPadGpioGpio9 = 31, /**< GPIO pad */
280 kDtPadGpioGpio10 = 32, /**< GPIO pad */
281 kDtPadGpioGpio11 = 33, /**< GPIO pad */
282 kDtPadGpioGpio12 = 34, /**< GPIO pad */
283 kDtPadGpioGpio13 = 35, /**< GPIO pad */
284 kDtPadGpioGpio14 = 36, /**< GPIO pad */
285 kDtPadGpioGpio15 = 37, /**< GPIO pad */
286 kDtPadGpioGpio16 = 38, /**< GPIO pad */
287 kDtPadGpioGpio17 = 39, /**< GPIO pad */
288 kDtPadGpioGpio18 = 40, /**< GPIO pad */
289 kDtPadGpioGpio19 = 41, /**< GPIO pad */
290 kDtPadGpioGpio20 = 42, /**< GPIO pad */
291 kDtPadGpioGpio21 = 43, /**< GPIO pad */
292 kDtPadGpioGpio22 = 44, /**< GPIO pad */
293 kDtPadGpioGpio23 = 45, /**< GPIO pad */
294 kDtPadGpioGpio24 = 46, /**< GPIO pad */
295 kDtPadGpioGpio25 = 47, /**< GPIO pad */
296 kDtPadGpioGpio26 = 48, /**< GPIO pad */
297 kDtPadGpioGpio27 = 49, /**< GPIO pad */
298 kDtPadGpioGpio28 = 50, /**< GPIO pad */
299 kDtPadGpioGpio29 = 51, /**< GPIO pad */
300 kDtPadGpioGpio30 = 52, /**< GPIO pad */
301 kDtPadGpioGpio31 = 53, /**< GPIO pad */
302 kDtPadSpiDeviceSck = 54, /**< SPI device clock */
303 kDtPadSpiDeviceCsb = 55, /**< SPI device chip select */
304 kDtPadSpiDeviceTpmCsb = 56, /**< SPI device TPM chip select */
305 kDtPadUart0Rx = 57, /**< UART receive */
306 kDtPadSocProxySocGpi0 = 58, /**< SoC general purpose input */
307 kDtPadSocProxySocGpi1 = 59, /**< SoC general purpose input */
308 kDtPadSocProxySocGpi2 = 60, /**< SoC general purpose input */
309 kDtPadSocProxySocGpi3 = 61, /**< SoC general purpose input */
310 kDtPadSocProxySocGpi4 = 62, /**< SoC general purpose input */
311 kDtPadSocProxySocGpi5 = 63, /**< SoC general purpose input */
312 kDtPadSocProxySocGpi6 = 64, /**< SoC general purpose input */
313 kDtPadSocProxySocGpi7 = 65, /**< SoC general purpose input */
314 kDtPadSocProxySocGpi8 = 66, /**< SoC general purpose input */
315 kDtPadSocProxySocGpi9 = 67, /**< SoC general purpose input */
316 kDtPadSocProxySocGpi10 = 68, /**< SoC general purpose input */
317 kDtPadSocProxySocGpi11 = 69, /**< SoC general purpose input */
318 kDtPadSpiHost0Sck = 70, /**< SPI host clock */
319 kDtPadSpiHost0Csb = 71, /**< SPI host chip select */
320 kDtPadUart0Tx = 72, /**< UART transmit */
321 kDtPadSocProxySocGpo0 = 73, /**< SoC general purpose output */
322 kDtPadSocProxySocGpo1 = 74, /**< SoC general purpose output */
323 kDtPadSocProxySocGpo2 = 75, /**< SoC general purpose output */
324 kDtPadSocProxySocGpo3 = 76, /**< SoC general purpose output */
325 kDtPadSocProxySocGpo4 = 77, /**< SoC general purpose output */
326 kDtPadSocProxySocGpo5 = 78, /**< SoC general purpose output */
327 kDtPadSocProxySocGpo6 = 79, /**< SoC general purpose output */
328 kDtPadSocProxySocGpo7 = 80, /**< SoC general purpose output */
329 kDtPadSocProxySocGpo8 = 81, /**< SoC general purpose output */
330 kDtPadSocProxySocGpo9 = 82, /**< SoC general purpose output */
331 kDtPadSocProxySocGpo10 = 83, /**< SoC general purpose output */
332 kDtPadSocProxySocGpo11 = 84, /**< SoC general purpose output */
333 kDtPadCount = 85, /**< \internal Number of pads */
335
336/** Type of peripheral I/O. */
337typedef enum dt_periph_io_type {
338 /** This peripheral I/O is connected to a muxed IO (MIO). */
340 /** This peripheral I/O is connected to a direct IO (DIO). */
342 /** This peripheral I/O is not connected to either a MIO or a DIO. */
345
346
347/** Direction of a peripheral I/O. */
348typedef enum dt_periph_io_dir {
349 /** This peripheral I/O is an input. */
351 /** This peripheral I/O is an output */
353 /** This peripheral I/O is an input-output */
356
357/** Peripheral I/O description.
358 *
359 * A `dt_periph_io_t` represents a HW IP block peripheral I/O, which can be an input, output or both.
360 * Importantly, this only represents how the block peripheral I/O is wired, i.e.
361 * whether it is connected a MIO or a direct IO on the pinmux, and the relevant information necessary to
362 * configure it.
363 *
364 * **Note:** The fields of this structure are internal, use the dt_periph_io_* functions to access them.
365 */
366typedef struct dt_periph_io {
367 struct {
368 dt_periph_io_type_t type; /**< Peripheral I/O type */
369 dt_periph_io_dir_t dir; /**< Peripheral I/O direction */
370 /**
371 * For `kDtPeriphIoTypeMio`: peripheral input number. This is the index of the MIO_PERIPH_INSEL register
372 * that controls this peripheral I/O.
373 *
374 * For `kDtPeriphIoTypeDio`: DIO pad number. This is the index of the various DIO_PAD_* registers
375 * that control this peripheral I/O.
376 */
377 uint16_t periph_input_or_direct_pad;
378 /**
379 * For `kDtPeriphIoTypeMio`: peripheral output number. This is the value to put in the MIO_OUTSEL registers
380 * to connect an output to this peripheral I/O. For `kDtPeriphIoTypeDio`: the pad index (`dt_pad_t`) to which this I/O is connected.
381 */
382 uint16_t outsel_or_dt_pad;
383 } __internal; /**< Private fields */
385
386
387/* Peripheral I/O that is constantly tied to high-Z (output only) */
388extern const dt_periph_io_t kDtPeriphIoConstantHighZ;
389
390/* Peripheral I/O that is constantly tied to one (output only) */
391extern const dt_periph_io_t kDtPeriphIoConstantZero;
392
393/* Peripheral I/O that is constantly tied to zero (output only) */
394extern const dt_periph_io_t kDtPeriphIoConstantOne;
395
396/**
397 * Return the type of a `dt_periph_io_t`.
398 *
399 * @param periph_io A peripheral I/O description.
400 * @return The peripheral I/O type (MIO, DIO, etc).
401 */
403 return periph_io.__internal.type;
404}
405
406/**
407 * Return the direction of a `dt_periph_io_t`.
408 *
409 * @param periph_io A peripheral I/O description.
410 * @return The peripheral I/O direction.
411 */
412static inline dt_periph_io_dir_t dt_periph_io_dir(dt_periph_io_t periph_io) {
413 return periph_io.__internal.dir;
414}
415
416/**
417 * Pinmux types.
418 *
419 * These types are aliases to top-level types for backward compatibility
420 * with existing code.
421 */
423typedef top_darjeeling_pinmux_insel_t dt_pinmux_insel_t;
424typedef top_darjeeling_pinmux_outsel_t dt_pinmux_outsel_t;
425typedef top_darjeeling_pinmux_mio_out_t dt_pinmux_mio_out_t;
426typedef top_darjeeling_direct_pads_t dt_pinmux_direct_pad_t;
427typedef top_darjeeling_muxed_pads_t dt_pinmux_muxed_pad_t;
428
429/** Tie constantly to zero. */
430static const dt_pinmux_outsel_t kDtPinmuxOutselConstantZero = kTopDarjeelingPinmuxOutselConstantZero;
431
432/** Tie constantly to one. */
433static const dt_pinmux_outsel_t kDtPinmuxOutselConstantOne = kTopDarjeelingPinmuxOutselConstantOne;
434
435/** Tie constantly to high-Z. */
436static const dt_pinmux_outsel_t kDtPinmuxOutselConstantHighZ = kTopDarjeelingPinmuxOutselConstantHighZ;
437
438/**
439 * Return the peripheral input for an MIO peripheral I/O.
440 *
441 * This is the index of the `MIO_PERIPH_INSEL` pinmux register that controls this peripheral I/O.
442 *
443 * @param periph_io A peripheral I/O of type `kDtPeriphIoTypeMio`.
444 * @return The peripheral input number of the MIO that this peripheral I/O is connected to.
445 *
446 * **Note:** This function only makes sense for peripheral I/Os of type `kDtPeriphIoTypeMio` which are
447 * inputs (`kDtPeriphIoDirIn`). For any other peripheral I/O, the return value is unspecified.
448 */
449static inline dt_pinmux_peripheral_in_t dt_periph_io_mio_periph_input(dt_periph_io_t periph_io) {
450 return (dt_pinmux_peripheral_in_t)periph_io.__internal.periph_input_or_direct_pad;
451}
452
453/**
454 * Return the outsel for an MIO peripheral I/O.
455 *
456 * This is the value to put in the `MIO_OUTSEL` pinmux registers to connect a pad to this peripheral I/O.
457 *
458 * @param periph_io A peripheral I/O of type `kDtPeriphIoTypeMio`.
459 * @return The outsel of the MIO that this peripheral I/O is connected to.
460 *
461 * **Note:** This function only makes sense for peripheral I/Os of type `kDtPeriphIoTypeMio` which are
462 * outputs (`kDtPeriphIoDirOut`). For any other peripheral I/O, the return value is unspecified.
463 */
464static inline dt_pinmux_outsel_t dt_periph_io_mio_outsel(dt_periph_io_t periph_io) {
465 return (dt_pinmux_outsel_t)periph_io.__internal.outsel_or_dt_pad;
466}
467
468/**
469 * Return the direct pad number of a DIO peripheral I/O.
470 *
471 * This is the index of the various `DIO_PAD_*` pinmux registers that control this peripheral I/O.
472 *
473 * @param periph_io A peripheral I/O of type `kDtPeriphIoTypeDio`.
474 * @return The direct pad number of the DIO that this peripheral I/O is connected to.
475 *
476 * **Note:** This function only makes sense for peripheral I/Os of type `kDtPeriphIoTypeDio` which are
477 * either outputs or inouts. For any other peripheral I/O type, the return value is unspecified.
478 */
479static inline dt_pinmux_direct_pad_t dt_periph_io_dio_pad_index(dt_periph_io_t periph_io) {
480 return (dt_pinmux_direct_pad_t)periph_io.__internal.periph_input_or_direct_pad;
481}
482
483/**
484 * Return the pad of a DIO peripheral I/O.
485 *
486 * @param periph_io A peripheral I/O of type `kDtPeriphIoTypeDio`.
487 * @return The pad to which this peripheral I/O is connected to.
488 *
489 * **Note:** This function only makes sense for peripheral I/Os of type `kDtPeriphIoTypeDio` which are
490 * either outputs or inouts. For any other peripheral I/O type, the return value is unspecified.
491 */
492static inline dt_pad_t dt_periph_io_dio_pad(dt_periph_io_t periph_io) {
493 return (dt_pad_t)periph_io.__internal.outsel_or_dt_pad;
494}
495
496/** Type of a pad. */
497typedef enum dt_pad_type {
498 /** This pad is a muxed IO (MIO). */
500 /** This pad is a direct IO (DIO). */
502 /** This pad is not an MIO or a DIO. */
505
506/**
507 * Return the type of a `dt_pad_t`.
508 *
509 * @param pad A pad description.
510 * @return The pad type (MIO, DIO, etc).
511 */
513
514/**
515 * Return the pad out number for an MIO pad.
516 *
517 * This is the index of the `MIO_OUT` registers that control this pad
518 * (or the output part of this pad).
519 *
520 * @param pad A pad of type `kDtPadTypeMio`.
521 * @return The pad out number of the MIO.
522 *
523 * **Note:** This function only makes sense for pads of type `kDtPadTypeMio` which are
524 * either inputs or inouts. For any other pad, the return value is unspecified.
525 */
526dt_pinmux_mio_out_t dt_pad_mio_out(dt_pad_t pad);
527
528/**
529 * Return the pad out number for an MIO pad.
530 *
531 * This is the index of the `MIO_PAD` registers that control this pad
532 * (or the output part of this pad).
533 *
534 * @param pad A pad of type `kDtPadTypeMio`.
535 * @return The pad out number of the MIO.
536 *
537 * **Note:** This function only makes sense for pads of type `kDtPadTypeMio`.
538 * For any other pad, the return value is unspecified.
539 */
540dt_pinmux_muxed_pad_t dt_pad_mio_pad_index(dt_pad_t pad);
541
542/**
543 * Return the insel for an MIO pad.
544 *
545 * This is the value to put in the `MIO_PERIPH_INSEL` registers to connect a peripheral I/O to this pad.
546 *
547 * @param pad A pad of type `kDtPadTypeMio`.
548 * @return The insel of the MIO that this pad is connected to.
549 *
550 * **Note:** This function only makes sense for pads of type `kDtPadTypeMio`.
551 * For any other pad, the return value is unspecified.
552 */
553dt_pinmux_insel_t dt_pad_mio_insel(dt_pad_t pad);
554
555/**
556 * Return the direct pad number of a DIO pad.
557 *
558 * This is the index of the various `DIO_PAD_*` registers that control this pad.
559 *
560 * @param pad A pad of type `kDtPadTypeDio`.
561 * @return The direct pad number of the DID that this pad is connected to.
562 *
563 * **Note:** This function only makes sense for pads of type `kDtPeriphIoTypeDio` which are
564 * either outputs or inouts. For any other pad type, the return value is unspecified.
565 */
566dt_pinmux_direct_pad_t dt_pad_dio_pad_index(dt_pad_t pad);
567
568#ifdef __cplusplus
569} // extern "C"
570#endif // __cplusplus
571
572#endif // OPENTITAN_TOP_DARJEELING_DT_API_H_