Datasheets

OpenTitan Subsystems

The OpenTitan Earl Grey chip is a low-power secure microcontroller that is designed for several use cases requiring hardware security.

OpenTitan Earl Grey (Standalone Chip)

📋 Datasheet

High speed domain

DUAL LOCKSTEP Ibex Core (RV32IMCB) Interrupt Controller ROM Debug Module Main
SRAM TL-UL
Crossbar Key Manager KMAC EDN SPI
Host 0 OTBN HMAC CSRNG SPI
Host 1 AES Flash Entropy Source USB

Peripheral domain

TL-UL Crossbar OTP (Fuse) Controller Life
Cycle Alert Handler 4 x UART Timers GPIO 3 x I²C SPI
Device Pattern Generators

Always-on domain

PWM Retention SRAM Power Manager Sysrst Controller AON
Timers Clk/Rst Managers Pinmux / Padctrl ADC Controller Sensor Control

Padring (only wire and pad instances) Analog Sensor Top

~100 MHz

96 MHz

48 MHz

24 MHz

200 kHz

Logic Only

OpenTitan Darjeeling is a system-on-a-chip Secure Execution Environment, capable of serving as a root of trust (RoT) for measurement and attestation among other applications, for instantiation within a larger system.

Darjeeling Block Diagram — **OpenTitan Darjeeling (Integrated Admissible Architecture)**