This document specifies Ibex CPU core wrapper functionality.
- Instantiation of a Ibex RV32 CPU Core.
- TileLink Uncached Light (TL-UL) host interfaces for the instruction and data ports.
- Simple address translation.
- NMI support for security alert events for watchdog bark.
- General error status collection and alert generation.
- Crash dump collection for software debug.
The Ibex RISC-V Core Wrapper instantiates an Ibex RV32 CPU Core, and wraps its data and instruction memory interfaces to TileLink Uncached Light (TL-UL). All configuration parameters of Ibex are passed through. The pipelining of the bus adapters is configurable.
Ibex is a compliant RV32 RISC-V CPU core, as documented in the Ibex documentation.
The TL-UL bus interfaces exposed by this wrapper block are compliant to the TileLink Uncached Lite Specification version 1.7.1.