Registers

Summary

INTR_STATE

Interrupt State Register

• Offset: 0x0
• Reset default: 0x0
• Reset mask: 0x3

Fields

{"reg": [{"name": "hci", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "targ", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

INTR_ENABLE

Interrupt Enable Register

• Offset: 0x4
• Reset default: 0x0
• Reset mask: 0x3

Fields

{"reg": [{"name": "hci", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "targ", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

INTR_TEST

Interrupt Test Register

• Offset: 0x8
• Reset default: 0x0
• Reset mask: 0x3

Fields

{"reg": [{"name": "hci", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "targ", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ALERT_TEST

Alert Test Register

• Offset: 0xc
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

INFO

IP block information, allowing software to adapt dynamically.

• Offset: 0x10
• Reset default: 0xfffff10
• Reset mask: 0x1fffffff

Fields

{"reg": [{"name": "REVISION", "bits": 4, "attr": ["ro"], "rotate": -90}, {"name": "VERSION", "bits": 4, "attr": ["ro"], "rotate": -90}, {"name": "DAT_ENTRY_MAX", "bits": 5, "attr": ["ro"], "rotate": -90}, {"name": "DCT_ENTRY_MAX", "bits": 5, "attr": ["ro"], "rotate": -90}, {"name": "BUF_DWORD_MAX", "bits": 11, "attr": ["ro"], "rotate": 0}, {"bits": 3}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}

CTRL_STATUS

Controller-side Status register.

• Offset: 0x14
• Reset default: 0x80000000
• Reset mask: 0x80000000

Fields

{"reg": [{"bits": 31}, {"name": "PRESENT", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}

CTRL_ERROR

Controller Error counts.

• Offset: 0x18
• Reset default: 0x0
• Reset mask: 0xffff

Fields

{"reg": [{"name": "CE0", "bits": 4, "attr": ["rw1c"], "rotate": 0}, {"name": "CE1", "bits": 4, "attr": ["rw1c"], "rotate": 0}, {"name": "CE2", "bits": 4, "attr": ["rw1c"], "rotate": 0}, {"name": "CE3", "bits": 4, "attr": ["rw1c"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TARG_CONTROL

Target Control register.

• Offset: 0x1c
• Reset default: 0x2
• Reset mask: 0xc000001f

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "STBY_CR_SUPPORT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CRHDLY1_AS", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "CRHDLY1_SET_AS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 25}, {"name": "HJ_REQUEST", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RESET", "bits": 1, "attr": ["wo"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}}

TARG_CONTROL . RESET

Software reset of Target logic.

Iff the Standby Controller support is disabled by clearing STBY_CR_SUPPORT, writing ‘1’ to this field will reset all of the Target-side logic. To reset the Target-side logic when Standby Controller support is enabled, software shall instead use the SOFT_RST field of the HCI-specified RESET_CONTROL register, whether or not the Controller is currently the Active Controller.

TARG_CONTROL . HJ_REQUEST

Issue Hot-Join request.

This applies to all Virtual Targets since they share a single physical Target. Software shall set this to ‘1’ to issue the request, and the hardware will clear it when the request has been sent and acknowledged.

TARG_CONTROL . CRHDLY1_SET_AS

Set Bus Activity State. This information is returned in response to the CRHDLY form of the GETMXDS CCC.

TARG_CONTROL . CRHDLY1_AS

Controller Handoff Activity State. This information is returned in response to the CRHDLY form of the GETMXDS CCC.

TARG_CONTROL . STBY_CR_SUPPORT

Standby Controller role supported.

When set the Controller shall have the option of performing Controller Role Handoff and switching into Standby Controller mode. If this field is clear the Controller will refuse to hand off the bus when requested and will instead remain the Active Controller, thus freeing up the first Virtual Target to operate independently as a dedicated Target device.

TARG_CONTROL . EN

Target enable.

Enable the Target-side logic as a separate I3C device, instead of supporting Standby Controller mode. In this configuration the Controller-side logic must remain the Active Controller and cannot perform Controller Role Handoff.

TARG_STATUS

Target-side Status register

• Offset: 0x20
• Reset default: 0x80000000
• Reset mask: 0xc7ffffff

Fields

{"reg": [{"name": "EXT_INFO", "bits": 15, "attr": ["rw"], "rotate": 0}, {"name": "EXT_PRESENT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RSTACT", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "RSTACT_VIRT_TARG_DET", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "VTM", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "PROTOCOL_ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 3}, {"name": "ACTIVE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "PRESENT", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

TARG_SINK_CONTROL

Target data sink control.

• Offset: 0x24
• Reset default: 0x0
• Reset mask: 0x87ff7000

Fields

{"reg": [{"bits": 12}, {"name": "BUFFER", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 1}, {"name": "LENGTH", "bits": 11, "attr": ["rw"], "rotate": 0}, {"bits": 4}, {"name": "START", "bits": 1, "attr": ["wo"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TARG_SINK_CONTROL . START

Initiate removal of DWORDs from a transmission buffer.

The ‘data sink’ logic is a mechanism for recovering from aborting or failed transmissions without impacting subsequent, already-queued transfers. Software shall write ‘1’ to this field to start the ‘data sink’ logic. The ACTIVE field in the corresponding TARG_SINK_STATUS register shows whether the logic is still active.

TARG_SINK_CONTROL . LENGTH

Specifies the number of DWORDs to be removed, minus 1.

This field instructs the ‘data sink’ logic to remove a specified number of DWORDs of data from the specified source. Software shall program ‘n-1’ into this field to remove ‘n’ DWORDs.

TARG_SINK_CONTROL . BUFFER

Specifies the transmission buffer from which DWORDs are to be removed.

0 - IBI Data buffer. 1 - Virtual Target 0 Tx buffer 2 - Virtual Target 1 Tx buffer…

TARG_SINK_STATUS

Target data sink status.

• Offset: 0x28
• Reset default: 0x0
• Reset mask: 0x7ff0003

Fields

{"reg": [{"name": "ACTIVE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ERROR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 14}, {"name": "LENGTH", "bits": 11, "attr": ["ro"], "rotate": 0}, {"bits": 5}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TARG_SINK_STATUS . LENGTH

Reports the numbers of DWORDs still to be removed when ERROR is asserted.

In the event of an error, this value may be used to ascertain how much of the operation was performed. When this field reports ‘m’, there are still ‘m+1’ DWORDs to be removed. In the event of successful completion (‘ACTIVE’ and ‘ERROR’ both reset) this field is not meaningful and the DWORDs were removed as expected.

TARG_SINK_STATUS . ERROR

Indicates whether the data sink mechanism stopped prematurely. If the specified buffer did not contain sufficient data for the logic to remove the specified number of DWORDs it will set this bit when becoming inactive.

TARG_SINK_STATUS . ACTIVE

Indicates whether the data sink logic is active. This bit becomes set when the operation is started and will be cleared at most a few tens of microseconds later when the operation is complete.

RESET_DET_CTRL

Reset detector control.

• Offset: 0x2c
• Reset default: 0x0
• Reset mask: 0x310002

Fields

{"reg": [{"bits": 1}, {"name": "SLEEP_REQ", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 14}, {"name": "WAKE_ACK", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 3}, {"name": "RST_PERIPH_EN", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RST_TARGET_EN", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 10}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}

RESET_DET_STATUS

Reset detector status.

• Offset: 0x30
• Reset default: 0x0
• Reset mask: 0xf

Fields

{"reg": [{"name": "ACTIVE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "WAKE_UP", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RST_PERIPH", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RST_TARGET", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}

CTRL_TIME_SP

Controller Timing Parameters for Start and stoP.

This register shall be modified only when the Controller is not connected to the I3C bus.

• Offset: 0x34
• Reset default: 0x3ff03ff
• Reset mask: 0x3ff03ff

Fields

{"reg": [{"name": "TCBP_DIV2", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}, {"name": "TCAS_DIV2", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CTRL_TIME_OD

Controller Timing Parameters for Open Drain signaling.

This register shall be modified only when the Controller is not connected to the I3C bus.

• Offset: 0x38
• Reset default: 0x3ff03ff
• Reset mask: 0x3ff03ff

Fields

{"reg": [{"name": "SCLLO_DIV2", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}, {"name": "SCLHI_DIV2", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CTRL_TIME_PP

Controller Timing Parameters for SDR0/HDR-DDR Push-Pull SCL High signaling.

This register shall be modified only when the Controller is not connected to the I3C bus.

• Offset: 0x3c
• Reset default: 0x3ff83ff
• Reset mask: 0x3ff83ff

Fields

{"reg": [{"name": "TCHH", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 5}, {"name": "HCEXT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "TCHS", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CTRL_TIME_PP . TCHS

Half of the SCL high interval during Push-Pull signaling, minus 1. This interval is in terms of the IP clock period. If this field has all bits set then the hardware will calculate a suitable value.

CTRL_TIME_PP . HCEXT

Enable half-cycle SCL extension. If the field PP_SCLHI_DIV2 has been set to something other than 0x3ff, this bit controls whether the half-cycle SCL extension is enabled. If PP_SCLHI_DIV2 has all bits set then the hardware will determine this setting automatically. Extending SCL by half a cycle of the IP clock enables support for other clock frequencies such as 96MHz.

CTRL_TIME_PP . TCHH

Half of the SCL low interval during Push-Pull signaling at SDR0 rate, minus 1. This interval is in terms of the IP clock period. If this field has all bits set then the hardware will calculate a suitable value.

CTRL_TIME_SDR0

Controller Timing Parameters for SDR0/HDR-DDR Push-Pull SCL Low signaling.

This register shall be modified only when the Controller is not connected to the I3C bus.

• Offset: 0x40
• Reset default: 0x3ff03ff
• Reset mask: 0x3ff03ff

Fields

{"reg": [{"name": "TCLH", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}, {"name": "TCLS", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CTRL_TIME_SDR1

Controller Timing Parameters for SDR1 Push-Pull SCL Low signaling.

This register shall be modified only when the Controller is not connected to the I3C bus.

• Offset: 0x44
• Reset default: 0x3ff03ff
• Reset mask: 0x3ff03ff

Fields

{"reg": [{"name": "TCLH", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}, {"name": "TCLS", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CTRL_TIME_SDR2

Controller Timing Parameters for SDR2 Push-Pull SCL Low signaling.

This register shall be modified only when the Controller is not connected to the I3C bus.

• Offset: 0x48
• Reset default: 0x3ff03ff
• Reset mask: 0x3ff03ff

Fields

{"reg": [{"name": "TCLH", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}, {"name": "TCLS", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CTRL_TIME_SDR3

Controller Timing Parameters for SDR3 Push-Pull SCL Low signaling.

This register shall be modified only when the Controller is not connected to the I3C bus.

• Offset: 0x4c
• Reset default: 0x3ff03ff
• Reset mask: 0x3ff03ff

Fields

{"reg": [{"name": "TCLH", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}, {"name": "TCLS", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CTRL_TIME_SDR4

Controller Timing Parameters for SDR4 Push-Pull SCL Low signaling.

This register shall be modified only when the Controller is not connected to the I3C bus.

• Offset: 0x50
• Reset default: 0x3ff03ff
• Reset mask: 0x3ff03ff

Fields

{"reg": [{"name": "TCLH", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}, {"name": "TCLS", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CTRL_TIME_FMP

Controller Timing Parameters for I2C Fast Mode Plus signaling.

This register shall be modified only when the Controller is not connected to the I3C bus.

• Offset: 0x54
• Reset default: 0x3ff03ff
• Reset mask: 0x3ff03ff

Fields

{"reg": [{"name": "SCLLO_DIV2", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}, {"name": "SCLHI_DIV2", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CTRL_TIME_FM

Controller Timing Parameters for I2C Fast Mode signaling.

This register shall be modified only when the Controller is not connected to the I3C bus.

• Offset: 0x58
• Reset default: 0x3ff03ff
• Reset mask: 0x3ff03ff

Fields

{"reg": [{"name": "SCLLO_DIV2", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}, {"name": "SCLHI_DIV2", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

INTERVAL_TIME0

Interval Timers 0 register. Time intervals are specified as two’s complement 8-bit signed offsets added to the default values calculated by the hardware:

• interval_clks = (hw_default_us * clks_per_us) + (signed_adj << shift)

The granularity of the adjustment is timer-dependent because the intervals span a large range, from 1us to 50ms. It is also scaled according to the clock frequency of the IP block, because the supported frequency range is 50MHz to 1.5GHz:

Clock frequencies:

• 50MHz to 64MHz, both inclusive: base weighting applies.
• From 64MHz (exclusive) to 128MHz (inclusive): adjustments have twice the base weighting.
• From 128MHz (excl.) to 256MHz (incl.): adjustments have 4 times the base weighting.
• From 256MHz (excl.) to 512MHz (incl.): adjustments have 8 times the base weighting.
• From 512MHz (excl.) to 1024MHz (incl.): adjustments have 16 times the base weighting.
• From 1024MHz (excl.) to 1500MHz (incl.): adjustments have 32 times the base weighting.

This allows the default intervals (in microseconds) to be adjusted in terms of IP clock cycles to an accuracy of +/- 0.8% typically.

• Offset: 0x5c
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "TARG_BUS_AVAIL", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "READ_STALLED", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "CTRL_BUS_AVAIL", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "DEAD_BUS", "bits": 8, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

INTERVAL_TIME1

Interval Timers 1 register. Time intervals are specified as two’s complement 8-bit signed adjustments to the default values calculated by the hardware.

The granularity of the adjustment is timer-dependent and clock frequency-dependent. The weightings given here apply to the base case of an IP clock frequency up to 64MHz, inclusive. See INTERVAL_TIME0 for details.

• Offset: 0x60
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "COMMAND_RETRY", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "TARG_BUS_IDLE", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "TE0_RECOV", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "TARG_TRX_RST", "bits": 8, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PHY_CONFIG

PHY configuration

• Offset: 0x64
• Reset default: 0x1100003
• Reset mask: 0x8bf00003

Fields

{"reg": [{"name": "SCL_HK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "SDA_HK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 18}, {"name": "CTRL_SDA", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CTRL_SDA_PU_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CTRL_SDA_OD_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CTRL_SDA_PP_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CTRL_SCL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CTRL_SCL_PU_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 1}, {"name": "CTRL_SCL_PP_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "CTRL_DIRECT_DRIVE_EN", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

BLOCKED_ADDR

Blocked target addresses. The controller will raise an error if any attempt is made to access a blocked target address. This feature is intended to safeguard against inadvertent accesses to any I2C device that may try to employ clock-stretching, but it may also be of use diagnostically.

• Offset: 0x68
• Reset default: 0x0
• Reset mask: 0x7f7f7f7f

Fields

{"reg": [{"name": "ADDR0", "bits": 7, "attr": ["rw"], "rotate": 0}, {"bits": 1}, {"name": "MASK0", "bits": 7, "attr": ["rw"], "rotate": 0}, {"bits": 1}, {"name": "ADDR1", "bits": 7, "attr": ["rw"], "rotate": 0}, {"bits": 1}, {"name": "MASK1", "bits": 7, "attr": ["rw"], "rotate": 0}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

BLOCKED_ADDR . MASK1

Address mask for the second set of blocked addresses.

This mask determines which bits of the device address will be tested and matched against the address in ‘ADDR1’. I2C devices are commonly configured with one of a small set of static addresses, differing in only one two address bits. If this field is zero then ‘ADDR1’ is implicitly not used.

BLOCKED_ADDR . ADDR1

Second blocked address.

BLOCKED_ADDR . MASK0

Address mask for the first set of blocked addresses.

This mask determines which bits of the device address will be tested and matched against the address in ‘ADDR0’. I2C devices are commonly configured with one of a small set of static addresses, differing in only one two address bits. If this field is zero then ‘ADDR0’ is implicitly not used.

BLOCKED_ADDR . ADDR0

First blocked address.

BUFFER_CTRL

Buffer control

• Offset: 0x6c
• Reset default: 0x0
• Reset mask: 0xb0000000

Fields

{"reg": [{"bits": 28}, {"name": "SW_ADDR_HI", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 1}, {"name": "CLEAR", "bits": 1, "attr": ["wo"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}

BUFFER_CTRL . CLEAR

Software clear of buffer state including the following: All WPTR and RPTR values are set to the corresponding MIN values, emptying all circular buffers. This shall only be used when both the Controller- and the Target-side functionality are disabled.

BUFFER_CTRL . SW_ADDR_HI

Supplies the high address bits when software performs direct accesses to the internal message buffer. The IP may be configured to map part of its internal message buffer into the upper half of the IP address space. This provides more RAM to a memory-limited system when the I3C is not being used, and may be diagnostically useful when it is used. Since half of the IP address space is typically 2KiB but the message buffer is larger, this field allows software-controlled paging.

BUFFER_STATUS

Buffer status

• Offset: 0x70
• Reset default: 0x0
• Reset mask: 0xc0000000

Fields

{"reg": [{"bits": 30}, {"name": "TTIQ_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "HCIQ_ERR", "bits": 1, "attr": ["rw1c"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}

CTRL_TXBUF_CONFIG

Controller TX Buffer Configuration

• Offset: 0x74
• Reset default: 0x607f0000
• Reset mask: 0x73ff03ff

Fields

{"reg": [{"name": "MIN_ADDR", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}, {"name": "MAX_ADDR", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 2}, {"name": "SIZE_VAL", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}

CTRL_TXBUF_STATE

Controller TX Buffer State.

• Offset: 0x78
• Reset default: 0x0
• Reset mask: 0xc3ff03ff

Fields

{"reg": [{"name": "WPTR", "bits": 10, "attr": ["ro"], "rotate": 0}, {"bits": 6}, {"name": "RPTR", "bits": 10, "attr": ["ro"], "rotate": 0}, {"bits": 4}, {"name": "PRE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FULL", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CTRL_RXBUF_CONFIG

Controller RX Buffer Configuration

• Offset: 0x7c
• Reset default: 0x60ff0080
• Reset mask: 0x73ff03ff

Fields

{"reg": [{"name": "MIN_ADDR", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}, {"name": "MAX_ADDR", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 2}, {"name": "SIZE_VAL", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}

CTRL_RXBUF_STATE

Controller RX Buffer State.

• Offset: 0x80
• Reset default: 0x800080
• Reset mask: 0xc3ff03ff

Fields

{"reg": [{"name": "WPTR", "bits": 10, "attr": ["ro"], "rotate": 0}, {"bits": 6}, {"name": "RPTR", "bits": 10, "attr": ["ro"], "rotate": 0}, {"bits": 4}, {"name": "PRE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FULL", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

COMMAND_QUEUE_CONFIG

Command Queue Configuration.

• Offset: 0x84
• Reset default: 0x1011f100
• Reset mask: 0xff3ff3ff

Fields

{"reg": [{"name": "MIN_ADDR", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 2}, {"name": "MAX_ADDR", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 2}, {"name": "SIZE_VAL", "bits": 8, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

COMMAND_QUEUE_STATE

Command Queue State.

• Offset: 0x88
• Reset default: 0x1000100
• Reset mask: 0xc3ff03ff

Fields

{"reg": [{"name": "WPTR", "bits": 10, "attr": ["ro"], "rotate": 0}, {"bits": 6}, {"name": "RPTR", "bits": 10, "attr": ["ro"], "rotate": 0}, {"bits": 4}, {"name": "PRE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FULL", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

RESPONSE_QUEUE_CONFIG

Response Queue Configuration.

• Offset: 0x8c
• Reset default: 0x1012f120
• Reset mask: 0xff3ff3ff

Fields

{"reg": [{"name": "MIN_ADDR", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 2}, {"name": "MAX_ADDR", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 2}, {"name": "SIZE_VAL", "bits": 8, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

RESPONSE_QUEUE_STATE

Response Queue State.

• Offset: 0x90
• Reset default: 0x1200120
• Reset mask: 0xc3ff03ff

Fields

{"reg": [{"name": "WPTR", "bits": 10, "attr": ["ro"], "rotate": 0}, {"bits": 6}, {"name": "RPTR", "bits": 10, "attr": ["ro"], "rotate": 0}, {"bits": 4}, {"name": "PRE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FULL", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

IBI_CONFIG

In-Band Interrupt Queue Configuration.

• Offset: 0x94
• Reset default: 0x141af130
• Reset mask: 0xff3ff3ff

Fields

{"reg": [{"name": "MIN_ADDR", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 2}, {"name": "MAX_ADDR", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 2}, {"name": "SIZE_VAL", "bits": 8, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

IBI_STATE

In-Band Interrupt Queue State.

• Offset: 0x98
• Reset default: 0x1300130
• Reset mask: 0xc3ff03ff

Fields

{"reg": [{"name": "WPTR", "bits": 10, "attr": ["ro"], "rotate": 0}, {"bits": 6}, {"name": "RPTR", "bits": 10, "attr": ["ro"], "rotate": 0}, {"bits": 4}, {"name": "PRE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FULL", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

IBI_STAT_CONFIG

In-Band Status Descriptor FIFO Configuration.

• Offset: 0x9c
• Reset default: 0x1cf1b0
• Reset mask: 0x3ff3ff

Fields

{"reg": [{"name": "MIN_ADDR", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 2}, {"name": "MAX_ADDR", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 10}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

IBI_STAT_STATE

In-Band Status Descriptor FIFO State.

• Offset: 0xa0
• Reset default: 0x1b001b0
• Reset mask: 0xc3ff03ff

Fields

{"reg": [{"name": "WPTR", "bits": 10, "attr": ["ro"], "rotate": 0}, {"bits": 6}, {"name": "RPTR", "bits": 10, "attr": ["ro"], "rotate": 0}, {"bits": 4}, {"name": "PRE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FULL", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TARG_TXBUF_CONFIG

Target TX Buffer Configuration.

• Reset default: 0x20f01d0
• Reset mask: 0x3ff03ff

Instances

Fields

{"reg": [{"name": "MIN_ADDR", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}, {"name": "MAX_ADDR", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TARG_TXBUF_STATE

Target 0 TX Buffer State.

• Reset default: 0x1d001d0
• Reset mask: 0xc3ff03ff

Instances

Fields

{"reg": [{"name": "WPTR", "bits": 10, "attr": ["ro"], "rotate": 0}, {"bits": 6}, {"name": "RPTR", "bits": 10, "attr": ["ro"], "rotate": 0}, {"bits": 4}, {"name": "PRE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FULL", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TARG_RXBUF_CONFIG

Target RX Buffer Configuration

• Offset: 0xc4
• Reset default: 0x36f02d0
• Reset mask: 0x3ff03ff

Fields

{"reg": [{"name": "MIN_ADDR", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}, {"name": "MAX_ADDR", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TARG_RXBUF_STATE

Target RX Buffer State.

• Offset: 0xc8
• Reset default: 0x2d002d0
• Reset mask: 0xc3ff03ff

Fields

{"reg": [{"name": "WPTR", "bits": 10, "attr": ["ro"], "rotate": 0}, {"bits": 6}, {"name": "RPTR", "bits": 10, "attr": ["ro"], "rotate": 0}, {"bits": 4}, {"name": "PRE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FULL", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TARG_IBI_CONFIG

Target In-Band Interrupt Payload Queue Configuration

• Offset: 0xcc
• Reset default: 0x3af0370
• Reset mask: 0x3ff03ff

Fields

{"reg": [{"name": "MIN_ADDR", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}, {"name": "MAX_ADDR", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TARG_IBI_STATE

Target In-Band Interrupt Payload Queue State.

• Offset: 0xd0
• Reset default: 0x3700370
• Reset mask: 0xc3ff03ff

Fields

{"reg": [{"name": "WPTR", "bits": 10, "attr": ["ro"], "rotate": 0}, {"bits": 6}, {"name": "RPTR", "bits": 10, "attr": ["ro"], "rotate": 0}, {"bits": 4}, {"name": "PRE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FULL", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TARG_TXDESC_CONFIG

Target Transmission Descriptor Queue Configuration.

• Reset default: 0x3b703b0
• Reset mask: 0x3ff03ff

Instances

Fields

{"reg": [{"name": "MIN_ADDR", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}, {"name": "MAX_ADDR", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TARG_TXDESC_STATE

Target Transmission Descriptor Queue State.

• Reset default: 0x3b003b0
• Reset mask: 0xc3ff03ff

Instances

Fields

{"reg": [{"name": "WPTR", "bits": 10, "attr": ["ro"], "rotate": 0}, {"bits": 6}, {"name": "RPTR", "bits": 10, "attr": ["ro"], "rotate": 0}, {"bits": 4}, {"name": "PRE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FULL", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TARG_RXDESC_CONFIG

Target Reception Descriptor Queue Configuration.

• Offset: 0xf4
• Reset default: 0x3df03d0
• Reset mask: 0x3ff03ff

Fields

{"reg": [{"name": "MIN_ADDR", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}, {"name": "MAX_ADDR", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TARG_RXDESC_STATE

Target Reception Descriptor Queue State.

• Offset: 0xf8
• Reset default: 0x3d003d0
• Reset mask: 0xc3ff03ff

Fields

{"reg": [{"name": "WPTR", "bits": 10, "attr": ["ro"], "rotate": 0}, {"bits": 6}, {"name": "RPTR", "bits": 10, "attr": ["ro"], "rotate": 0}, {"bits": 4}, {"name": "PRE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FULL", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TARG_IBIDESC_CONFIG

Target In-Band Interrupt Descriptor Queue Configuration.

• Offset: 0xfc
• Reset default: 0x3ef03e0
• Reset mask: 0x3ff03ff

Fields

{"reg": [{"name": "MIN_ADDR", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}, {"name": "MAX_ADDR", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TARG_IBIDESC_STATE

Target In-Band Interrupt Descriptor Queue State.

• Offset: 0x100
• Reset default: 0x3e003e0
• Reset mask: 0xc3ff03ff

Fields

{"reg": [{"name": "WPTR", "bits": 10, "attr": ["ro"], "rotate": 0}, {"bits": 6}, {"name": "RPTR", "bits": 10, "attr": ["ro"], "rotate": 0}, {"bits": 4}, {"name": "PRE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FULL", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TARG_ASYNC_CONFIG

Target Asynchronous Event Queue Configuration.

• Offset: 0x104
• Reset default: 0x3ff03f0
• Reset mask: 0x3ff03ff

Fields

{"reg": [{"name": "MIN_ADDR", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}, {"name": "MAX_ADDR", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 6}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TARG_ASYNC_STATE

Target Asynchronous Event Queue State.

• Offset: 0x108
• Reset default: 0x3f003f0
• Reset mask: 0xc3ff03ff

Fields

{"reg": [{"name": "WPTR", "bits": 10, "attr": ["ro"], "rotate": 0}, {"bits": 6}, {"name": "RPTR", "bits": 10, "attr": ["ro"], "rotate": 0}, {"bits": 4}, {"name": "PRE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FULL", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

HCI_VERSION

HCI Version.

• Offset: 0x180
• Reset default: 0x120
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "VERSION", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

HC_CONTROL

Host Controller Control.

• Offset: 0x184
• Reset default: 0x48
• Reset mask: 0xe00011d9

Fields

{"reg": [{"name": "IBA_INCLUDE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 2}, {"name": "AUTOCMD_DATA_RPT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DATA_BYTE_ORDER_MODE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "MODE_SELECTOR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "I2C_DEV_PRESENT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "HOT_JOIN_CTRL", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "HALT_ON_CMD_SEQ_TIMEOUT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 16}, {"name": "ABORT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RESUME", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "BUS_ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}

CONTROLLER_DEVICE_ADDR

Controller Device Address.

• Offset: 0x188
• Reset default: 0x0
• Reset mask: 0x807f0000

Fields

{"reg": [{"bits": 16}, {"name": "DYNAMIC_ADDR", "bits": 7, "attr": ["rw"], "rotate": 0}, {"bits": 8}, {"name": "DYNAMIC_ADDR_VALID", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}

HC_CAPABILITIES

Host Controller Capabilities.

• Offset: 0x18c
• Reset default: 0x440
• Reset mask: 0x70303cec

Fields

{"reg": [{"bits": 2}, {"name": "COMBO_COMMAND", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "AUTO_COMMAND", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "STANDBY_CR_CAP", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "HDR_DDR_EN", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "HDR_TS_EN", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 2}, {"name": "CMD_CCC_DEFBYTE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "IBI_DATA_ABORT_EN", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "IBI_CREDIT_COUNT_EN", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SCHEDULED_COMMANDS_EN", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 6}, {"name": "CMD_SIZE", "bits": 2, "attr": ["ro"], "rotate": -90}, {"bits": 6}, {"name": "SG_CAPABILITY_CR_EN", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SG_CAPABILITY_IBI_EN", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SG_CAPABILITY_DC_EN", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}

RESET_CONTROL

Reset Control.

• Offset: 0x190
• Reset default: 0x0
• Reset mask: 0x3f

Fields

{"reg": [{"name": "SOFT_RST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "CMD_QUEUE_RST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RESP_QUEUE_RST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "TX_FIFO_RST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RX_FIFO_RST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "IBI_QUEUE_RST", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}

PRESENT_STATE

Present State.

• Offset: 0x194
• Reset default: 0x0
• Reset mask: 0x4

Fields

{"reg": [{"bits": 2}, {"name": "AC_CURRENT_OWN", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}

INTR_STATUS

Interrupt Status.

• Offset: 0x1a0
• Reset default: 0x0
• Reset mask: 0x7c00

Fields

{"reg": [{"bits": 10}, {"name": "HC_INTERNAL_ERR_STAT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "HC_SEQ_CANCEL_STAT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "HC_WARN_CMD_SEQ_STALL_STAT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "HC_ERR_CMD_SEQ_TIMEOUT_STAT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "SCHED_CMD_MISSED_TICK_STAT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 17}], "config": {"lanes": 1, "fontsize": 10, "vspace": 290}}

INTR_STATUS_ENABLE

Interrupt Status Enable.

• Offset: 0x1a4
• Reset default: 0x0
• Reset mask: 0x7c00

Fields

{"reg": [{"bits": 10}, {"name": "HC_INTERNAL_ERR_STAT_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "HC_SEQ_CANCEL_STAT_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "HC_WARN_CMD_SEQ_STALL_STAT_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "HC_ERR_CMD_SEQ_TIMEOUT_STAT_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "SCHED_CMD_MISSED_TICK_STAT_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 17}], "config": {"lanes": 1, "fontsize": 10, "vspace": 320}}

INTR_SIGNAL_ENABLE

Interrupt Signal Enable.

• Offset: 0x1a8
• Reset default: 0x0
• Reset mask: 0x7c00

Fields

{"reg": [{"bits": 10}, {"name": "HC_INTERNAL_ERR_SIGNAL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "HC_SEQ_CANCEL_SIGNAL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "HC_WARN_CMD_SEQ_STALL_SIGNAL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "HC_ERR_CMD_SEQ_TIMEOUT_SIGNAL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "SCHED_CMD_MISSED_TICK_SIGNAL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 17}], "config": {"lanes": 1, "fontsize": 10, "vspace": 340}}

INTR_FORCE

Interrupt Force.

• Offset: 0x1ac
• Reset default: 0x0
• Reset mask: 0x7c00

Fields

{"reg": [{"bits": 10}, {"name": "HC_INTERNAL_ERR_FORCE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "HC_SEQ_CANCEL_FORCE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "HC_WARN_CMD_SEQ_STALL_FORCE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "HC_ERR_CMD_SEQ_TIMEOUT_FORCE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "SCHED_CMD_MISSED_TICK_FORCE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 17}], "config": {"lanes": 1, "fontsize": 10, "vspace": 300}}

DAT_SECTION_OFFSET

Device Address Table Section Offset.

• Offset: 0x1b0
• Reset default: 0x20880
• Reset mask: 0xf007ffff

Fields

{"reg": [{"name": "TABLE_OFFSET", "bits": 12, "attr": ["ro"], "rotate": 0}, {"name": "TABLE_SIZE", "bits": 7, "attr": ["ro"], "rotate": 0}, {"bits": 9}, {"name": "ENTRY_SIZE", "bits": 4, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 120}}

DCT_SECTION_OFFSET

Device Characteristics Table Section Offset.

• Offset: 0x1b4
• Reset default: 0x20a80
• Reset mask: 0xf0ffffff

Fields

{"reg": [{"name": "TABLE_OFFSET", "bits": 12, "attr": ["ro"], "rotate": 0}, {"name": "TABLE_SIZE", "bits": 7, "attr": ["ro"], "rotate": 0}, {"name": "TABLE_INDEX", "bits": 5, "attr": ["rw"], "rotate": -90}, {"bits": 4}, {"name": "ENTRY_SIZE", "bits": 4, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

RING_HEADERS_SECTION_OFFSET

Ring Headers Section Offset.

• Offset: 0x1b8
• Reset default: 0x0
• Reset mask: 0xffff

Fields

{"reg": [{"name": "SECTION_OFFSET", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PIO_SECTION_OFFSET

PIO Section Offset.

• Offset: 0x1bc
• Reset default: 0x80
• Reset mask: 0xffff

Fields

{"reg": [{"name": "SECTION_OFFSET", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

EXT_CAPS_SECTION_OFFSET

Extended Capabilities Section Offset.

• Offset: 0x1c0
• Reset default: 0x120
• Reset mask: 0xffff

Fields

{"reg": [{"name": "SECTION_OFFSET", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

INT_CTRL_CMDS_EN

Internal Control Command Subtype Support.

• Offset: 0x1cc
• Reset default: 0x61
• Reset mask: 0xffff

Fields

{"reg": [{"name": "ICC_SUPPORT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MIPI_CMDS_SUPPORTED", "bits": 15, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

IBI_NOTIFY_CTRL

IBI Notify Control.

• Offset: 0x1d8
• Reset default: 0x0
• Reset mask: 0xb

Fields

{"reg": [{"name": "NOTIFY_HJ_REJECTED", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "NOTIFY_CRR_REJECTED", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 1}, {"name": "NOTIFY_IBI_REJECTED", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}

IBI_DATA_ABORT_CTRL

IBI Data Abort Control.

• Offset: 0x1dc
• Reset default: 0x0
• Reset mask: 0x801fff00

Fields

{"reg": [{"bits": 8}, {"name": "MATCH_IBI_ID", "bits": 8, "attr": ["wo"], "rotate": 0}, {"name": "AFTER_N_CHUNKS", "bits": 2, "attr": ["wo"], "rotate": -90}, {"name": "MATCH_STATUS_TYPE", "bits": 3, "attr": ["wo"], "rotate": -90}, {"bits": 10}, {"name": "IBI_DATA_ABORT_MON", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}

DEV_CTX_BASE_LO

Device Context Base Address Low.

• Offset: 0x1e0
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "BASE_LO", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

DEV_CTX_BASE_HI

Device Context Base Address High.

• Offset: 0x1e4
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "BASE_HI", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

DEV_CTX_SG

Device Context Scatter-Gather Support.

• Offset: 0x1e8
• Reset default: 0x0
• Reset mask: 0x8000ffff

Fields

{"reg": [{"name": "LIST_SIZE", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 15}, {"name": "BLP", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

HCI_PORTS

HCI ports, occupying successive word addresses:

• COMMAND_QUEUE_PORT - Write-only Command Descriptor queue.

• RESPONSE_QUEUE_PORT - Read-only Response Descriptor queue.

• XFER_DATA_PORT - Read/write data buffer; Rx Data Buffer and Tx Data Buffer.

• IBI_PORT - Read-only In-Band Interrupt queue.

• Word Aligned Offset Range: 0x200to0x20c

• Size (words): 4

• Access: rw

• Byte writes are not supported.

QUEUE_THLD_CTRL

Queue Threshold Control.

• Offset: 0x210
• Reset default: 0x1010101
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "CMD_EMPTY_BUF_THLD", "bits": 8, "attr": ["rw"], "rotate": -90}, {"name": "RESP_BUF_THLD", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "IBI_DATA_SEGMENT_SIZE", "bits": 8, "attr": ["rw"], "rotate": -90}, {"name": "IBI_STATUS_THLD", "bits": 8, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}

DATA_BUFFER_THLD_CTRL

Transfer Data Buffer Threshold Control.

• Offset: 0x214
• Reset default: 0x1010101
• Reset mask: 0x7070707

Fields

{"reg": [{"name": "TX_BUF_THLD", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 5}, {"name": "RX_BUF_THLD", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 5}, {"name": "TX_START_THLD", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 5}, {"name": "RX_START_THLD", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 5}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}

QUEUE_SIZE

Queue Size.

• Offset: 0x218
• Reset default: 0x6061408
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "CR_QUEUE_SIZE", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "IBI_STATUS_SIZE", "bits": 8, "attr": ["ro"], "rotate": -90}, {"name": "RX_DATA_BUFFER_SIZE", "bits": 8, "attr": ["ro"], "rotate": -90}, {"name": "TX_DATA_BUFFER_SIZE", "bits": 8, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}

ALT_QUEUE_SIZE

Alternate Queue Size.

• Offset: 0x21c
• Reset default: 0x11000010
• Reset mask: 0x110000ff

Fields

{"reg": [{"name": "ALT_RESP_QUEUE_SIZE", "bits": 8, "attr": ["ro"], "rotate": -90}, {"bits": 16}, {"name": "ALT_RESP_QUEUE_EN", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 3}, {"name": "EXT_IBI_QUEUE_EN", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 3}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}

PIO_INTR_STATUS

PIO Interrupt Status.

• Offset: 0x220
• Reset default: 0x0
• Reset mask: 0x23f

Fields

{"reg": [{"name": "TX_THLD_STAT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RX_THLD_STAT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "IBI_STATUS_THLD_STAT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_QUEUE_READY_STAT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RESP_READY_STAT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TRANSFER_ABORT_STAT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 3}, {"name": "TRANSFER_ERR_STAT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 22}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}

PIO_INTR_STATUS_ENABLE

PIO Interrupt Status Enable.

• Offset: 0x224
• Reset default: 0x0
• Reset mask: 0x23f

Fields

{"reg": [{"name": "TX_THLD_STAT_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RX_THLD_STAT_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "IBI_STATUS_THLD_STAT_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CMD_QUEUE_READY_STAT_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RESP_READY_STAT_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "TRANSFER_ABORT_STAT_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "TRANSFER_ERR_STAT_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 22}], "config": {"lanes": 1, "fontsize": 10, "vspace": 250}}

PIO_INTR_SIGNAL_ENABLE

PIO Interrupt Signal Enable.

• Offset: 0x228
• Reset default: 0x0
• Reset mask: 0x23f

Fields

{"reg": [{"name": "TX_THLD_SIGNAL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RX_THLD_SIGNAL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "IBI_STATUS_THLD_SIGNAL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CMD_QUEUE_READY_SIGNAL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RESP_READY_SIGNAL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "TRANSFER_ABORT_SIGNAL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "TRANSFER_ERR_SIGNAL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 22}], "config": {"lanes": 1, "fontsize": 10, "vspace": 270}}

PIO_INTR_FORCE

PIO Interrupt Force.

• Offset: 0x22c
• Reset default: 0x0
• Reset mask: 0x23f

Fields

{"reg": [{"name": "TX_THLD_FORCE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RX_THLD_FORCE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "IBI_THLD_FORCE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "CMD_QUEUE_READY_FORCE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "RESP_READY_FORCE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "TRANSFER_ABORT_FORCE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 3}, {"name": "TRANSFER_ERR_FORCE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 22}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}

PIO_CONTROL

PIO Control.

• Offset: 0x230
• Reset default: 0x1
• Reset mask: 0x7

Fields

{"reg": [{"name": "ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "RS", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ABORT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ID_EXTCAP_HEADER

Hardware Identification Extended Capability Header

• Offset: 0x2a0
• Reset default: 0x401
• Reset mask: 0xffffff

Fields

{"reg": [{"name": "CAP_ID", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "CAP_LENGTH", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

COMP_MANUFACTURER

Component Manufacturer.

• Offset: 0x2a4
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "MIPI_VENDOR_ID", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

COMP_VERSION

Component Version.

• Offset: 0x2a8
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "I3C_VER_ID", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

COMP_TYPE

Component Type.

• Offset: 0x2ac
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "I3C_PRODUCT_ID", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CTRL_CFG_EXTCAP_HEADER

Controller Config Extended Capability Header

• Offset: 0x2b0
• Reset default: 0x202
• Reset mask: 0xffffff

Fields

{"reg": [{"name": "CAP_ID", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "CAP_LENGTH", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

CONTROLLER_CONFIG

Controller Config.

• Offset: 0x2b4
• Reset default: 0x10
• Reset mask: 0x30

Fields

{"reg": [{"bits": 4}, {"name": "OPERATION_MODE", "bits": 2, "attr": ["ro"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}

DBR_EXTCAP_HEADER

Dead Bus Recovery Extended Capability Header

• Offset: 0x2b8
• Reset default: 0x20b
• Reset mask: 0xffffff

Fields

{"reg": [{"name": "CAP_ID", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "CAP_LENGTH", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

DBR_ENGAGE

Dead Bus Recovery Engage.

• Offset: 0x2bc
• Reset default: 0x0
• Reset mask: 0x7f037f

Fields

{"reg": [{"name": "DBR_VERIF_KEY", "bits": 4, "attr": ["wo"], "rotate": -90}, {"name": "DBR_MODE", "bits": 3, "attr": ["wo"], "rotate": -90}, {"bits": 1}, {"name": "DBR_ASX_TIMING", "bits": 2, "attr": ["wo"], "rotate": -90}, {"bits": 6}, {"name": "DBR_IBI_ADDRESS", "bits": 7, "attr": ["wo"], "rotate": -90}, {"bits": 9}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}}

DEBUG_EXTCAP_HEADER

Debug Specific Extended Capability Header

• Offset: 0x2c0
• Reset default: 0x60c
• Reset mask: 0xffffff

Fields

{"reg": [{"name": "CAP_ID", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "CAP_LENGTH", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

QUEUE_STATUS_LEVEL

Queue Status Level

• Offset: 0x2c4
• Reset default: 0x10
• Reset mask: 0x1fffffff

Fields

{"reg": [{"name": "CMD_QUEUE_FREE_LVL", "bits": 8, "attr": ["ro"], "rotate": -90}, {"name": "RESPONSE_BUFFER_LVL", "bits": 8, "attr": ["ro"], "rotate": -90}, {"name": "IBI_BUFFER_LVL", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "IBI_STATUS_CNT", "bits": 5, "attr": ["ro"], "rotate": -90}, {"bits": 3}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}

DATA_BUFFER_STATUS_LEVEL

Data Buffer Status Level

• Offset: 0x2c8
• Reset default: 0x80
• Reset mask: 0xffff

Fields

{"reg": [{"name": "TX_BUF_FREE_LVL", "bits": 8, "attr": ["ro"], "rotate": -90}, {"name": "RX_BUF_LVL", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}}

PRESENT_STATE_DEBUG

Present State Debug

• Offset: 0x2cc
• Reset default: 0x3
• Reset mask: 0xf3f3f03

Fields

{"reg": [{"name": "SCL_LINE_SIGNAL_LEVEL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SDA_LINE_SIGNAL_LEVEL", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 6}, {"name": "BCL_TFR_STATUS", "bits": 6, "attr": ["ro"], "rotate": -90}, {"bits": 2}, {"name": "BCL_TFR_ST_STATUS", "bits": 6, "attr": ["ro"], "rotate": -90}, {"bits": 2}, {"name": "CMD_TID", "bits": 4, "attr": ["ro"], "rotate": -90}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}

MX_ERROR_COUNTERS

Controller Error Counters.

• Offset: 0x2d0
• Reset default: 0x0
• Reset mask: 0xff

Fields

{"reg": [{"name": "CE2_ERROR_COUNT", "bits": 8, "attr": ["ro"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}}

SCHED_CMDS_DEBUG

Scheduled Commands Debug

• Offset: 0x2d4
• Reset default: 0x0
• Reset mask: 0x3fffff

Fields

{"reg": [{"name": "SCHED_HANDLER", "bits": 4, "attr": ["ro"], "rotate": -90}, {"name": "INST_ID", "bits": 3, "attr": ["ro"], "rotate": -90}, {"name": "ERR_TYPE", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ENTITY_ID", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "TICK_INTERVAL", "bits": 5, "attr": ["ro"], "rotate": -90}, {"name": "ERR_OCCURRED", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 10}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}}

STBY_CR_EXTCAP_HEADER

Standby Controller Extended Capability Header

• Offset: 0x2d8
• Reset default: 0xe12
• Reset mask: 0xffffff

Fields

{"reg": [{"name": "CAP_ID", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "CAP_LENGTH", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

STBY_CR_CONTROL

Standby Controller Control

• Offset: 0x2dc
• Reset default: 0x100c
• Reset mask: 0xc010f73f

Fields

{"reg": [{"name": "PENDING_RX_NACK", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "HANDOFF_DELAY_NACK", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ACR_FSM_OP_SELECT", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "PRIME_ACCEPT_GETACCCR", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "HANDOFF_DEEP_SLEEP", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CR_REQUEST_SEND", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 2}, {"name": "BCAST_CCC_IBI_RING", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 1}, {"name": "TARGET_XACT_ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DAA_SETAASA_ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DAA_SETDASA_ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DAA_ENTDAA_ENABLE", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 4}, {"name": "RSTACT_DEFBYTE_02", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 9}, {"name": "STBY_CR_ENABLE_INIT", "bits": 2, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}

STBY_CR_CONTROL . STBY_CR_ENABLE_INIT

Host Controller Secondary Controller Enable. 0 - DISABLED: Secondary Controller operation is disabled. 1 - ACM_INIT: Enabled, but Host Controller initializes in Active Controller mode. 2 - SCM_RUNNING: Enabled, initializes in Standby Controller mode. 3 - SCM_HOT_JOIN: Enabled, Host Controller conditionally becomes a Hot-Joining Device before operating in Standby Controller mode.

STBY_CR_CONTROL . RSTACT_DEFBYTE_02

RSTACT Support DefByte 0x02

STBY_CR_CONTROL . DAA_ENTDAA_ENABLE

Dynamic Address Method Enable.

STBY_CR_CONTROL . DAA_SETDASA_ENABLE

Dynamic Address Method Enable.

STBY_CR_CONTROL . DAA_SETAASA_ENABLE

Dynamic Address Method Enable.

STBY_CR_CONTROL . TARGET_XACT_ENABLE

Target Transaction Interface Servicing Enable.

STBY_CR_CONTROL . BCAST_CCC_IBI_RING

Ring Bundle IBI Selector for Broadcast CCC Capture.

STBY_CR_CONTROL . CR_REQUEST_SEND

Send Controller Role Request.

STBY_CR_CONTROL . HANDOFF_DEEP_SLEEP

Handoff Deep Sleep.

STBY_CR_CONTROL . PRIME_ACCEPT_GETACCCR

Prime to Accept Controller Role.

STBY_CR_CONTROL . ACR_FSM_OP_SELECT

Active Controller Select.

STBY_CR_CONTROL . HANDOFF_DELAY_NACK

Handoff Delay NACK.

STBY_CR_CONTROL . PENDING_RX_NACK

Pending RX NACK.

STBY_CR_DEVICE_ADDR

Standby Controller Device Address

• Offset: 0x2e0
• Reset default: 0x0
• Reset mask: 0x807f807f

Fields

{"reg": [{"name": "STATIC_ADDR", "bits": 7, "attr": ["rw"], "rotate": 0}, {"bits": 8}, {"name": "STATIC_ADDR_VALID", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "DYNAMIC_ADDR", "bits": 7, "attr": ["ro"], "rotate": 0}, {"bits": 8}, {"name": "DYNAMIC_ADDR_VALID", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}

STBY_CR_CAPABILITIES

Standby Controller Capabilities

• Offset: 0x2e4
• Reset default: 0xf020
• Reset mask: 0xf020

Fields

{"reg": [{"bits": 5}, {"name": "SIMPLE_CRR_SUPPORT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 6}, {"name": "TARGET_XACT_SUPPORT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DAA_SETAASA_SUPPORT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DAA_SETDASA_SUPPORT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DAA_ENTDAA_SUPPORT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 210}}

STBY_CR_STATUS

Standby Controller Status

• Offset: 0x2ec
• Reset default: 0x0
• Reset mask: 0x1e4

Fields

{"reg": [{"bits": 2}, {"name": "AC_CURRENT_OWN", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 2}, {"name": "SIMPLE_CRR_STATUS", "bits": 3, "attr": ["ro"], "rotate": -90}, {"name": "HJ_REQ_STATUS", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 190}}

STBY_CR_DEVICE_CHAR

Standby Controller Device Characteristics

• Offset: 0x2f0
• Reset default: 0x60000000
• Reset mask: 0xfffffffe

Fields

{"reg": [{"bits": 1}, {"name": "PID_HI", "bits": 15, "attr": ["rw"], "rotate": 0}, {"name": "DCR", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "BCR_VAR", "bits": 5, "attr": ["rw"], "rotate": 0}, {"name": "BCR_FIXED", "bits": 3, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}

STBY_CR_DEVICE_PID_LO

Standby Controller PID Low

• Offset: 0x2f4
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "PID_LO", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

STBY_CR_INTR_STATUS

Standby Controller Interrupt Status

• Offset: 0x2f8
• Reset default: 0x0
• Reset mask: 0xf7c0f

Fields

{"reg": [{"name": "ACR_HANDOFF_OK_REMAIN_STAT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "ACR_HANDOFF_OK_PRIMED_STAT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "ACR_HANDOFF_ERR_FAIL_STAT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "ACR_HANDOFF_ERR_M3_STAT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 6}, {"name": "CRR_RESPONSE_STAT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "STBY_CR_DYN_ADDR_STAT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "STBY_CR_ACCEPT_NACKED_STAT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "STBY_CR_ACCEPT_OK_STAT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "STBY_CR_ACCEPT_ERR_STAT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 1}, {"name": "STBY_CR_OP_RSTACT_STAT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "CCC_PARAM_MODIFIED_STAT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "CCC_UNHANDLED_NACK_STAT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "CCC_FATAL_RSTDAA_ERR_STAT", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 280}}

STBY_CR_INTR_SIGNAL_ENABLE

Standby Controller Interrupt Signal Enable

• Offset: 0x300
• Reset default: 0xc0000
• Reset mask: 0xf7c0f

Fields

{"reg": [{"name": "ACR_HANDOFF_OK_REMAIN_SIGNAL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ACR_HANDOFF_OK_PRIMED_SIGNAL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ACR_HANDOFF_ERR_FAIL_SIGNAL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "ACR_HANDOFF_ERR_M3_SIGNAL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 6}, {"name": "CRR_RESPONSE_SIGNAL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "STBY_CR_DYN_ADDR_SIGNAL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "STBY_CR_ACCEPT_NACKED_SIGNAL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "STBY_CR_ACCEPT_OK_SIGNAL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "STBY_CR_ACCEPT_ERR_SIGNAL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 1}, {"name": "STBY_CR_OP_RSTACT_SIGNAL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CCC_PARAM_MODIFIED_SIGNAL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CCC_UNHANDLED_NACK_SIGNAL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "CCC_FATAL_RSTDAA_ERR_SIGNAL_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 330}}

STBY_CR_INTR_FORCE

Standby Controller Interrupt Force

• Offset: 0x304
• Reset default: 0x0
• Reset mask: 0xf7c00

Fields

{"reg": [{"bits": 10}, {"name": "CRR_RESPONSE_FORCE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "STBY_CR_DYN_ADDR_FORCE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "STBY_CR_ACCEPT_NACKED_FORCE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "STBY_CR_ACCEPT_OK_FORCE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "STBY_CR_ACCEPT_ERR_FORCE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 1}, {"name": "STBY_CR_OP_RSTACT_FORCE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "CCC_PARAM_MODIFIED_FORCE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "CCC_UNHANDLED_NACK_FORCE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"name": "CCC_FATAL_RSTDAA_ERR_FORCE", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 12}], "config": {"lanes": 1, "fontsize": 10, "vspace": 290}}

STBY_CR_CCC_CONFIG_GETCAPS

Standby Controller CCC Auto-Response Config Get Capabilities

• Offset: 0x308
• Reset default: 0x0
• Reset mask: 0xf07

Fields

{"reg": [{"name": "F2_CRCAP1_BUS_CONFIG", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 5}, {"name": "F2_CRCAP2_DEV_INTERACT", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 20}], "config": {"lanes": 1, "fontsize": 10, "vspace": 240}}

STBY_CR_CCC_CONFIG_RSTACT_PARAMS

Standby Controller CCC Auto-Response Config Target Reset Action

• Offset: 0x30c
• Reset default: 0x80000000
• Reset mask: 0x80ffffff

Fields

{"reg": [{"name": "RST_ACTION", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "RESET_TIME_PERIPHERAL", "bits": 8, "attr": ["rw"], "rotate": -90}, {"name": "RESET_TIME_TARGET", "bits": 8, "attr": ["rw"], "rotate": -90}, {"bits": 7}, {"name": "RESET_DYNAMIC_ADDR", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 230}}

TTI_EXTCAP_HEADER

Target Transaction Interface Extended Capability Header

• Offset: 0x310
• Reset default: 0x59c8
• Reset mask: 0xffffff

Fields

{"reg": [{"name": "CAP_ID", "bits": 8, "attr": ["ro"], "rotate": 0}, {"name": "CAP_LENGTH", "bits": 16, "attr": ["ro"], "rotate": 0}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

TARG_INTR_STATUS

Target Interrupt Status.

• Offset: 0x314
• Reset default: 0x0
• Reset mask: 0x800f0f7f

Fields

{"reg": [{"name": "RX_DESC_READY_STAT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "IBI_STATUS_THLD_STAT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ASYNC_EVT_READY_STAT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TRANSFER_ABORT_STAT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TRANSFER_ERR_STAT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "RX_BUFFER_OVF_STAT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "ASYNC_EVT_OVF_STAT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "TX0_THLD_STAT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TX1_THLD_STAT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TX2_THLD_STAT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TX3_THLD_STAT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 4}, {"name": "TX0_DESC_READY_STAT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TX1_DESC_READY_STAT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TX2_DESC_READY_STAT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "TX3_DESC_READY_STAT", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 11}, {"name": "TE_STAT", "bits": 1, "attr": ["ro"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 220}}