CHERIoT DV document

Goals

• Verify the CHERIoT memory subsystem with a SV/UVM testbench based on the CIP testbench architecture.
• Run the tests in the testplan towards closing code and functional coverage.

Current status

• Design & verification stage
  • HW development stages

Design features

See the CHERIoT Memory Subsystem HWIP technical specification.

Testbench

hw/ip/cheriot/dv/tb.sv instantiates hw/ip/cheriot/rtl/cheriot.sv with:

• Clock and reset interface
• TileLink host interface on the regs CSR port
• Alerts (alert_esc_if) for fatal_fault

Building and running tests

Built and run with dvsim.py.

$ dvsim hw/ip/cheriot/dv/cheriot_sim_cfg.hjson -i cheriot_smoke   # smoke only
$ dvsim hw/ip/cheriot/dv/cheriot_sim_cfg.hjson                    # CSR, alert and TL-UL suites

Testplan

Testplan