opentitanlib/otp/
alert_handler_regs.rs

1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4
5/* automatically generated by rust-bindgen 0.60.1 */
6
7pub const ALERT_HANDLER_PARAM_N_ALERTS: u32 = 65;
8pub const ALERT_HANDLER_PARAM_N_LPG: u32 = 22;
9pub const ALERT_HANDLER_PARAM_N_LPG_WIDTH: u32 = 5;
10pub const ALERT_HANDLER_PARAM_ESC_CNT_DW: u32 = 32;
11pub const ALERT_HANDLER_PARAM_ACCU_CNT_DW: u32 = 16;
12pub const ALERT_HANDLER_PARAM_N_CLASSES: u32 = 4;
13pub const ALERT_HANDLER_PARAM_N_ESC_SEV: u32 = 4;
14pub const ALERT_HANDLER_PARAM_N_PHASES: u32 = 4;
15pub const ALERT_HANDLER_PARAM_N_LOC_ALERT: u32 = 7;
16pub const ALERT_HANDLER_PARAM_PING_CNT_DW: u32 = 16;
17pub const ALERT_HANDLER_PARAM_PHASE_DW: u32 = 2;
18pub const ALERT_HANDLER_PARAM_CLASS_DW: u32 = 2;
19pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ALERT_PINGFAIL: u32 = 0;
20pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ESC_PINGFAIL: u32 = 1;
21pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ALERT_INTEGFAIL: u32 = 2;
22pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ESC_INTEGFAIL: u32 = 3;
23pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_BUS_INTEGFAIL: u32 = 4;
24pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_SHADOW_REG_UPDATE_ERROR: u32 = 5;
25pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_SHADOW_REG_STORAGE_ERROR: u32 = 6;
26pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_LAST: u32 = 6;
27pub const ALERT_HANDLER_PARAM_REG_WIDTH: u32 = 32;
28pub const ALERT_HANDLER_INTR_COMMON_CLASSA_BIT: u32 = 0;
29pub const ALERT_HANDLER_INTR_COMMON_CLASSB_BIT: u32 = 1;
30pub const ALERT_HANDLER_INTR_COMMON_CLASSC_BIT: u32 = 2;
31pub const ALERT_HANDLER_INTR_COMMON_CLASSD_BIT: u32 = 3;
32pub const ALERT_HANDLER_INTR_STATE_REG_OFFSET: u32 = 0;
33pub const ALERT_HANDLER_INTR_STATE_REG_RESVAL: u32 = 0;
34pub const ALERT_HANDLER_INTR_STATE_CLASSA_BIT: u32 = 0;
35pub const ALERT_HANDLER_INTR_STATE_CLASSB_BIT: u32 = 1;
36pub const ALERT_HANDLER_INTR_STATE_CLASSC_BIT: u32 = 2;
37pub const ALERT_HANDLER_INTR_STATE_CLASSD_BIT: u32 = 3;
38pub const ALERT_HANDLER_INTR_ENABLE_REG_OFFSET: u32 = 4;
39pub const ALERT_HANDLER_INTR_ENABLE_REG_RESVAL: u32 = 0;
40pub const ALERT_HANDLER_INTR_ENABLE_CLASSA_BIT: u32 = 0;
41pub const ALERT_HANDLER_INTR_ENABLE_CLASSB_BIT: u32 = 1;
42pub const ALERT_HANDLER_INTR_ENABLE_CLASSC_BIT: u32 = 2;
43pub const ALERT_HANDLER_INTR_ENABLE_CLASSD_BIT: u32 = 3;
44pub const ALERT_HANDLER_INTR_TEST_REG_OFFSET: u32 = 8;
45pub const ALERT_HANDLER_INTR_TEST_REG_RESVAL: u32 = 0;
46pub const ALERT_HANDLER_INTR_TEST_CLASSA_BIT: u32 = 0;
47pub const ALERT_HANDLER_INTR_TEST_CLASSB_BIT: u32 = 1;
48pub const ALERT_HANDLER_INTR_TEST_CLASSC_BIT: u32 = 2;
49pub const ALERT_HANDLER_INTR_TEST_CLASSD_BIT: u32 = 3;
50pub const ALERT_HANDLER_PING_TIMER_REGWEN_REG_OFFSET: u32 = 12;
51pub const ALERT_HANDLER_PING_TIMER_REGWEN_REG_RESVAL: u32 = 1;
52pub const ALERT_HANDLER_PING_TIMER_REGWEN_PING_TIMER_REGWEN_BIT: u32 = 0;
53pub const ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 16;
54pub const ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_REG_RESVAL: u32 = 256;
55pub const ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_MASK: u32 = 65535;
56pub const ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_OFFSET: u32 = 0;
57pub const ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_OFFSET: u32 = 20;
58pub const ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_RESVAL: u32 = 0;
59pub const ALERT_HANDLER_PING_TIMER_EN_SHADOWED_PING_TIMER_EN_SHADOWED_BIT: u32 = 0;
60pub const ALERT_HANDLER_ALERT_REGWEN_EN_FIELD_WIDTH: u32 = 1;
61pub const ALERT_HANDLER_ALERT_REGWEN_MULTIREG_COUNT: u32 = 65;
62pub const ALERT_HANDLER_ALERT_REGWEN_0_REG_OFFSET: u32 = 24;
63pub const ALERT_HANDLER_ALERT_REGWEN_0_REG_RESVAL: u32 = 1;
64pub const ALERT_HANDLER_ALERT_REGWEN_0_EN_0_BIT: u32 = 0;
65pub const ALERT_HANDLER_ALERT_REGWEN_1_REG_OFFSET: u32 = 28;
66pub const ALERT_HANDLER_ALERT_REGWEN_1_REG_RESVAL: u32 = 1;
67pub const ALERT_HANDLER_ALERT_REGWEN_1_EN_1_BIT: u32 = 0;
68pub const ALERT_HANDLER_ALERT_REGWEN_2_REG_OFFSET: u32 = 32;
69pub const ALERT_HANDLER_ALERT_REGWEN_2_REG_RESVAL: u32 = 1;
70pub const ALERT_HANDLER_ALERT_REGWEN_2_EN_2_BIT: u32 = 0;
71pub const ALERT_HANDLER_ALERT_REGWEN_3_REG_OFFSET: u32 = 36;
72pub const ALERT_HANDLER_ALERT_REGWEN_3_REG_RESVAL: u32 = 1;
73pub const ALERT_HANDLER_ALERT_REGWEN_3_EN_3_BIT: u32 = 0;
74pub const ALERT_HANDLER_ALERT_REGWEN_4_REG_OFFSET: u32 = 40;
75pub const ALERT_HANDLER_ALERT_REGWEN_4_REG_RESVAL: u32 = 1;
76pub const ALERT_HANDLER_ALERT_REGWEN_4_EN_4_BIT: u32 = 0;
77pub const ALERT_HANDLER_ALERT_REGWEN_5_REG_OFFSET: u32 = 44;
78pub const ALERT_HANDLER_ALERT_REGWEN_5_REG_RESVAL: u32 = 1;
79pub const ALERT_HANDLER_ALERT_REGWEN_5_EN_5_BIT: u32 = 0;
80pub const ALERT_HANDLER_ALERT_REGWEN_6_REG_OFFSET: u32 = 48;
81pub const ALERT_HANDLER_ALERT_REGWEN_6_REG_RESVAL: u32 = 1;
82pub const ALERT_HANDLER_ALERT_REGWEN_6_EN_6_BIT: u32 = 0;
83pub const ALERT_HANDLER_ALERT_REGWEN_7_REG_OFFSET: u32 = 52;
84pub const ALERT_HANDLER_ALERT_REGWEN_7_REG_RESVAL: u32 = 1;
85pub const ALERT_HANDLER_ALERT_REGWEN_7_EN_7_BIT: u32 = 0;
86pub const ALERT_HANDLER_ALERT_REGWEN_8_REG_OFFSET: u32 = 56;
87pub const ALERT_HANDLER_ALERT_REGWEN_8_REG_RESVAL: u32 = 1;
88pub const ALERT_HANDLER_ALERT_REGWEN_8_EN_8_BIT: u32 = 0;
89pub const ALERT_HANDLER_ALERT_REGWEN_9_REG_OFFSET: u32 = 60;
90pub const ALERT_HANDLER_ALERT_REGWEN_9_REG_RESVAL: u32 = 1;
91pub const ALERT_HANDLER_ALERT_REGWEN_9_EN_9_BIT: u32 = 0;
92pub const ALERT_HANDLER_ALERT_REGWEN_10_REG_OFFSET: u32 = 64;
93pub const ALERT_HANDLER_ALERT_REGWEN_10_REG_RESVAL: u32 = 1;
94pub const ALERT_HANDLER_ALERT_REGWEN_10_EN_10_BIT: u32 = 0;
95pub const ALERT_HANDLER_ALERT_REGWEN_11_REG_OFFSET: u32 = 68;
96pub const ALERT_HANDLER_ALERT_REGWEN_11_REG_RESVAL: u32 = 1;
97pub const ALERT_HANDLER_ALERT_REGWEN_11_EN_11_BIT: u32 = 0;
98pub const ALERT_HANDLER_ALERT_REGWEN_12_REG_OFFSET: u32 = 72;
99pub const ALERT_HANDLER_ALERT_REGWEN_12_REG_RESVAL: u32 = 1;
100pub const ALERT_HANDLER_ALERT_REGWEN_12_EN_12_BIT: u32 = 0;
101pub const ALERT_HANDLER_ALERT_REGWEN_13_REG_OFFSET: u32 = 76;
102pub const ALERT_HANDLER_ALERT_REGWEN_13_REG_RESVAL: u32 = 1;
103pub const ALERT_HANDLER_ALERT_REGWEN_13_EN_13_BIT: u32 = 0;
104pub const ALERT_HANDLER_ALERT_REGWEN_14_REG_OFFSET: u32 = 80;
105pub const ALERT_HANDLER_ALERT_REGWEN_14_REG_RESVAL: u32 = 1;
106pub const ALERT_HANDLER_ALERT_REGWEN_14_EN_14_BIT: u32 = 0;
107pub const ALERT_HANDLER_ALERT_REGWEN_15_REG_OFFSET: u32 = 84;
108pub const ALERT_HANDLER_ALERT_REGWEN_15_REG_RESVAL: u32 = 1;
109pub const ALERT_HANDLER_ALERT_REGWEN_15_EN_15_BIT: u32 = 0;
110pub const ALERT_HANDLER_ALERT_REGWEN_16_REG_OFFSET: u32 = 88;
111pub const ALERT_HANDLER_ALERT_REGWEN_16_REG_RESVAL: u32 = 1;
112pub const ALERT_HANDLER_ALERT_REGWEN_16_EN_16_BIT: u32 = 0;
113pub const ALERT_HANDLER_ALERT_REGWEN_17_REG_OFFSET: u32 = 92;
114pub const ALERT_HANDLER_ALERT_REGWEN_17_REG_RESVAL: u32 = 1;
115pub const ALERT_HANDLER_ALERT_REGWEN_17_EN_17_BIT: u32 = 0;
116pub const ALERT_HANDLER_ALERT_REGWEN_18_REG_OFFSET: u32 = 96;
117pub const ALERT_HANDLER_ALERT_REGWEN_18_REG_RESVAL: u32 = 1;
118pub const ALERT_HANDLER_ALERT_REGWEN_18_EN_18_BIT: u32 = 0;
119pub const ALERT_HANDLER_ALERT_REGWEN_19_REG_OFFSET: u32 = 100;
120pub const ALERT_HANDLER_ALERT_REGWEN_19_REG_RESVAL: u32 = 1;
121pub const ALERT_HANDLER_ALERT_REGWEN_19_EN_19_BIT: u32 = 0;
122pub const ALERT_HANDLER_ALERT_REGWEN_20_REG_OFFSET: u32 = 104;
123pub const ALERT_HANDLER_ALERT_REGWEN_20_REG_RESVAL: u32 = 1;
124pub const ALERT_HANDLER_ALERT_REGWEN_20_EN_20_BIT: u32 = 0;
125pub const ALERT_HANDLER_ALERT_REGWEN_21_REG_OFFSET: u32 = 108;
126pub const ALERT_HANDLER_ALERT_REGWEN_21_REG_RESVAL: u32 = 1;
127pub const ALERT_HANDLER_ALERT_REGWEN_21_EN_21_BIT: u32 = 0;
128pub const ALERT_HANDLER_ALERT_REGWEN_22_REG_OFFSET: u32 = 112;
129pub const ALERT_HANDLER_ALERT_REGWEN_22_REG_RESVAL: u32 = 1;
130pub const ALERT_HANDLER_ALERT_REGWEN_22_EN_22_BIT: u32 = 0;
131pub const ALERT_HANDLER_ALERT_REGWEN_23_REG_OFFSET: u32 = 116;
132pub const ALERT_HANDLER_ALERT_REGWEN_23_REG_RESVAL: u32 = 1;
133pub const ALERT_HANDLER_ALERT_REGWEN_23_EN_23_BIT: u32 = 0;
134pub const ALERT_HANDLER_ALERT_REGWEN_24_REG_OFFSET: u32 = 120;
135pub const ALERT_HANDLER_ALERT_REGWEN_24_REG_RESVAL: u32 = 1;
136pub const ALERT_HANDLER_ALERT_REGWEN_24_EN_24_BIT: u32 = 0;
137pub const ALERT_HANDLER_ALERT_REGWEN_25_REG_OFFSET: u32 = 124;
138pub const ALERT_HANDLER_ALERT_REGWEN_25_REG_RESVAL: u32 = 1;
139pub const ALERT_HANDLER_ALERT_REGWEN_25_EN_25_BIT: u32 = 0;
140pub const ALERT_HANDLER_ALERT_REGWEN_26_REG_OFFSET: u32 = 128;
141pub const ALERT_HANDLER_ALERT_REGWEN_26_REG_RESVAL: u32 = 1;
142pub const ALERT_HANDLER_ALERT_REGWEN_26_EN_26_BIT: u32 = 0;
143pub const ALERT_HANDLER_ALERT_REGWEN_27_REG_OFFSET: u32 = 132;
144pub const ALERT_HANDLER_ALERT_REGWEN_27_REG_RESVAL: u32 = 1;
145pub const ALERT_HANDLER_ALERT_REGWEN_27_EN_27_BIT: u32 = 0;
146pub const ALERT_HANDLER_ALERT_REGWEN_28_REG_OFFSET: u32 = 136;
147pub const ALERT_HANDLER_ALERT_REGWEN_28_REG_RESVAL: u32 = 1;
148pub const ALERT_HANDLER_ALERT_REGWEN_28_EN_28_BIT: u32 = 0;
149pub const ALERT_HANDLER_ALERT_REGWEN_29_REG_OFFSET: u32 = 140;
150pub const ALERT_HANDLER_ALERT_REGWEN_29_REG_RESVAL: u32 = 1;
151pub const ALERT_HANDLER_ALERT_REGWEN_29_EN_29_BIT: u32 = 0;
152pub const ALERT_HANDLER_ALERT_REGWEN_30_REG_OFFSET: u32 = 144;
153pub const ALERT_HANDLER_ALERT_REGWEN_30_REG_RESVAL: u32 = 1;
154pub const ALERT_HANDLER_ALERT_REGWEN_30_EN_30_BIT: u32 = 0;
155pub const ALERT_HANDLER_ALERT_REGWEN_31_REG_OFFSET: u32 = 148;
156pub const ALERT_HANDLER_ALERT_REGWEN_31_REG_RESVAL: u32 = 1;
157pub const ALERT_HANDLER_ALERT_REGWEN_31_EN_31_BIT: u32 = 0;
158pub const ALERT_HANDLER_ALERT_REGWEN_32_REG_OFFSET: u32 = 152;
159pub const ALERT_HANDLER_ALERT_REGWEN_32_REG_RESVAL: u32 = 1;
160pub const ALERT_HANDLER_ALERT_REGWEN_32_EN_32_BIT: u32 = 0;
161pub const ALERT_HANDLER_ALERT_REGWEN_33_REG_OFFSET: u32 = 156;
162pub const ALERT_HANDLER_ALERT_REGWEN_33_REG_RESVAL: u32 = 1;
163pub const ALERT_HANDLER_ALERT_REGWEN_33_EN_33_BIT: u32 = 0;
164pub const ALERT_HANDLER_ALERT_REGWEN_34_REG_OFFSET: u32 = 160;
165pub const ALERT_HANDLER_ALERT_REGWEN_34_REG_RESVAL: u32 = 1;
166pub const ALERT_HANDLER_ALERT_REGWEN_34_EN_34_BIT: u32 = 0;
167pub const ALERT_HANDLER_ALERT_REGWEN_35_REG_OFFSET: u32 = 164;
168pub const ALERT_HANDLER_ALERT_REGWEN_35_REG_RESVAL: u32 = 1;
169pub const ALERT_HANDLER_ALERT_REGWEN_35_EN_35_BIT: u32 = 0;
170pub const ALERT_HANDLER_ALERT_REGWEN_36_REG_OFFSET: u32 = 168;
171pub const ALERT_HANDLER_ALERT_REGWEN_36_REG_RESVAL: u32 = 1;
172pub const ALERT_HANDLER_ALERT_REGWEN_36_EN_36_BIT: u32 = 0;
173pub const ALERT_HANDLER_ALERT_REGWEN_37_REG_OFFSET: u32 = 172;
174pub const ALERT_HANDLER_ALERT_REGWEN_37_REG_RESVAL: u32 = 1;
175pub const ALERT_HANDLER_ALERT_REGWEN_37_EN_37_BIT: u32 = 0;
176pub const ALERT_HANDLER_ALERT_REGWEN_38_REG_OFFSET: u32 = 176;
177pub const ALERT_HANDLER_ALERT_REGWEN_38_REG_RESVAL: u32 = 1;
178pub const ALERT_HANDLER_ALERT_REGWEN_38_EN_38_BIT: u32 = 0;
179pub const ALERT_HANDLER_ALERT_REGWEN_39_REG_OFFSET: u32 = 180;
180pub const ALERT_HANDLER_ALERT_REGWEN_39_REG_RESVAL: u32 = 1;
181pub const ALERT_HANDLER_ALERT_REGWEN_39_EN_39_BIT: u32 = 0;
182pub const ALERT_HANDLER_ALERT_REGWEN_40_REG_OFFSET: u32 = 184;
183pub const ALERT_HANDLER_ALERT_REGWEN_40_REG_RESVAL: u32 = 1;
184pub const ALERT_HANDLER_ALERT_REGWEN_40_EN_40_BIT: u32 = 0;
185pub const ALERT_HANDLER_ALERT_REGWEN_41_REG_OFFSET: u32 = 188;
186pub const ALERT_HANDLER_ALERT_REGWEN_41_REG_RESVAL: u32 = 1;
187pub const ALERT_HANDLER_ALERT_REGWEN_41_EN_41_BIT: u32 = 0;
188pub const ALERT_HANDLER_ALERT_REGWEN_42_REG_OFFSET: u32 = 192;
189pub const ALERT_HANDLER_ALERT_REGWEN_42_REG_RESVAL: u32 = 1;
190pub const ALERT_HANDLER_ALERT_REGWEN_42_EN_42_BIT: u32 = 0;
191pub const ALERT_HANDLER_ALERT_REGWEN_43_REG_OFFSET: u32 = 196;
192pub const ALERT_HANDLER_ALERT_REGWEN_43_REG_RESVAL: u32 = 1;
193pub const ALERT_HANDLER_ALERT_REGWEN_43_EN_43_BIT: u32 = 0;
194pub const ALERT_HANDLER_ALERT_REGWEN_44_REG_OFFSET: u32 = 200;
195pub const ALERT_HANDLER_ALERT_REGWEN_44_REG_RESVAL: u32 = 1;
196pub const ALERT_HANDLER_ALERT_REGWEN_44_EN_44_BIT: u32 = 0;
197pub const ALERT_HANDLER_ALERT_REGWEN_45_REG_OFFSET: u32 = 204;
198pub const ALERT_HANDLER_ALERT_REGWEN_45_REG_RESVAL: u32 = 1;
199pub const ALERT_HANDLER_ALERT_REGWEN_45_EN_45_BIT: u32 = 0;
200pub const ALERT_HANDLER_ALERT_REGWEN_46_REG_OFFSET: u32 = 208;
201pub const ALERT_HANDLER_ALERT_REGWEN_46_REG_RESVAL: u32 = 1;
202pub const ALERT_HANDLER_ALERT_REGWEN_46_EN_46_BIT: u32 = 0;
203pub const ALERT_HANDLER_ALERT_REGWEN_47_REG_OFFSET: u32 = 212;
204pub const ALERT_HANDLER_ALERT_REGWEN_47_REG_RESVAL: u32 = 1;
205pub const ALERT_HANDLER_ALERT_REGWEN_47_EN_47_BIT: u32 = 0;
206pub const ALERT_HANDLER_ALERT_REGWEN_48_REG_OFFSET: u32 = 216;
207pub const ALERT_HANDLER_ALERT_REGWEN_48_REG_RESVAL: u32 = 1;
208pub const ALERT_HANDLER_ALERT_REGWEN_48_EN_48_BIT: u32 = 0;
209pub const ALERT_HANDLER_ALERT_REGWEN_49_REG_OFFSET: u32 = 220;
210pub const ALERT_HANDLER_ALERT_REGWEN_49_REG_RESVAL: u32 = 1;
211pub const ALERT_HANDLER_ALERT_REGWEN_49_EN_49_BIT: u32 = 0;
212pub const ALERT_HANDLER_ALERT_REGWEN_50_REG_OFFSET: u32 = 224;
213pub const ALERT_HANDLER_ALERT_REGWEN_50_REG_RESVAL: u32 = 1;
214pub const ALERT_HANDLER_ALERT_REGWEN_50_EN_50_BIT: u32 = 0;
215pub const ALERT_HANDLER_ALERT_REGWEN_51_REG_OFFSET: u32 = 228;
216pub const ALERT_HANDLER_ALERT_REGWEN_51_REG_RESVAL: u32 = 1;
217pub const ALERT_HANDLER_ALERT_REGWEN_51_EN_51_BIT: u32 = 0;
218pub const ALERT_HANDLER_ALERT_REGWEN_52_REG_OFFSET: u32 = 232;
219pub const ALERT_HANDLER_ALERT_REGWEN_52_REG_RESVAL: u32 = 1;
220pub const ALERT_HANDLER_ALERT_REGWEN_52_EN_52_BIT: u32 = 0;
221pub const ALERT_HANDLER_ALERT_REGWEN_53_REG_OFFSET: u32 = 236;
222pub const ALERT_HANDLER_ALERT_REGWEN_53_REG_RESVAL: u32 = 1;
223pub const ALERT_HANDLER_ALERT_REGWEN_53_EN_53_BIT: u32 = 0;
224pub const ALERT_HANDLER_ALERT_REGWEN_54_REG_OFFSET: u32 = 240;
225pub const ALERT_HANDLER_ALERT_REGWEN_54_REG_RESVAL: u32 = 1;
226pub const ALERT_HANDLER_ALERT_REGWEN_54_EN_54_BIT: u32 = 0;
227pub const ALERT_HANDLER_ALERT_REGWEN_55_REG_OFFSET: u32 = 244;
228pub const ALERT_HANDLER_ALERT_REGWEN_55_REG_RESVAL: u32 = 1;
229pub const ALERT_HANDLER_ALERT_REGWEN_55_EN_55_BIT: u32 = 0;
230pub const ALERT_HANDLER_ALERT_REGWEN_56_REG_OFFSET: u32 = 248;
231pub const ALERT_HANDLER_ALERT_REGWEN_56_REG_RESVAL: u32 = 1;
232pub const ALERT_HANDLER_ALERT_REGWEN_56_EN_56_BIT: u32 = 0;
233pub const ALERT_HANDLER_ALERT_REGWEN_57_REG_OFFSET: u32 = 252;
234pub const ALERT_HANDLER_ALERT_REGWEN_57_REG_RESVAL: u32 = 1;
235pub const ALERT_HANDLER_ALERT_REGWEN_57_EN_57_BIT: u32 = 0;
236pub const ALERT_HANDLER_ALERT_REGWEN_58_REG_OFFSET: u32 = 256;
237pub const ALERT_HANDLER_ALERT_REGWEN_58_REG_RESVAL: u32 = 1;
238pub const ALERT_HANDLER_ALERT_REGWEN_58_EN_58_BIT: u32 = 0;
239pub const ALERT_HANDLER_ALERT_REGWEN_59_REG_OFFSET: u32 = 260;
240pub const ALERT_HANDLER_ALERT_REGWEN_59_REG_RESVAL: u32 = 1;
241pub const ALERT_HANDLER_ALERT_REGWEN_59_EN_59_BIT: u32 = 0;
242pub const ALERT_HANDLER_ALERT_REGWEN_60_REG_OFFSET: u32 = 264;
243pub const ALERT_HANDLER_ALERT_REGWEN_60_REG_RESVAL: u32 = 1;
244pub const ALERT_HANDLER_ALERT_REGWEN_60_EN_60_BIT: u32 = 0;
245pub const ALERT_HANDLER_ALERT_REGWEN_61_REG_OFFSET: u32 = 268;
246pub const ALERT_HANDLER_ALERT_REGWEN_61_REG_RESVAL: u32 = 1;
247pub const ALERT_HANDLER_ALERT_REGWEN_61_EN_61_BIT: u32 = 0;
248pub const ALERT_HANDLER_ALERT_REGWEN_62_REG_OFFSET: u32 = 272;
249pub const ALERT_HANDLER_ALERT_REGWEN_62_REG_RESVAL: u32 = 1;
250pub const ALERT_HANDLER_ALERT_REGWEN_62_EN_62_BIT: u32 = 0;
251pub const ALERT_HANDLER_ALERT_REGWEN_63_REG_OFFSET: u32 = 276;
252pub const ALERT_HANDLER_ALERT_REGWEN_63_REG_RESVAL: u32 = 1;
253pub const ALERT_HANDLER_ALERT_REGWEN_63_EN_63_BIT: u32 = 0;
254pub const ALERT_HANDLER_ALERT_REGWEN_64_REG_OFFSET: u32 = 280;
255pub const ALERT_HANDLER_ALERT_REGWEN_64_REG_RESVAL: u32 = 1;
256pub const ALERT_HANDLER_ALERT_REGWEN_64_EN_64_BIT: u32 = 0;
257pub const ALERT_HANDLER_ALERT_EN_SHADOWED_EN_A_FIELD_WIDTH: u32 = 1;
258pub const ALERT_HANDLER_ALERT_EN_SHADOWED_MULTIREG_COUNT: u32 = 65;
259pub const ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_OFFSET: u32 = 284;
260pub const ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_RESVAL: u32 = 0;
261pub const ALERT_HANDLER_ALERT_EN_SHADOWED_0_EN_A_0_BIT: u32 = 0;
262pub const ALERT_HANDLER_ALERT_EN_SHADOWED_1_REG_OFFSET: u32 = 288;
263pub const ALERT_HANDLER_ALERT_EN_SHADOWED_1_REG_RESVAL: u32 = 0;
264pub const ALERT_HANDLER_ALERT_EN_SHADOWED_1_EN_A_1_BIT: u32 = 0;
265pub const ALERT_HANDLER_ALERT_EN_SHADOWED_2_REG_OFFSET: u32 = 292;
266pub const ALERT_HANDLER_ALERT_EN_SHADOWED_2_REG_RESVAL: u32 = 0;
267pub const ALERT_HANDLER_ALERT_EN_SHADOWED_2_EN_A_2_BIT: u32 = 0;
268pub const ALERT_HANDLER_ALERT_EN_SHADOWED_3_REG_OFFSET: u32 = 296;
269pub const ALERT_HANDLER_ALERT_EN_SHADOWED_3_REG_RESVAL: u32 = 0;
270pub const ALERT_HANDLER_ALERT_EN_SHADOWED_3_EN_A_3_BIT: u32 = 0;
271pub const ALERT_HANDLER_ALERT_EN_SHADOWED_4_REG_OFFSET: u32 = 300;
272pub const ALERT_HANDLER_ALERT_EN_SHADOWED_4_REG_RESVAL: u32 = 0;
273pub const ALERT_HANDLER_ALERT_EN_SHADOWED_4_EN_A_4_BIT: u32 = 0;
274pub const ALERT_HANDLER_ALERT_EN_SHADOWED_5_REG_OFFSET: u32 = 304;
275pub const ALERT_HANDLER_ALERT_EN_SHADOWED_5_REG_RESVAL: u32 = 0;
276pub const ALERT_HANDLER_ALERT_EN_SHADOWED_5_EN_A_5_BIT: u32 = 0;
277pub const ALERT_HANDLER_ALERT_EN_SHADOWED_6_REG_OFFSET: u32 = 308;
278pub const ALERT_HANDLER_ALERT_EN_SHADOWED_6_REG_RESVAL: u32 = 0;
279pub const ALERT_HANDLER_ALERT_EN_SHADOWED_6_EN_A_6_BIT: u32 = 0;
280pub const ALERT_HANDLER_ALERT_EN_SHADOWED_7_REG_OFFSET: u32 = 312;
281pub const ALERT_HANDLER_ALERT_EN_SHADOWED_7_REG_RESVAL: u32 = 0;
282pub const ALERT_HANDLER_ALERT_EN_SHADOWED_7_EN_A_7_BIT: u32 = 0;
283pub const ALERT_HANDLER_ALERT_EN_SHADOWED_8_REG_OFFSET: u32 = 316;
284pub const ALERT_HANDLER_ALERT_EN_SHADOWED_8_REG_RESVAL: u32 = 0;
285pub const ALERT_HANDLER_ALERT_EN_SHADOWED_8_EN_A_8_BIT: u32 = 0;
286pub const ALERT_HANDLER_ALERT_EN_SHADOWED_9_REG_OFFSET: u32 = 320;
287pub const ALERT_HANDLER_ALERT_EN_SHADOWED_9_REG_RESVAL: u32 = 0;
288pub const ALERT_HANDLER_ALERT_EN_SHADOWED_9_EN_A_9_BIT: u32 = 0;
289pub const ALERT_HANDLER_ALERT_EN_SHADOWED_10_REG_OFFSET: u32 = 324;
290pub const ALERT_HANDLER_ALERT_EN_SHADOWED_10_REG_RESVAL: u32 = 0;
291pub const ALERT_HANDLER_ALERT_EN_SHADOWED_10_EN_A_10_BIT: u32 = 0;
292pub const ALERT_HANDLER_ALERT_EN_SHADOWED_11_REG_OFFSET: u32 = 328;
293pub const ALERT_HANDLER_ALERT_EN_SHADOWED_11_REG_RESVAL: u32 = 0;
294pub const ALERT_HANDLER_ALERT_EN_SHADOWED_11_EN_A_11_BIT: u32 = 0;
295pub const ALERT_HANDLER_ALERT_EN_SHADOWED_12_REG_OFFSET: u32 = 332;
296pub const ALERT_HANDLER_ALERT_EN_SHADOWED_12_REG_RESVAL: u32 = 0;
297pub const ALERT_HANDLER_ALERT_EN_SHADOWED_12_EN_A_12_BIT: u32 = 0;
298pub const ALERT_HANDLER_ALERT_EN_SHADOWED_13_REG_OFFSET: u32 = 336;
299pub const ALERT_HANDLER_ALERT_EN_SHADOWED_13_REG_RESVAL: u32 = 0;
300pub const ALERT_HANDLER_ALERT_EN_SHADOWED_13_EN_A_13_BIT: u32 = 0;
301pub const ALERT_HANDLER_ALERT_EN_SHADOWED_14_REG_OFFSET: u32 = 340;
302pub const ALERT_HANDLER_ALERT_EN_SHADOWED_14_REG_RESVAL: u32 = 0;
303pub const ALERT_HANDLER_ALERT_EN_SHADOWED_14_EN_A_14_BIT: u32 = 0;
304pub const ALERT_HANDLER_ALERT_EN_SHADOWED_15_REG_OFFSET: u32 = 344;
305pub const ALERT_HANDLER_ALERT_EN_SHADOWED_15_REG_RESVAL: u32 = 0;
306pub const ALERT_HANDLER_ALERT_EN_SHADOWED_15_EN_A_15_BIT: u32 = 0;
307pub const ALERT_HANDLER_ALERT_EN_SHADOWED_16_REG_OFFSET: u32 = 348;
308pub const ALERT_HANDLER_ALERT_EN_SHADOWED_16_REG_RESVAL: u32 = 0;
309pub const ALERT_HANDLER_ALERT_EN_SHADOWED_16_EN_A_16_BIT: u32 = 0;
310pub const ALERT_HANDLER_ALERT_EN_SHADOWED_17_REG_OFFSET: u32 = 352;
311pub const ALERT_HANDLER_ALERT_EN_SHADOWED_17_REG_RESVAL: u32 = 0;
312pub const ALERT_HANDLER_ALERT_EN_SHADOWED_17_EN_A_17_BIT: u32 = 0;
313pub const ALERT_HANDLER_ALERT_EN_SHADOWED_18_REG_OFFSET: u32 = 356;
314pub const ALERT_HANDLER_ALERT_EN_SHADOWED_18_REG_RESVAL: u32 = 0;
315pub const ALERT_HANDLER_ALERT_EN_SHADOWED_18_EN_A_18_BIT: u32 = 0;
316pub const ALERT_HANDLER_ALERT_EN_SHADOWED_19_REG_OFFSET: u32 = 360;
317pub const ALERT_HANDLER_ALERT_EN_SHADOWED_19_REG_RESVAL: u32 = 0;
318pub const ALERT_HANDLER_ALERT_EN_SHADOWED_19_EN_A_19_BIT: u32 = 0;
319pub const ALERT_HANDLER_ALERT_EN_SHADOWED_20_REG_OFFSET: u32 = 364;
320pub const ALERT_HANDLER_ALERT_EN_SHADOWED_20_REG_RESVAL: u32 = 0;
321pub const ALERT_HANDLER_ALERT_EN_SHADOWED_20_EN_A_20_BIT: u32 = 0;
322pub const ALERT_HANDLER_ALERT_EN_SHADOWED_21_REG_OFFSET: u32 = 368;
323pub const ALERT_HANDLER_ALERT_EN_SHADOWED_21_REG_RESVAL: u32 = 0;
324pub const ALERT_HANDLER_ALERT_EN_SHADOWED_21_EN_A_21_BIT: u32 = 0;
325pub const ALERT_HANDLER_ALERT_EN_SHADOWED_22_REG_OFFSET: u32 = 372;
326pub const ALERT_HANDLER_ALERT_EN_SHADOWED_22_REG_RESVAL: u32 = 0;
327pub const ALERT_HANDLER_ALERT_EN_SHADOWED_22_EN_A_22_BIT: u32 = 0;
328pub const ALERT_HANDLER_ALERT_EN_SHADOWED_23_REG_OFFSET: u32 = 376;
329pub const ALERT_HANDLER_ALERT_EN_SHADOWED_23_REG_RESVAL: u32 = 0;
330pub const ALERT_HANDLER_ALERT_EN_SHADOWED_23_EN_A_23_BIT: u32 = 0;
331pub const ALERT_HANDLER_ALERT_EN_SHADOWED_24_REG_OFFSET: u32 = 380;
332pub const ALERT_HANDLER_ALERT_EN_SHADOWED_24_REG_RESVAL: u32 = 0;
333pub const ALERT_HANDLER_ALERT_EN_SHADOWED_24_EN_A_24_BIT: u32 = 0;
334pub const ALERT_HANDLER_ALERT_EN_SHADOWED_25_REG_OFFSET: u32 = 384;
335pub const ALERT_HANDLER_ALERT_EN_SHADOWED_25_REG_RESVAL: u32 = 0;
336pub const ALERT_HANDLER_ALERT_EN_SHADOWED_25_EN_A_25_BIT: u32 = 0;
337pub const ALERT_HANDLER_ALERT_EN_SHADOWED_26_REG_OFFSET: u32 = 388;
338pub const ALERT_HANDLER_ALERT_EN_SHADOWED_26_REG_RESVAL: u32 = 0;
339pub const ALERT_HANDLER_ALERT_EN_SHADOWED_26_EN_A_26_BIT: u32 = 0;
340pub const ALERT_HANDLER_ALERT_EN_SHADOWED_27_REG_OFFSET: u32 = 392;
341pub const ALERT_HANDLER_ALERT_EN_SHADOWED_27_REG_RESVAL: u32 = 0;
342pub const ALERT_HANDLER_ALERT_EN_SHADOWED_27_EN_A_27_BIT: u32 = 0;
343pub const ALERT_HANDLER_ALERT_EN_SHADOWED_28_REG_OFFSET: u32 = 396;
344pub const ALERT_HANDLER_ALERT_EN_SHADOWED_28_REG_RESVAL: u32 = 0;
345pub const ALERT_HANDLER_ALERT_EN_SHADOWED_28_EN_A_28_BIT: u32 = 0;
346pub const ALERT_HANDLER_ALERT_EN_SHADOWED_29_REG_OFFSET: u32 = 400;
347pub const ALERT_HANDLER_ALERT_EN_SHADOWED_29_REG_RESVAL: u32 = 0;
348pub const ALERT_HANDLER_ALERT_EN_SHADOWED_29_EN_A_29_BIT: u32 = 0;
349pub const ALERT_HANDLER_ALERT_EN_SHADOWED_30_REG_OFFSET: u32 = 404;
350pub const ALERT_HANDLER_ALERT_EN_SHADOWED_30_REG_RESVAL: u32 = 0;
351pub const ALERT_HANDLER_ALERT_EN_SHADOWED_30_EN_A_30_BIT: u32 = 0;
352pub const ALERT_HANDLER_ALERT_EN_SHADOWED_31_REG_OFFSET: u32 = 408;
353pub const ALERT_HANDLER_ALERT_EN_SHADOWED_31_REG_RESVAL: u32 = 0;
354pub const ALERT_HANDLER_ALERT_EN_SHADOWED_31_EN_A_31_BIT: u32 = 0;
355pub const ALERT_HANDLER_ALERT_EN_SHADOWED_32_REG_OFFSET: u32 = 412;
356pub const ALERT_HANDLER_ALERT_EN_SHADOWED_32_REG_RESVAL: u32 = 0;
357pub const ALERT_HANDLER_ALERT_EN_SHADOWED_32_EN_A_32_BIT: u32 = 0;
358pub const ALERT_HANDLER_ALERT_EN_SHADOWED_33_REG_OFFSET: u32 = 416;
359pub const ALERT_HANDLER_ALERT_EN_SHADOWED_33_REG_RESVAL: u32 = 0;
360pub const ALERT_HANDLER_ALERT_EN_SHADOWED_33_EN_A_33_BIT: u32 = 0;
361pub const ALERT_HANDLER_ALERT_EN_SHADOWED_34_REG_OFFSET: u32 = 420;
362pub const ALERT_HANDLER_ALERT_EN_SHADOWED_34_REG_RESVAL: u32 = 0;
363pub const ALERT_HANDLER_ALERT_EN_SHADOWED_34_EN_A_34_BIT: u32 = 0;
364pub const ALERT_HANDLER_ALERT_EN_SHADOWED_35_REG_OFFSET: u32 = 424;
365pub const ALERT_HANDLER_ALERT_EN_SHADOWED_35_REG_RESVAL: u32 = 0;
366pub const ALERT_HANDLER_ALERT_EN_SHADOWED_35_EN_A_35_BIT: u32 = 0;
367pub const ALERT_HANDLER_ALERT_EN_SHADOWED_36_REG_OFFSET: u32 = 428;
368pub const ALERT_HANDLER_ALERT_EN_SHADOWED_36_REG_RESVAL: u32 = 0;
369pub const ALERT_HANDLER_ALERT_EN_SHADOWED_36_EN_A_36_BIT: u32 = 0;
370pub const ALERT_HANDLER_ALERT_EN_SHADOWED_37_REG_OFFSET: u32 = 432;
371pub const ALERT_HANDLER_ALERT_EN_SHADOWED_37_REG_RESVAL: u32 = 0;
372pub const ALERT_HANDLER_ALERT_EN_SHADOWED_37_EN_A_37_BIT: u32 = 0;
373pub const ALERT_HANDLER_ALERT_EN_SHADOWED_38_REG_OFFSET: u32 = 436;
374pub const ALERT_HANDLER_ALERT_EN_SHADOWED_38_REG_RESVAL: u32 = 0;
375pub const ALERT_HANDLER_ALERT_EN_SHADOWED_38_EN_A_38_BIT: u32 = 0;
376pub const ALERT_HANDLER_ALERT_EN_SHADOWED_39_REG_OFFSET: u32 = 440;
377pub const ALERT_HANDLER_ALERT_EN_SHADOWED_39_REG_RESVAL: u32 = 0;
378pub const ALERT_HANDLER_ALERT_EN_SHADOWED_39_EN_A_39_BIT: u32 = 0;
379pub const ALERT_HANDLER_ALERT_EN_SHADOWED_40_REG_OFFSET: u32 = 444;
380pub const ALERT_HANDLER_ALERT_EN_SHADOWED_40_REG_RESVAL: u32 = 0;
381pub const ALERT_HANDLER_ALERT_EN_SHADOWED_40_EN_A_40_BIT: u32 = 0;
382pub const ALERT_HANDLER_ALERT_EN_SHADOWED_41_REG_OFFSET: u32 = 448;
383pub const ALERT_HANDLER_ALERT_EN_SHADOWED_41_REG_RESVAL: u32 = 0;
384pub const ALERT_HANDLER_ALERT_EN_SHADOWED_41_EN_A_41_BIT: u32 = 0;
385pub const ALERT_HANDLER_ALERT_EN_SHADOWED_42_REG_OFFSET: u32 = 452;
386pub const ALERT_HANDLER_ALERT_EN_SHADOWED_42_REG_RESVAL: u32 = 0;
387pub const ALERT_HANDLER_ALERT_EN_SHADOWED_42_EN_A_42_BIT: u32 = 0;
388pub const ALERT_HANDLER_ALERT_EN_SHADOWED_43_REG_OFFSET: u32 = 456;
389pub const ALERT_HANDLER_ALERT_EN_SHADOWED_43_REG_RESVAL: u32 = 0;
390pub const ALERT_HANDLER_ALERT_EN_SHADOWED_43_EN_A_43_BIT: u32 = 0;
391pub const ALERT_HANDLER_ALERT_EN_SHADOWED_44_REG_OFFSET: u32 = 460;
392pub const ALERT_HANDLER_ALERT_EN_SHADOWED_44_REG_RESVAL: u32 = 0;
393pub const ALERT_HANDLER_ALERT_EN_SHADOWED_44_EN_A_44_BIT: u32 = 0;
394pub const ALERT_HANDLER_ALERT_EN_SHADOWED_45_REG_OFFSET: u32 = 464;
395pub const ALERT_HANDLER_ALERT_EN_SHADOWED_45_REG_RESVAL: u32 = 0;
396pub const ALERT_HANDLER_ALERT_EN_SHADOWED_45_EN_A_45_BIT: u32 = 0;
397pub const ALERT_HANDLER_ALERT_EN_SHADOWED_46_REG_OFFSET: u32 = 468;
398pub const ALERT_HANDLER_ALERT_EN_SHADOWED_46_REG_RESVAL: u32 = 0;
399pub const ALERT_HANDLER_ALERT_EN_SHADOWED_46_EN_A_46_BIT: u32 = 0;
400pub const ALERT_HANDLER_ALERT_EN_SHADOWED_47_REG_OFFSET: u32 = 472;
401pub const ALERT_HANDLER_ALERT_EN_SHADOWED_47_REG_RESVAL: u32 = 0;
402pub const ALERT_HANDLER_ALERT_EN_SHADOWED_47_EN_A_47_BIT: u32 = 0;
403pub const ALERT_HANDLER_ALERT_EN_SHADOWED_48_REG_OFFSET: u32 = 476;
404pub const ALERT_HANDLER_ALERT_EN_SHADOWED_48_REG_RESVAL: u32 = 0;
405pub const ALERT_HANDLER_ALERT_EN_SHADOWED_48_EN_A_48_BIT: u32 = 0;
406pub const ALERT_HANDLER_ALERT_EN_SHADOWED_49_REG_OFFSET: u32 = 480;
407pub const ALERT_HANDLER_ALERT_EN_SHADOWED_49_REG_RESVAL: u32 = 0;
408pub const ALERT_HANDLER_ALERT_EN_SHADOWED_49_EN_A_49_BIT: u32 = 0;
409pub const ALERT_HANDLER_ALERT_EN_SHADOWED_50_REG_OFFSET: u32 = 484;
410pub const ALERT_HANDLER_ALERT_EN_SHADOWED_50_REG_RESVAL: u32 = 0;
411pub const ALERT_HANDLER_ALERT_EN_SHADOWED_50_EN_A_50_BIT: u32 = 0;
412pub const ALERT_HANDLER_ALERT_EN_SHADOWED_51_REG_OFFSET: u32 = 488;
413pub const ALERT_HANDLER_ALERT_EN_SHADOWED_51_REG_RESVAL: u32 = 0;
414pub const ALERT_HANDLER_ALERT_EN_SHADOWED_51_EN_A_51_BIT: u32 = 0;
415pub const ALERT_HANDLER_ALERT_EN_SHADOWED_52_REG_OFFSET: u32 = 492;
416pub const ALERT_HANDLER_ALERT_EN_SHADOWED_52_REG_RESVAL: u32 = 0;
417pub const ALERT_HANDLER_ALERT_EN_SHADOWED_52_EN_A_52_BIT: u32 = 0;
418pub const ALERT_HANDLER_ALERT_EN_SHADOWED_53_REG_OFFSET: u32 = 496;
419pub const ALERT_HANDLER_ALERT_EN_SHADOWED_53_REG_RESVAL: u32 = 0;
420pub const ALERT_HANDLER_ALERT_EN_SHADOWED_53_EN_A_53_BIT: u32 = 0;
421pub const ALERT_HANDLER_ALERT_EN_SHADOWED_54_REG_OFFSET: u32 = 500;
422pub const ALERT_HANDLER_ALERT_EN_SHADOWED_54_REG_RESVAL: u32 = 0;
423pub const ALERT_HANDLER_ALERT_EN_SHADOWED_54_EN_A_54_BIT: u32 = 0;
424pub const ALERT_HANDLER_ALERT_EN_SHADOWED_55_REG_OFFSET: u32 = 504;
425pub const ALERT_HANDLER_ALERT_EN_SHADOWED_55_REG_RESVAL: u32 = 0;
426pub const ALERT_HANDLER_ALERT_EN_SHADOWED_55_EN_A_55_BIT: u32 = 0;
427pub const ALERT_HANDLER_ALERT_EN_SHADOWED_56_REG_OFFSET: u32 = 508;
428pub const ALERT_HANDLER_ALERT_EN_SHADOWED_56_REG_RESVAL: u32 = 0;
429pub const ALERT_HANDLER_ALERT_EN_SHADOWED_56_EN_A_56_BIT: u32 = 0;
430pub const ALERT_HANDLER_ALERT_EN_SHADOWED_57_REG_OFFSET: u32 = 512;
431pub const ALERT_HANDLER_ALERT_EN_SHADOWED_57_REG_RESVAL: u32 = 0;
432pub const ALERT_HANDLER_ALERT_EN_SHADOWED_57_EN_A_57_BIT: u32 = 0;
433pub const ALERT_HANDLER_ALERT_EN_SHADOWED_58_REG_OFFSET: u32 = 516;
434pub const ALERT_HANDLER_ALERT_EN_SHADOWED_58_REG_RESVAL: u32 = 0;
435pub const ALERT_HANDLER_ALERT_EN_SHADOWED_58_EN_A_58_BIT: u32 = 0;
436pub const ALERT_HANDLER_ALERT_EN_SHADOWED_59_REG_OFFSET: u32 = 520;
437pub const ALERT_HANDLER_ALERT_EN_SHADOWED_59_REG_RESVAL: u32 = 0;
438pub const ALERT_HANDLER_ALERT_EN_SHADOWED_59_EN_A_59_BIT: u32 = 0;
439pub const ALERT_HANDLER_ALERT_EN_SHADOWED_60_REG_OFFSET: u32 = 524;
440pub const ALERT_HANDLER_ALERT_EN_SHADOWED_60_REG_RESVAL: u32 = 0;
441pub const ALERT_HANDLER_ALERT_EN_SHADOWED_60_EN_A_60_BIT: u32 = 0;
442pub const ALERT_HANDLER_ALERT_EN_SHADOWED_61_REG_OFFSET: u32 = 528;
443pub const ALERT_HANDLER_ALERT_EN_SHADOWED_61_REG_RESVAL: u32 = 0;
444pub const ALERT_HANDLER_ALERT_EN_SHADOWED_61_EN_A_61_BIT: u32 = 0;
445pub const ALERT_HANDLER_ALERT_EN_SHADOWED_62_REG_OFFSET: u32 = 532;
446pub const ALERT_HANDLER_ALERT_EN_SHADOWED_62_REG_RESVAL: u32 = 0;
447pub const ALERT_HANDLER_ALERT_EN_SHADOWED_62_EN_A_62_BIT: u32 = 0;
448pub const ALERT_HANDLER_ALERT_EN_SHADOWED_63_REG_OFFSET: u32 = 536;
449pub const ALERT_HANDLER_ALERT_EN_SHADOWED_63_REG_RESVAL: u32 = 0;
450pub const ALERT_HANDLER_ALERT_EN_SHADOWED_63_EN_A_63_BIT: u32 = 0;
451pub const ALERT_HANDLER_ALERT_EN_SHADOWED_64_REG_OFFSET: u32 = 540;
452pub const ALERT_HANDLER_ALERT_EN_SHADOWED_64_REG_RESVAL: u32 = 0;
453pub const ALERT_HANDLER_ALERT_EN_SHADOWED_64_EN_A_64_BIT: u32 = 0;
454pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_CLASS_A_FIELD_WIDTH: u32 = 2;
455pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_MULTIREG_COUNT: u32 = 65;
456pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET: u32 = 544;
457pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_RESVAL: u32 = 0;
458pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_MASK: u32 = 3;
459pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_OFFSET: u32 = 0;
460pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSA: u32 = 0;
461pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSB: u32 = 1;
462pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSC: u32 = 2;
463pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSD: u32 = 3;
464pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_REG_OFFSET: u32 = 548;
465pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_REG_RESVAL: u32 = 0;
466pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_MASK: u32 = 3;
467pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_OFFSET: u32 = 0;
468pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_REG_OFFSET: u32 = 552;
469pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_REG_RESVAL: u32 = 0;
470pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_MASK: u32 = 3;
471pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_OFFSET: u32 = 0;
472pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_REG_OFFSET: u32 = 556;
473pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_REG_RESVAL: u32 = 0;
474pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_MASK: u32 = 3;
475pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_OFFSET: u32 = 0;
476pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_REG_OFFSET: u32 = 560;
477pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_REG_RESVAL: u32 = 0;
478pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_MASK: u32 = 3;
479pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_OFFSET: u32 = 0;
480pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_REG_OFFSET: u32 = 564;
481pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_REG_RESVAL: u32 = 0;
482pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_MASK: u32 = 3;
483pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_OFFSET: u32 = 0;
484pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_REG_OFFSET: u32 = 568;
485pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_REG_RESVAL: u32 = 0;
486pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_MASK: u32 = 3;
487pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_OFFSET: u32 = 0;
488pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_REG_OFFSET: u32 = 572;
489pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_REG_RESVAL: u32 = 0;
490pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_MASK: u32 = 3;
491pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_OFFSET: u32 = 0;
492pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_REG_OFFSET: u32 = 576;
493pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_REG_RESVAL: u32 = 0;
494pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_MASK: u32 = 3;
495pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_OFFSET: u32 = 0;
496pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_REG_OFFSET: u32 = 580;
497pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_REG_RESVAL: u32 = 0;
498pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_MASK: u32 = 3;
499pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_OFFSET: u32 = 0;
500pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_REG_OFFSET: u32 = 584;
501pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_REG_RESVAL: u32 = 0;
502pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_MASK: u32 = 3;
503pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_OFFSET: u32 = 0;
504pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_REG_OFFSET: u32 = 588;
505pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_REG_RESVAL: u32 = 0;
506pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_MASK: u32 = 3;
507pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_OFFSET: u32 = 0;
508pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_REG_OFFSET: u32 = 592;
509pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_REG_RESVAL: u32 = 0;
510pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_MASK: u32 = 3;
511pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_OFFSET: u32 = 0;
512pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_REG_OFFSET: u32 = 596;
513pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_REG_RESVAL: u32 = 0;
514pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_MASK: u32 = 3;
515pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_OFFSET: u32 = 0;
516pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_REG_OFFSET: u32 = 600;
517pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_REG_RESVAL: u32 = 0;
518pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_MASK: u32 = 3;
519pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_OFFSET: u32 = 0;
520pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_REG_OFFSET: u32 = 604;
521pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_REG_RESVAL: u32 = 0;
522pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_MASK: u32 = 3;
523pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_OFFSET: u32 = 0;
524pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_REG_OFFSET: u32 = 608;
525pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_REG_RESVAL: u32 = 0;
526pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_MASK: u32 = 3;
527pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_OFFSET: u32 = 0;
528pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_REG_OFFSET: u32 = 612;
529pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_REG_RESVAL: u32 = 0;
530pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_MASK: u32 = 3;
531pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_OFFSET: u32 = 0;
532pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_REG_OFFSET: u32 = 616;
533pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_REG_RESVAL: u32 = 0;
534pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_MASK: u32 = 3;
535pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_OFFSET: u32 = 0;
536pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_REG_OFFSET: u32 = 620;
537pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_REG_RESVAL: u32 = 0;
538pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_MASK: u32 = 3;
539pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_OFFSET: u32 = 0;
540pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_REG_OFFSET: u32 = 624;
541pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_REG_RESVAL: u32 = 0;
542pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_MASK: u32 = 3;
543pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_OFFSET: u32 = 0;
544pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_REG_OFFSET: u32 = 628;
545pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_REG_RESVAL: u32 = 0;
546pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_MASK: u32 = 3;
547pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_OFFSET: u32 = 0;
548pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_REG_OFFSET: u32 = 632;
549pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_REG_RESVAL: u32 = 0;
550pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_MASK: u32 = 3;
551pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_OFFSET: u32 = 0;
552pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_REG_OFFSET: u32 = 636;
553pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_REG_RESVAL: u32 = 0;
554pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_MASK: u32 = 3;
555pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_OFFSET: u32 = 0;
556pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_REG_OFFSET: u32 = 640;
557pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_REG_RESVAL: u32 = 0;
558pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_MASK: u32 = 3;
559pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_OFFSET: u32 = 0;
560pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_REG_OFFSET: u32 = 644;
561pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_REG_RESVAL: u32 = 0;
562pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_MASK: u32 = 3;
563pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_OFFSET: u32 = 0;
564pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_REG_OFFSET: u32 = 648;
565pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_REG_RESVAL: u32 = 0;
566pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_MASK: u32 = 3;
567pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_OFFSET: u32 = 0;
568pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_REG_OFFSET: u32 = 652;
569pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_REG_RESVAL: u32 = 0;
570pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_MASK: u32 = 3;
571pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_OFFSET: u32 = 0;
572pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_REG_OFFSET: u32 = 656;
573pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_REG_RESVAL: u32 = 0;
574pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_MASK: u32 = 3;
575pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_OFFSET: u32 = 0;
576pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_REG_OFFSET: u32 = 660;
577pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_REG_RESVAL: u32 = 0;
578pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_MASK: u32 = 3;
579pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_OFFSET: u32 = 0;
580pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_REG_OFFSET: u32 = 664;
581pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_REG_RESVAL: u32 = 0;
582pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_MASK: u32 = 3;
583pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_OFFSET: u32 = 0;
584pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_REG_OFFSET: u32 = 668;
585pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_REG_RESVAL: u32 = 0;
586pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_MASK: u32 = 3;
587pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_OFFSET: u32 = 0;
588pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_REG_OFFSET: u32 = 672;
589pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_REG_RESVAL: u32 = 0;
590pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_MASK: u32 = 3;
591pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_OFFSET: u32 = 0;
592pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_REG_OFFSET: u32 = 676;
593pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_REG_RESVAL: u32 = 0;
594pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_MASK: u32 = 3;
595pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_OFFSET: u32 = 0;
596pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_REG_OFFSET: u32 = 680;
597pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_REG_RESVAL: u32 = 0;
598pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_MASK: u32 = 3;
599pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_OFFSET: u32 = 0;
600pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_REG_OFFSET: u32 = 684;
601pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_REG_RESVAL: u32 = 0;
602pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_MASK: u32 = 3;
603pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_OFFSET: u32 = 0;
604pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_REG_OFFSET: u32 = 688;
605pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_REG_RESVAL: u32 = 0;
606pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_MASK: u32 = 3;
607pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_OFFSET: u32 = 0;
608pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_REG_OFFSET: u32 = 692;
609pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_REG_RESVAL: u32 = 0;
610pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_MASK: u32 = 3;
611pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_OFFSET: u32 = 0;
612pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_REG_OFFSET: u32 = 696;
613pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_REG_RESVAL: u32 = 0;
614pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_MASK: u32 = 3;
615pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_OFFSET: u32 = 0;
616pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_REG_OFFSET: u32 = 700;
617pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_REG_RESVAL: u32 = 0;
618pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_MASK: u32 = 3;
619pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_OFFSET: u32 = 0;
620pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_REG_OFFSET: u32 = 704;
621pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_REG_RESVAL: u32 = 0;
622pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_MASK: u32 = 3;
623pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_OFFSET: u32 = 0;
624pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_REG_OFFSET: u32 = 708;
625pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_REG_RESVAL: u32 = 0;
626pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_MASK: u32 = 3;
627pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_OFFSET: u32 = 0;
628pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_REG_OFFSET: u32 = 712;
629pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_REG_RESVAL: u32 = 0;
630pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_MASK: u32 = 3;
631pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_OFFSET: u32 = 0;
632pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_REG_OFFSET: u32 = 716;
633pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_REG_RESVAL: u32 = 0;
634pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_MASK: u32 = 3;
635pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_OFFSET: u32 = 0;
636pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_REG_OFFSET: u32 = 720;
637pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_REG_RESVAL: u32 = 0;
638pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_MASK: u32 = 3;
639pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_OFFSET: u32 = 0;
640pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_REG_OFFSET: u32 = 724;
641pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_REG_RESVAL: u32 = 0;
642pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_MASK: u32 = 3;
643pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_OFFSET: u32 = 0;
644pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_REG_OFFSET: u32 = 728;
645pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_REG_RESVAL: u32 = 0;
646pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_MASK: u32 = 3;
647pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_OFFSET: u32 = 0;
648pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_REG_OFFSET: u32 = 732;
649pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_REG_RESVAL: u32 = 0;
650pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_MASK: u32 = 3;
651pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_OFFSET: u32 = 0;
652pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_REG_OFFSET: u32 = 736;
653pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_REG_RESVAL: u32 = 0;
654pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_MASK: u32 = 3;
655pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_OFFSET: u32 = 0;
656pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_REG_OFFSET: u32 = 740;
657pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_REG_RESVAL: u32 = 0;
658pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_MASK: u32 = 3;
659pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_OFFSET: u32 = 0;
660pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_REG_OFFSET: u32 = 744;
661pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_REG_RESVAL: u32 = 0;
662pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_MASK: u32 = 3;
663pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_OFFSET: u32 = 0;
664pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_REG_OFFSET: u32 = 748;
665pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_REG_RESVAL: u32 = 0;
666pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_MASK: u32 = 3;
667pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_OFFSET: u32 = 0;
668pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_REG_OFFSET: u32 = 752;
669pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_REG_RESVAL: u32 = 0;
670pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_MASK: u32 = 3;
671pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_OFFSET: u32 = 0;
672pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_REG_OFFSET: u32 = 756;
673pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_REG_RESVAL: u32 = 0;
674pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_MASK: u32 = 3;
675pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_OFFSET: u32 = 0;
676pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_REG_OFFSET: u32 = 760;
677pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_REG_RESVAL: u32 = 0;
678pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_MASK: u32 = 3;
679pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_OFFSET: u32 = 0;
680pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_REG_OFFSET: u32 = 764;
681pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_REG_RESVAL: u32 = 0;
682pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_MASK: u32 = 3;
683pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_OFFSET: u32 = 0;
684pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_REG_OFFSET: u32 = 768;
685pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_REG_RESVAL: u32 = 0;
686pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_MASK: u32 = 3;
687pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_OFFSET: u32 = 0;
688pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_REG_OFFSET: u32 = 772;
689pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_REG_RESVAL: u32 = 0;
690pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_MASK: u32 = 3;
691pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_OFFSET: u32 = 0;
692pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_REG_OFFSET: u32 = 776;
693pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_REG_RESVAL: u32 = 0;
694pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_MASK: u32 = 3;
695pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_OFFSET: u32 = 0;
696pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_REG_OFFSET: u32 = 780;
697pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_REG_RESVAL: u32 = 0;
698pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_MASK: u32 = 3;
699pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_OFFSET: u32 = 0;
700pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_REG_OFFSET: u32 = 784;
701pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_REG_RESVAL: u32 = 0;
702pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_MASK: u32 = 3;
703pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_OFFSET: u32 = 0;
704pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_REG_OFFSET: u32 = 788;
705pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_REG_RESVAL: u32 = 0;
706pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_MASK: u32 = 3;
707pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_OFFSET: u32 = 0;
708pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_REG_OFFSET: u32 = 792;
709pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_REG_RESVAL: u32 = 0;
710pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_MASK: u32 = 3;
711pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_OFFSET: u32 = 0;
712pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_REG_OFFSET: u32 = 796;
713pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_REG_RESVAL: u32 = 0;
714pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_MASK: u32 = 3;
715pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_OFFSET: u32 = 0;
716pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_REG_OFFSET: u32 = 800;
717pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_REG_RESVAL: u32 = 0;
718pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_MASK: u32 = 3;
719pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_OFFSET: u32 = 0;
720pub const ALERT_HANDLER_ALERT_CAUSE_A_FIELD_WIDTH: u32 = 1;
721pub const ALERT_HANDLER_ALERT_CAUSE_MULTIREG_COUNT: u32 = 65;
722pub const ALERT_HANDLER_ALERT_CAUSE_0_REG_OFFSET: u32 = 804;
723pub const ALERT_HANDLER_ALERT_CAUSE_0_REG_RESVAL: u32 = 0;
724pub const ALERT_HANDLER_ALERT_CAUSE_0_A_0_BIT: u32 = 0;
725pub const ALERT_HANDLER_ALERT_CAUSE_1_REG_OFFSET: u32 = 808;
726pub const ALERT_HANDLER_ALERT_CAUSE_1_REG_RESVAL: u32 = 0;
727pub const ALERT_HANDLER_ALERT_CAUSE_1_A_1_BIT: u32 = 0;
728pub const ALERT_HANDLER_ALERT_CAUSE_2_REG_OFFSET: u32 = 812;
729pub const ALERT_HANDLER_ALERT_CAUSE_2_REG_RESVAL: u32 = 0;
730pub const ALERT_HANDLER_ALERT_CAUSE_2_A_2_BIT: u32 = 0;
731pub const ALERT_HANDLER_ALERT_CAUSE_3_REG_OFFSET: u32 = 816;
732pub const ALERT_HANDLER_ALERT_CAUSE_3_REG_RESVAL: u32 = 0;
733pub const ALERT_HANDLER_ALERT_CAUSE_3_A_3_BIT: u32 = 0;
734pub const ALERT_HANDLER_ALERT_CAUSE_4_REG_OFFSET: u32 = 820;
735pub const ALERT_HANDLER_ALERT_CAUSE_4_REG_RESVAL: u32 = 0;
736pub const ALERT_HANDLER_ALERT_CAUSE_4_A_4_BIT: u32 = 0;
737pub const ALERT_HANDLER_ALERT_CAUSE_5_REG_OFFSET: u32 = 824;
738pub const ALERT_HANDLER_ALERT_CAUSE_5_REG_RESVAL: u32 = 0;
739pub const ALERT_HANDLER_ALERT_CAUSE_5_A_5_BIT: u32 = 0;
740pub const ALERT_HANDLER_ALERT_CAUSE_6_REG_OFFSET: u32 = 828;
741pub const ALERT_HANDLER_ALERT_CAUSE_6_REG_RESVAL: u32 = 0;
742pub const ALERT_HANDLER_ALERT_CAUSE_6_A_6_BIT: u32 = 0;
743pub const ALERT_HANDLER_ALERT_CAUSE_7_REG_OFFSET: u32 = 832;
744pub const ALERT_HANDLER_ALERT_CAUSE_7_REG_RESVAL: u32 = 0;
745pub const ALERT_HANDLER_ALERT_CAUSE_7_A_7_BIT: u32 = 0;
746pub const ALERT_HANDLER_ALERT_CAUSE_8_REG_OFFSET: u32 = 836;
747pub const ALERT_HANDLER_ALERT_CAUSE_8_REG_RESVAL: u32 = 0;
748pub const ALERT_HANDLER_ALERT_CAUSE_8_A_8_BIT: u32 = 0;
749pub const ALERT_HANDLER_ALERT_CAUSE_9_REG_OFFSET: u32 = 840;
750pub const ALERT_HANDLER_ALERT_CAUSE_9_REG_RESVAL: u32 = 0;
751pub const ALERT_HANDLER_ALERT_CAUSE_9_A_9_BIT: u32 = 0;
752pub const ALERT_HANDLER_ALERT_CAUSE_10_REG_OFFSET: u32 = 844;
753pub const ALERT_HANDLER_ALERT_CAUSE_10_REG_RESVAL: u32 = 0;
754pub const ALERT_HANDLER_ALERT_CAUSE_10_A_10_BIT: u32 = 0;
755pub const ALERT_HANDLER_ALERT_CAUSE_11_REG_OFFSET: u32 = 848;
756pub const ALERT_HANDLER_ALERT_CAUSE_11_REG_RESVAL: u32 = 0;
757pub const ALERT_HANDLER_ALERT_CAUSE_11_A_11_BIT: u32 = 0;
758pub const ALERT_HANDLER_ALERT_CAUSE_12_REG_OFFSET: u32 = 852;
759pub const ALERT_HANDLER_ALERT_CAUSE_12_REG_RESVAL: u32 = 0;
760pub const ALERT_HANDLER_ALERT_CAUSE_12_A_12_BIT: u32 = 0;
761pub const ALERT_HANDLER_ALERT_CAUSE_13_REG_OFFSET: u32 = 856;
762pub const ALERT_HANDLER_ALERT_CAUSE_13_REG_RESVAL: u32 = 0;
763pub const ALERT_HANDLER_ALERT_CAUSE_13_A_13_BIT: u32 = 0;
764pub const ALERT_HANDLER_ALERT_CAUSE_14_REG_OFFSET: u32 = 860;
765pub const ALERT_HANDLER_ALERT_CAUSE_14_REG_RESVAL: u32 = 0;
766pub const ALERT_HANDLER_ALERT_CAUSE_14_A_14_BIT: u32 = 0;
767pub const ALERT_HANDLER_ALERT_CAUSE_15_REG_OFFSET: u32 = 864;
768pub const ALERT_HANDLER_ALERT_CAUSE_15_REG_RESVAL: u32 = 0;
769pub const ALERT_HANDLER_ALERT_CAUSE_15_A_15_BIT: u32 = 0;
770pub const ALERT_HANDLER_ALERT_CAUSE_16_REG_OFFSET: u32 = 868;
771pub const ALERT_HANDLER_ALERT_CAUSE_16_REG_RESVAL: u32 = 0;
772pub const ALERT_HANDLER_ALERT_CAUSE_16_A_16_BIT: u32 = 0;
773pub const ALERT_HANDLER_ALERT_CAUSE_17_REG_OFFSET: u32 = 872;
774pub const ALERT_HANDLER_ALERT_CAUSE_17_REG_RESVAL: u32 = 0;
775pub const ALERT_HANDLER_ALERT_CAUSE_17_A_17_BIT: u32 = 0;
776pub const ALERT_HANDLER_ALERT_CAUSE_18_REG_OFFSET: u32 = 876;
777pub const ALERT_HANDLER_ALERT_CAUSE_18_REG_RESVAL: u32 = 0;
778pub const ALERT_HANDLER_ALERT_CAUSE_18_A_18_BIT: u32 = 0;
779pub const ALERT_HANDLER_ALERT_CAUSE_19_REG_OFFSET: u32 = 880;
780pub const ALERT_HANDLER_ALERT_CAUSE_19_REG_RESVAL: u32 = 0;
781pub const ALERT_HANDLER_ALERT_CAUSE_19_A_19_BIT: u32 = 0;
782pub const ALERT_HANDLER_ALERT_CAUSE_20_REG_OFFSET: u32 = 884;
783pub const ALERT_HANDLER_ALERT_CAUSE_20_REG_RESVAL: u32 = 0;
784pub const ALERT_HANDLER_ALERT_CAUSE_20_A_20_BIT: u32 = 0;
785pub const ALERT_HANDLER_ALERT_CAUSE_21_REG_OFFSET: u32 = 888;
786pub const ALERT_HANDLER_ALERT_CAUSE_21_REG_RESVAL: u32 = 0;
787pub const ALERT_HANDLER_ALERT_CAUSE_21_A_21_BIT: u32 = 0;
788pub const ALERT_HANDLER_ALERT_CAUSE_22_REG_OFFSET: u32 = 892;
789pub const ALERT_HANDLER_ALERT_CAUSE_22_REG_RESVAL: u32 = 0;
790pub const ALERT_HANDLER_ALERT_CAUSE_22_A_22_BIT: u32 = 0;
791pub const ALERT_HANDLER_ALERT_CAUSE_23_REG_OFFSET: u32 = 896;
792pub const ALERT_HANDLER_ALERT_CAUSE_23_REG_RESVAL: u32 = 0;
793pub const ALERT_HANDLER_ALERT_CAUSE_23_A_23_BIT: u32 = 0;
794pub const ALERT_HANDLER_ALERT_CAUSE_24_REG_OFFSET: u32 = 900;
795pub const ALERT_HANDLER_ALERT_CAUSE_24_REG_RESVAL: u32 = 0;
796pub const ALERT_HANDLER_ALERT_CAUSE_24_A_24_BIT: u32 = 0;
797pub const ALERT_HANDLER_ALERT_CAUSE_25_REG_OFFSET: u32 = 904;
798pub const ALERT_HANDLER_ALERT_CAUSE_25_REG_RESVAL: u32 = 0;
799pub const ALERT_HANDLER_ALERT_CAUSE_25_A_25_BIT: u32 = 0;
800pub const ALERT_HANDLER_ALERT_CAUSE_26_REG_OFFSET: u32 = 908;
801pub const ALERT_HANDLER_ALERT_CAUSE_26_REG_RESVAL: u32 = 0;
802pub const ALERT_HANDLER_ALERT_CAUSE_26_A_26_BIT: u32 = 0;
803pub const ALERT_HANDLER_ALERT_CAUSE_27_REG_OFFSET: u32 = 912;
804pub const ALERT_HANDLER_ALERT_CAUSE_27_REG_RESVAL: u32 = 0;
805pub const ALERT_HANDLER_ALERT_CAUSE_27_A_27_BIT: u32 = 0;
806pub const ALERT_HANDLER_ALERT_CAUSE_28_REG_OFFSET: u32 = 916;
807pub const ALERT_HANDLER_ALERT_CAUSE_28_REG_RESVAL: u32 = 0;
808pub const ALERT_HANDLER_ALERT_CAUSE_28_A_28_BIT: u32 = 0;
809pub const ALERT_HANDLER_ALERT_CAUSE_29_REG_OFFSET: u32 = 920;
810pub const ALERT_HANDLER_ALERT_CAUSE_29_REG_RESVAL: u32 = 0;
811pub const ALERT_HANDLER_ALERT_CAUSE_29_A_29_BIT: u32 = 0;
812pub const ALERT_HANDLER_ALERT_CAUSE_30_REG_OFFSET: u32 = 924;
813pub const ALERT_HANDLER_ALERT_CAUSE_30_REG_RESVAL: u32 = 0;
814pub const ALERT_HANDLER_ALERT_CAUSE_30_A_30_BIT: u32 = 0;
815pub const ALERT_HANDLER_ALERT_CAUSE_31_REG_OFFSET: u32 = 928;
816pub const ALERT_HANDLER_ALERT_CAUSE_31_REG_RESVAL: u32 = 0;
817pub const ALERT_HANDLER_ALERT_CAUSE_31_A_31_BIT: u32 = 0;
818pub const ALERT_HANDLER_ALERT_CAUSE_32_REG_OFFSET: u32 = 932;
819pub const ALERT_HANDLER_ALERT_CAUSE_32_REG_RESVAL: u32 = 0;
820pub const ALERT_HANDLER_ALERT_CAUSE_32_A_32_BIT: u32 = 0;
821pub const ALERT_HANDLER_ALERT_CAUSE_33_REG_OFFSET: u32 = 936;
822pub const ALERT_HANDLER_ALERT_CAUSE_33_REG_RESVAL: u32 = 0;
823pub const ALERT_HANDLER_ALERT_CAUSE_33_A_33_BIT: u32 = 0;
824pub const ALERT_HANDLER_ALERT_CAUSE_34_REG_OFFSET: u32 = 940;
825pub const ALERT_HANDLER_ALERT_CAUSE_34_REG_RESVAL: u32 = 0;
826pub const ALERT_HANDLER_ALERT_CAUSE_34_A_34_BIT: u32 = 0;
827pub const ALERT_HANDLER_ALERT_CAUSE_35_REG_OFFSET: u32 = 944;
828pub const ALERT_HANDLER_ALERT_CAUSE_35_REG_RESVAL: u32 = 0;
829pub const ALERT_HANDLER_ALERT_CAUSE_35_A_35_BIT: u32 = 0;
830pub const ALERT_HANDLER_ALERT_CAUSE_36_REG_OFFSET: u32 = 948;
831pub const ALERT_HANDLER_ALERT_CAUSE_36_REG_RESVAL: u32 = 0;
832pub const ALERT_HANDLER_ALERT_CAUSE_36_A_36_BIT: u32 = 0;
833pub const ALERT_HANDLER_ALERT_CAUSE_37_REG_OFFSET: u32 = 952;
834pub const ALERT_HANDLER_ALERT_CAUSE_37_REG_RESVAL: u32 = 0;
835pub const ALERT_HANDLER_ALERT_CAUSE_37_A_37_BIT: u32 = 0;
836pub const ALERT_HANDLER_ALERT_CAUSE_38_REG_OFFSET: u32 = 956;
837pub const ALERT_HANDLER_ALERT_CAUSE_38_REG_RESVAL: u32 = 0;
838pub const ALERT_HANDLER_ALERT_CAUSE_38_A_38_BIT: u32 = 0;
839pub const ALERT_HANDLER_ALERT_CAUSE_39_REG_OFFSET: u32 = 960;
840pub const ALERT_HANDLER_ALERT_CAUSE_39_REG_RESVAL: u32 = 0;
841pub const ALERT_HANDLER_ALERT_CAUSE_39_A_39_BIT: u32 = 0;
842pub const ALERT_HANDLER_ALERT_CAUSE_40_REG_OFFSET: u32 = 964;
843pub const ALERT_HANDLER_ALERT_CAUSE_40_REG_RESVAL: u32 = 0;
844pub const ALERT_HANDLER_ALERT_CAUSE_40_A_40_BIT: u32 = 0;
845pub const ALERT_HANDLER_ALERT_CAUSE_41_REG_OFFSET: u32 = 968;
846pub const ALERT_HANDLER_ALERT_CAUSE_41_REG_RESVAL: u32 = 0;
847pub const ALERT_HANDLER_ALERT_CAUSE_41_A_41_BIT: u32 = 0;
848pub const ALERT_HANDLER_ALERT_CAUSE_42_REG_OFFSET: u32 = 972;
849pub const ALERT_HANDLER_ALERT_CAUSE_42_REG_RESVAL: u32 = 0;
850pub const ALERT_HANDLER_ALERT_CAUSE_42_A_42_BIT: u32 = 0;
851pub const ALERT_HANDLER_ALERT_CAUSE_43_REG_OFFSET: u32 = 976;
852pub const ALERT_HANDLER_ALERT_CAUSE_43_REG_RESVAL: u32 = 0;
853pub const ALERT_HANDLER_ALERT_CAUSE_43_A_43_BIT: u32 = 0;
854pub const ALERT_HANDLER_ALERT_CAUSE_44_REG_OFFSET: u32 = 980;
855pub const ALERT_HANDLER_ALERT_CAUSE_44_REG_RESVAL: u32 = 0;
856pub const ALERT_HANDLER_ALERT_CAUSE_44_A_44_BIT: u32 = 0;
857pub const ALERT_HANDLER_ALERT_CAUSE_45_REG_OFFSET: u32 = 984;
858pub const ALERT_HANDLER_ALERT_CAUSE_45_REG_RESVAL: u32 = 0;
859pub const ALERT_HANDLER_ALERT_CAUSE_45_A_45_BIT: u32 = 0;
860pub const ALERT_HANDLER_ALERT_CAUSE_46_REG_OFFSET: u32 = 988;
861pub const ALERT_HANDLER_ALERT_CAUSE_46_REG_RESVAL: u32 = 0;
862pub const ALERT_HANDLER_ALERT_CAUSE_46_A_46_BIT: u32 = 0;
863pub const ALERT_HANDLER_ALERT_CAUSE_47_REG_OFFSET: u32 = 992;
864pub const ALERT_HANDLER_ALERT_CAUSE_47_REG_RESVAL: u32 = 0;
865pub const ALERT_HANDLER_ALERT_CAUSE_47_A_47_BIT: u32 = 0;
866pub const ALERT_HANDLER_ALERT_CAUSE_48_REG_OFFSET: u32 = 996;
867pub const ALERT_HANDLER_ALERT_CAUSE_48_REG_RESVAL: u32 = 0;
868pub const ALERT_HANDLER_ALERT_CAUSE_48_A_48_BIT: u32 = 0;
869pub const ALERT_HANDLER_ALERT_CAUSE_49_REG_OFFSET: u32 = 1000;
870pub const ALERT_HANDLER_ALERT_CAUSE_49_REG_RESVAL: u32 = 0;
871pub const ALERT_HANDLER_ALERT_CAUSE_49_A_49_BIT: u32 = 0;
872pub const ALERT_HANDLER_ALERT_CAUSE_50_REG_OFFSET: u32 = 1004;
873pub const ALERT_HANDLER_ALERT_CAUSE_50_REG_RESVAL: u32 = 0;
874pub const ALERT_HANDLER_ALERT_CAUSE_50_A_50_BIT: u32 = 0;
875pub const ALERT_HANDLER_ALERT_CAUSE_51_REG_OFFSET: u32 = 1008;
876pub const ALERT_HANDLER_ALERT_CAUSE_51_REG_RESVAL: u32 = 0;
877pub const ALERT_HANDLER_ALERT_CAUSE_51_A_51_BIT: u32 = 0;
878pub const ALERT_HANDLER_ALERT_CAUSE_52_REG_OFFSET: u32 = 1012;
879pub const ALERT_HANDLER_ALERT_CAUSE_52_REG_RESVAL: u32 = 0;
880pub const ALERT_HANDLER_ALERT_CAUSE_52_A_52_BIT: u32 = 0;
881pub const ALERT_HANDLER_ALERT_CAUSE_53_REG_OFFSET: u32 = 1016;
882pub const ALERT_HANDLER_ALERT_CAUSE_53_REG_RESVAL: u32 = 0;
883pub const ALERT_HANDLER_ALERT_CAUSE_53_A_53_BIT: u32 = 0;
884pub const ALERT_HANDLER_ALERT_CAUSE_54_REG_OFFSET: u32 = 1020;
885pub const ALERT_HANDLER_ALERT_CAUSE_54_REG_RESVAL: u32 = 0;
886pub const ALERT_HANDLER_ALERT_CAUSE_54_A_54_BIT: u32 = 0;
887pub const ALERT_HANDLER_ALERT_CAUSE_55_REG_OFFSET: u32 = 1024;
888pub const ALERT_HANDLER_ALERT_CAUSE_55_REG_RESVAL: u32 = 0;
889pub const ALERT_HANDLER_ALERT_CAUSE_55_A_55_BIT: u32 = 0;
890pub const ALERT_HANDLER_ALERT_CAUSE_56_REG_OFFSET: u32 = 1028;
891pub const ALERT_HANDLER_ALERT_CAUSE_56_REG_RESVAL: u32 = 0;
892pub const ALERT_HANDLER_ALERT_CAUSE_56_A_56_BIT: u32 = 0;
893pub const ALERT_HANDLER_ALERT_CAUSE_57_REG_OFFSET: u32 = 1032;
894pub const ALERT_HANDLER_ALERT_CAUSE_57_REG_RESVAL: u32 = 0;
895pub const ALERT_HANDLER_ALERT_CAUSE_57_A_57_BIT: u32 = 0;
896pub const ALERT_HANDLER_ALERT_CAUSE_58_REG_OFFSET: u32 = 1036;
897pub const ALERT_HANDLER_ALERT_CAUSE_58_REG_RESVAL: u32 = 0;
898pub const ALERT_HANDLER_ALERT_CAUSE_58_A_58_BIT: u32 = 0;
899pub const ALERT_HANDLER_ALERT_CAUSE_59_REG_OFFSET: u32 = 1040;
900pub const ALERT_HANDLER_ALERT_CAUSE_59_REG_RESVAL: u32 = 0;
901pub const ALERT_HANDLER_ALERT_CAUSE_59_A_59_BIT: u32 = 0;
902pub const ALERT_HANDLER_ALERT_CAUSE_60_REG_OFFSET: u32 = 1044;
903pub const ALERT_HANDLER_ALERT_CAUSE_60_REG_RESVAL: u32 = 0;
904pub const ALERT_HANDLER_ALERT_CAUSE_60_A_60_BIT: u32 = 0;
905pub const ALERT_HANDLER_ALERT_CAUSE_61_REG_OFFSET: u32 = 1048;
906pub const ALERT_HANDLER_ALERT_CAUSE_61_REG_RESVAL: u32 = 0;
907pub const ALERT_HANDLER_ALERT_CAUSE_61_A_61_BIT: u32 = 0;
908pub const ALERT_HANDLER_ALERT_CAUSE_62_REG_OFFSET: u32 = 1052;
909pub const ALERT_HANDLER_ALERT_CAUSE_62_REG_RESVAL: u32 = 0;
910pub const ALERT_HANDLER_ALERT_CAUSE_62_A_62_BIT: u32 = 0;
911pub const ALERT_HANDLER_ALERT_CAUSE_63_REG_OFFSET: u32 = 1056;
912pub const ALERT_HANDLER_ALERT_CAUSE_63_REG_RESVAL: u32 = 0;
913pub const ALERT_HANDLER_ALERT_CAUSE_63_A_63_BIT: u32 = 0;
914pub const ALERT_HANDLER_ALERT_CAUSE_64_REG_OFFSET: u32 = 1060;
915pub const ALERT_HANDLER_ALERT_CAUSE_64_REG_RESVAL: u32 = 0;
916pub const ALERT_HANDLER_ALERT_CAUSE_64_A_64_BIT: u32 = 0;
917pub const ALERT_HANDLER_LOC_ALERT_REGWEN_EN_FIELD_WIDTH: u32 = 1;
918pub const ALERT_HANDLER_LOC_ALERT_REGWEN_MULTIREG_COUNT: u32 = 7;
919pub const ALERT_HANDLER_LOC_ALERT_REGWEN_0_REG_OFFSET: u32 = 1064;
920pub const ALERT_HANDLER_LOC_ALERT_REGWEN_0_REG_RESVAL: u32 = 1;
921pub const ALERT_HANDLER_LOC_ALERT_REGWEN_0_EN_0_BIT: u32 = 0;
922pub const ALERT_HANDLER_LOC_ALERT_REGWEN_1_REG_OFFSET: u32 = 1068;
923pub const ALERT_HANDLER_LOC_ALERT_REGWEN_1_REG_RESVAL: u32 = 1;
924pub const ALERT_HANDLER_LOC_ALERT_REGWEN_1_EN_1_BIT: u32 = 0;
925pub const ALERT_HANDLER_LOC_ALERT_REGWEN_2_REG_OFFSET: u32 = 1072;
926pub const ALERT_HANDLER_LOC_ALERT_REGWEN_2_REG_RESVAL: u32 = 1;
927pub const ALERT_HANDLER_LOC_ALERT_REGWEN_2_EN_2_BIT: u32 = 0;
928pub const ALERT_HANDLER_LOC_ALERT_REGWEN_3_REG_OFFSET: u32 = 1076;
929pub const ALERT_HANDLER_LOC_ALERT_REGWEN_3_REG_RESVAL: u32 = 1;
930pub const ALERT_HANDLER_LOC_ALERT_REGWEN_3_EN_3_BIT: u32 = 0;
931pub const ALERT_HANDLER_LOC_ALERT_REGWEN_4_REG_OFFSET: u32 = 1080;
932pub const ALERT_HANDLER_LOC_ALERT_REGWEN_4_REG_RESVAL: u32 = 1;
933pub const ALERT_HANDLER_LOC_ALERT_REGWEN_4_EN_4_BIT: u32 = 0;
934pub const ALERT_HANDLER_LOC_ALERT_REGWEN_5_REG_OFFSET: u32 = 1084;
935pub const ALERT_HANDLER_LOC_ALERT_REGWEN_5_REG_RESVAL: u32 = 1;
936pub const ALERT_HANDLER_LOC_ALERT_REGWEN_5_EN_5_BIT: u32 = 0;
937pub const ALERT_HANDLER_LOC_ALERT_REGWEN_6_REG_OFFSET: u32 = 1088;
938pub const ALERT_HANDLER_LOC_ALERT_REGWEN_6_REG_RESVAL: u32 = 1;
939pub const ALERT_HANDLER_LOC_ALERT_REGWEN_6_EN_6_BIT: u32 = 0;
940pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_EN_LA_FIELD_WIDTH: u32 = 1;
941pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_MULTIREG_COUNT: u32 = 7;
942pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_OFFSET: u32 = 1092;
943pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_RESVAL: u32 = 0;
944pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_EN_LA_0_BIT: u32 = 0;
945pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_REG_OFFSET: u32 = 1096;
946pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_REG_RESVAL: u32 = 0;
947pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_EN_LA_1_BIT: u32 = 0;
948pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_REG_OFFSET: u32 = 1100;
949pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_REG_RESVAL: u32 = 0;
950pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_EN_LA_2_BIT: u32 = 0;
951pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_REG_OFFSET: u32 = 1104;
952pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_REG_RESVAL: u32 = 0;
953pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_EN_LA_3_BIT: u32 = 0;
954pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_REG_OFFSET: u32 = 1108;
955pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_REG_RESVAL: u32 = 0;
956pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_EN_LA_4_BIT: u32 = 0;
957pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_REG_OFFSET: u32 = 1112;
958pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_REG_RESVAL: u32 = 0;
959pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_EN_LA_5_BIT: u32 = 0;
960pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_REG_OFFSET: u32 = 1116;
961pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_REG_RESVAL: u32 = 0;
962pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_EN_LA_6_BIT: u32 = 0;
963pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_CLASS_LA_FIELD_WIDTH: u32 = 2;
964pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_MULTIREG_COUNT: u32 = 7;
965pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_OFFSET: u32 = 1120;
966pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_RESVAL: u32 = 0;
967pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_MASK: u32 = 3;
968pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_OFFSET: u32 = 0;
969pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSA: u32 = 0;
970pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSB: u32 = 1;
971pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSC: u32 = 2;
972pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSD: u32 = 3;
973pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_REG_OFFSET: u32 = 1124;
974pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_REG_RESVAL: u32 = 0;
975pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_MASK: u32 = 3;
976pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_OFFSET: u32 = 0;
977pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_REG_OFFSET: u32 = 1128;
978pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_REG_RESVAL: u32 = 0;
979pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_MASK: u32 = 3;
980pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_OFFSET: u32 = 0;
981pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_REG_OFFSET: u32 = 1132;
982pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_REG_RESVAL: u32 = 0;
983pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_MASK: u32 = 3;
984pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_OFFSET: u32 = 0;
985pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_REG_OFFSET: u32 = 1136;
986pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_REG_RESVAL: u32 = 0;
987pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_MASK: u32 = 3;
988pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_OFFSET: u32 = 0;
989pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_REG_OFFSET: u32 = 1140;
990pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_REG_RESVAL: u32 = 0;
991pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_MASK: u32 = 3;
992pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_OFFSET: u32 = 0;
993pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_REG_OFFSET: u32 = 1144;
994pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_REG_RESVAL: u32 = 0;
995pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_MASK: u32 = 3;
996pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_OFFSET: u32 = 0;
997pub const ALERT_HANDLER_LOC_ALERT_CAUSE_LA_FIELD_WIDTH: u32 = 1;
998pub const ALERT_HANDLER_LOC_ALERT_CAUSE_MULTIREG_COUNT: u32 = 7;
999pub const ALERT_HANDLER_LOC_ALERT_CAUSE_0_REG_OFFSET: u32 = 1148;
1000pub const ALERT_HANDLER_LOC_ALERT_CAUSE_0_REG_RESVAL: u32 = 0;
1001pub const ALERT_HANDLER_LOC_ALERT_CAUSE_0_LA_0_BIT: u32 = 0;
1002pub const ALERT_HANDLER_LOC_ALERT_CAUSE_1_REG_OFFSET: u32 = 1152;
1003pub const ALERT_HANDLER_LOC_ALERT_CAUSE_1_REG_RESVAL: u32 = 0;
1004pub const ALERT_HANDLER_LOC_ALERT_CAUSE_1_LA_1_BIT: u32 = 0;
1005pub const ALERT_HANDLER_LOC_ALERT_CAUSE_2_REG_OFFSET: u32 = 1156;
1006pub const ALERT_HANDLER_LOC_ALERT_CAUSE_2_REG_RESVAL: u32 = 0;
1007pub const ALERT_HANDLER_LOC_ALERT_CAUSE_2_LA_2_BIT: u32 = 0;
1008pub const ALERT_HANDLER_LOC_ALERT_CAUSE_3_REG_OFFSET: u32 = 1160;
1009pub const ALERT_HANDLER_LOC_ALERT_CAUSE_3_REG_RESVAL: u32 = 0;
1010pub const ALERT_HANDLER_LOC_ALERT_CAUSE_3_LA_3_BIT: u32 = 0;
1011pub const ALERT_HANDLER_LOC_ALERT_CAUSE_4_REG_OFFSET: u32 = 1164;
1012pub const ALERT_HANDLER_LOC_ALERT_CAUSE_4_REG_RESVAL: u32 = 0;
1013pub const ALERT_HANDLER_LOC_ALERT_CAUSE_4_LA_4_BIT: u32 = 0;
1014pub const ALERT_HANDLER_LOC_ALERT_CAUSE_5_REG_OFFSET: u32 = 1168;
1015pub const ALERT_HANDLER_LOC_ALERT_CAUSE_5_REG_RESVAL: u32 = 0;
1016pub const ALERT_HANDLER_LOC_ALERT_CAUSE_5_LA_5_BIT: u32 = 0;
1017pub const ALERT_HANDLER_LOC_ALERT_CAUSE_6_REG_OFFSET: u32 = 1172;
1018pub const ALERT_HANDLER_LOC_ALERT_CAUSE_6_REG_RESVAL: u32 = 0;
1019pub const ALERT_HANDLER_LOC_ALERT_CAUSE_6_LA_6_BIT: u32 = 0;
1020pub const ALERT_HANDLER_CLASSA_REGWEN_REG_OFFSET: u32 = 1176;
1021pub const ALERT_HANDLER_CLASSA_REGWEN_REG_RESVAL: u32 = 1;
1022pub const ALERT_HANDLER_CLASSA_REGWEN_CLASSA_REGWEN_BIT: u32 = 0;
1023pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_OFFSET: u32 = 1180;
1024pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_RESVAL: u32 = 14652;
1025pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_BIT: u32 = 0;
1026pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_LOCK_BIT: u32 = 1;
1027pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E0_BIT: u32 = 2;
1028pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E1_BIT: u32 = 3;
1029pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E2_BIT: u32 = 4;
1030pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E3_BIT: u32 = 5;
1031pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_MASK: u32 = 3;
1032pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_OFFSET: u32 = 6;
1033pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_MASK: u32 = 3;
1034pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_OFFSET: u32 = 8;
1035pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_MASK: u32 = 3;
1036pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_OFFSET: u32 = 10;
1037pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_MASK: u32 = 3;
1038pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_OFFSET: u32 = 12;
1039pub const ALERT_HANDLER_CLASSA_CLR_REGWEN_REG_OFFSET: u32 = 1184;
1040pub const ALERT_HANDLER_CLASSA_CLR_REGWEN_REG_RESVAL: u32 = 1;
1041pub const ALERT_HANDLER_CLASSA_CLR_REGWEN_CLASSA_CLR_REGWEN_BIT: u32 = 0;
1042pub const ALERT_HANDLER_CLASSA_CLR_SHADOWED_REG_OFFSET: u32 = 1188;
1043pub const ALERT_HANDLER_CLASSA_CLR_SHADOWED_REG_RESVAL: u32 = 0;
1044pub const ALERT_HANDLER_CLASSA_CLR_SHADOWED_CLASSA_CLR_SHADOWED_BIT: u32 = 0;
1045pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_REG_OFFSET: u32 = 1192;
1046pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_REG_RESVAL: u32 = 0;
1047pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_MASK: u32 = 65535;
1048pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_OFFSET: u32 = 0;
1049pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1196;
1050pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_RESVAL: u32 = 0;
1051pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_MASK: u32 = 65535;
1052pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET: u32 = 0;
1053pub const ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1200;
1054pub const ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_RESVAL: u32 = 0;
1055pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1204;
1056pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL: u32 = 0;
1057pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_MASK:
1058    u32 = 3;
1059pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET : u32 = 0 ;
1060pub const ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1208;
1061pub const ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_RESVAL: u32 = 0;
1062pub const ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1212;
1063pub const ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_REG_RESVAL: u32 = 0;
1064pub const ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1216;
1065pub const ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_REG_RESVAL: u32 = 0;
1066pub const ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1220;
1067pub const ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_REG_RESVAL: u32 = 0;
1068pub const ALERT_HANDLER_CLASSA_ESC_CNT_REG_OFFSET: u32 = 1224;
1069pub const ALERT_HANDLER_CLASSA_ESC_CNT_REG_RESVAL: u32 = 0;
1070pub const ALERT_HANDLER_CLASSA_STATE_REG_OFFSET: u32 = 1228;
1071pub const ALERT_HANDLER_CLASSA_STATE_REG_RESVAL: u32 = 0;
1072pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_MASK: u32 = 7;
1073pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_OFFSET: u32 = 0;
1074pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_IDLE: u32 = 0;
1075pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_TIMEOUT: u32 = 1;
1076pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_FSMERROR: u32 = 2;
1077pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_TERMINAL: u32 = 3;
1078pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE0: u32 = 4;
1079pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE1: u32 = 5;
1080pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE2: u32 = 6;
1081pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE3: u32 = 7;
1082pub const ALERT_HANDLER_CLASSB_REGWEN_REG_OFFSET: u32 = 1232;
1083pub const ALERT_HANDLER_CLASSB_REGWEN_REG_RESVAL: u32 = 1;
1084pub const ALERT_HANDLER_CLASSB_REGWEN_CLASSB_REGWEN_BIT: u32 = 0;
1085pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_OFFSET: u32 = 1236;
1086pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_RESVAL: u32 = 14652;
1087pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_BIT: u32 = 0;
1088pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_LOCK_BIT: u32 = 1;
1089pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E0_BIT: u32 = 2;
1090pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E1_BIT: u32 = 3;
1091pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E2_BIT: u32 = 4;
1092pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E3_BIT: u32 = 5;
1093pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E0_MASK: u32 = 3;
1094pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E0_OFFSET: u32 = 6;
1095pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E1_MASK: u32 = 3;
1096pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E1_OFFSET: u32 = 8;
1097pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_MASK: u32 = 3;
1098pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_OFFSET: u32 = 10;
1099pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_MASK: u32 = 3;
1100pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_OFFSET: u32 = 12;
1101pub const ALERT_HANDLER_CLASSB_CLR_REGWEN_REG_OFFSET: u32 = 1240;
1102pub const ALERT_HANDLER_CLASSB_CLR_REGWEN_REG_RESVAL: u32 = 1;
1103pub const ALERT_HANDLER_CLASSB_CLR_REGWEN_CLASSB_CLR_REGWEN_BIT: u32 = 0;
1104pub const ALERT_HANDLER_CLASSB_CLR_SHADOWED_REG_OFFSET: u32 = 1244;
1105pub const ALERT_HANDLER_CLASSB_CLR_SHADOWED_REG_RESVAL: u32 = 0;
1106pub const ALERT_HANDLER_CLASSB_CLR_SHADOWED_CLASSB_CLR_SHADOWED_BIT: u32 = 0;
1107pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_REG_OFFSET: u32 = 1248;
1108pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_REG_RESVAL: u32 = 0;
1109pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_MASK: u32 = 65535;
1110pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_OFFSET: u32 = 0;
1111pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1252;
1112pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_REG_RESVAL: u32 = 0;
1113pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_MASK: u32 = 65535;
1114pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET: u32 = 0;
1115pub const ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1256;
1116pub const ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_REG_RESVAL: u32 = 0;
1117pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1260;
1118pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL: u32 = 0;
1119pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_MASK:
1120    u32 = 3;
1121pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET : u32 = 0 ;
1122pub const ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1264;
1123pub const ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_REG_RESVAL: u32 = 0;
1124pub const ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1268;
1125pub const ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_REG_RESVAL: u32 = 0;
1126pub const ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1272;
1127pub const ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_REG_RESVAL: u32 = 0;
1128pub const ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1276;
1129pub const ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_REG_RESVAL: u32 = 0;
1130pub const ALERT_HANDLER_CLASSB_ESC_CNT_REG_OFFSET: u32 = 1280;
1131pub const ALERT_HANDLER_CLASSB_ESC_CNT_REG_RESVAL: u32 = 0;
1132pub const ALERT_HANDLER_CLASSB_STATE_REG_OFFSET: u32 = 1284;
1133pub const ALERT_HANDLER_CLASSB_STATE_REG_RESVAL: u32 = 0;
1134pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_MASK: u32 = 7;
1135pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_OFFSET: u32 = 0;
1136pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_IDLE: u32 = 0;
1137pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_TIMEOUT: u32 = 1;
1138pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_FSMERROR: u32 = 2;
1139pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_TERMINAL: u32 = 3;
1140pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE0: u32 = 4;
1141pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE1: u32 = 5;
1142pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE2: u32 = 6;
1143pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE3: u32 = 7;
1144pub const ALERT_HANDLER_CLASSC_REGWEN_REG_OFFSET: u32 = 1288;
1145pub const ALERT_HANDLER_CLASSC_REGWEN_REG_RESVAL: u32 = 1;
1146pub const ALERT_HANDLER_CLASSC_REGWEN_CLASSC_REGWEN_BIT: u32 = 0;
1147pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_OFFSET: u32 = 1292;
1148pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_RESVAL: u32 = 14652;
1149pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_BIT: u32 = 0;
1150pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_LOCK_BIT: u32 = 1;
1151pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E0_BIT: u32 = 2;
1152pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E1_BIT: u32 = 3;
1153pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E2_BIT: u32 = 4;
1154pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E3_BIT: u32 = 5;
1155pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E0_MASK: u32 = 3;
1156pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E0_OFFSET: u32 = 6;
1157pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E1_MASK: u32 = 3;
1158pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E1_OFFSET: u32 = 8;
1159pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_MASK: u32 = 3;
1160pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_OFFSET: u32 = 10;
1161pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_MASK: u32 = 3;
1162pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_OFFSET: u32 = 12;
1163pub const ALERT_HANDLER_CLASSC_CLR_REGWEN_REG_OFFSET: u32 = 1296;
1164pub const ALERT_HANDLER_CLASSC_CLR_REGWEN_REG_RESVAL: u32 = 1;
1165pub const ALERT_HANDLER_CLASSC_CLR_REGWEN_CLASSC_CLR_REGWEN_BIT: u32 = 0;
1166pub const ALERT_HANDLER_CLASSC_CLR_SHADOWED_REG_OFFSET: u32 = 1300;
1167pub const ALERT_HANDLER_CLASSC_CLR_SHADOWED_REG_RESVAL: u32 = 0;
1168pub const ALERT_HANDLER_CLASSC_CLR_SHADOWED_CLASSC_CLR_SHADOWED_BIT: u32 = 0;
1169pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_REG_OFFSET: u32 = 1304;
1170pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_REG_RESVAL: u32 = 0;
1171pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_MASK: u32 = 65535;
1172pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_OFFSET: u32 = 0;
1173pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1308;
1174pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_REG_RESVAL: u32 = 0;
1175pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_MASK: u32 = 65535;
1176pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET: u32 = 0;
1177pub const ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1312;
1178pub const ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_REG_RESVAL: u32 = 0;
1179pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1316;
1180pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL: u32 = 0;
1181pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_MASK:
1182    u32 = 3;
1183pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET : u32 = 0 ;
1184pub const ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1320;
1185pub const ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_REG_RESVAL: u32 = 0;
1186pub const ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1324;
1187pub const ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_REG_RESVAL: u32 = 0;
1188pub const ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1328;
1189pub const ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_REG_RESVAL: u32 = 0;
1190pub const ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1332;
1191pub const ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_REG_RESVAL: u32 = 0;
1192pub const ALERT_HANDLER_CLASSC_ESC_CNT_REG_OFFSET: u32 = 1336;
1193pub const ALERT_HANDLER_CLASSC_ESC_CNT_REG_RESVAL: u32 = 0;
1194pub const ALERT_HANDLER_CLASSC_STATE_REG_OFFSET: u32 = 1340;
1195pub const ALERT_HANDLER_CLASSC_STATE_REG_RESVAL: u32 = 0;
1196pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_MASK: u32 = 7;
1197pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_OFFSET: u32 = 0;
1198pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_IDLE: u32 = 0;
1199pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_TIMEOUT: u32 = 1;
1200pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_FSMERROR: u32 = 2;
1201pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_TERMINAL: u32 = 3;
1202pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE0: u32 = 4;
1203pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE1: u32 = 5;
1204pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE2: u32 = 6;
1205pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE3: u32 = 7;
1206pub const ALERT_HANDLER_CLASSD_REGWEN_REG_OFFSET: u32 = 1344;
1207pub const ALERT_HANDLER_CLASSD_REGWEN_REG_RESVAL: u32 = 1;
1208pub const ALERT_HANDLER_CLASSD_REGWEN_CLASSD_REGWEN_BIT: u32 = 0;
1209pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_OFFSET: u32 = 1348;
1210pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_RESVAL: u32 = 14652;
1211pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_BIT: u32 = 0;
1212pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_LOCK_BIT: u32 = 1;
1213pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E0_BIT: u32 = 2;
1214pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E1_BIT: u32 = 3;
1215pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E2_BIT: u32 = 4;
1216pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E3_BIT: u32 = 5;
1217pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E0_MASK: u32 = 3;
1218pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E0_OFFSET: u32 = 6;
1219pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E1_MASK: u32 = 3;
1220pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E1_OFFSET: u32 = 8;
1221pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_MASK: u32 = 3;
1222pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_OFFSET: u32 = 10;
1223pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_MASK: u32 = 3;
1224pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_OFFSET: u32 = 12;
1225pub const ALERT_HANDLER_CLASSD_CLR_REGWEN_REG_OFFSET: u32 = 1352;
1226pub const ALERT_HANDLER_CLASSD_CLR_REGWEN_REG_RESVAL: u32 = 1;
1227pub const ALERT_HANDLER_CLASSD_CLR_REGWEN_CLASSD_CLR_REGWEN_BIT: u32 = 0;
1228pub const ALERT_HANDLER_CLASSD_CLR_SHADOWED_REG_OFFSET: u32 = 1356;
1229pub const ALERT_HANDLER_CLASSD_CLR_SHADOWED_REG_RESVAL: u32 = 0;
1230pub const ALERT_HANDLER_CLASSD_CLR_SHADOWED_CLASSD_CLR_SHADOWED_BIT: u32 = 0;
1231pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_REG_OFFSET: u32 = 1360;
1232pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_REG_RESVAL: u32 = 0;
1233pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_MASK: u32 = 65535;
1234pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_OFFSET: u32 = 0;
1235pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1364;
1236pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_REG_RESVAL: u32 = 0;
1237pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_MASK: u32 = 65535;
1238pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET: u32 = 0;
1239pub const ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1368;
1240pub const ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_REG_RESVAL: u32 = 0;
1241pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1372;
1242pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL: u32 = 0;
1243pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_MASK:
1244    u32 = 3;
1245pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET : u32 = 0 ;
1246pub const ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1376;
1247pub const ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_REG_RESVAL: u32 = 0;
1248pub const ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1380;
1249pub const ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_REG_RESVAL: u32 = 0;
1250pub const ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1384;
1251pub const ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_REG_RESVAL: u32 = 0;
1252pub const ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1388;
1253pub const ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_REG_RESVAL: u32 = 0;
1254pub const ALERT_HANDLER_CLASSD_ESC_CNT_REG_OFFSET: u32 = 1392;
1255pub const ALERT_HANDLER_CLASSD_ESC_CNT_REG_RESVAL: u32 = 0;
1256pub const ALERT_HANDLER_CLASSD_STATE_REG_OFFSET: u32 = 1396;
1257pub const ALERT_HANDLER_CLASSD_STATE_REG_RESVAL: u32 = 0;
1258pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_MASK: u32 = 7;
1259pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_OFFSET: u32 = 0;
1260pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_IDLE: u32 = 0;
1261pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_TIMEOUT: u32 = 1;
1262pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_FSMERROR: u32 = 2;
1263pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_TERMINAL: u32 = 3;
1264pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE0: u32 = 4;
1265pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE1: u32 = 5;
1266pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE2: u32 = 6;
1267pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE3: u32 = 7;
opentitanlib/otp/alert_handler_regs.rs

opentitanlib/otp/
alert_handler_regs.rs
