opentitanlib/dif/
rstmgr.rs

1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4
5use crate::util::bitfield::BitField;
6use crate::with_unknown;
7
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u32)]
10#[non_exhaustive]
11pub enum RstmgrReg {
12    AlertTest = bindgen::dif::RSTMGR_ALERT_TEST_REG_OFFSET,
13    ResetReq = bindgen::dif::RSTMGR_RESET_REQ_REG_OFFSET,
14    ResetInfo = bindgen::dif::RSTMGR_RESET_INFO_REG_OFFSET,
15    AlertRegwen = bindgen::dif::RSTMGR_ALERT_REGWEN_REG_OFFSET,
16    AlertInfoCtrl = bindgen::dif::RSTMGR_ALERT_INFO_CTRL_REG_OFFSET,
17    AlertInfoAttr = bindgen::dif::RSTMGR_ALERT_INFO_ATTR_REG_OFFSET,
18    AlertInfo = bindgen::dif::RSTMGR_ALERT_INFO_REG_OFFSET,
19    CpuRegwen = bindgen::dif::RSTMGR_CPU_REGWEN_REG_OFFSET,
20    CpuInfoCtrl = bindgen::dif::RSTMGR_CPU_INFO_CTRL_REG_OFFSET,
21    CpuInfoAttr = bindgen::dif::RSTMGR_CPU_INFO_ATTR_REG_OFFSET,
22    CpuInfo = bindgen::dif::RSTMGR_CPU_INFO_REG_OFFSET,
23    SwRstRegwen0 = bindgen::dif::RSTMGR_SW_RST_REGWEN_0_REG_OFFSET,
24    SwRstRegwen1 = bindgen::dif::RSTMGR_SW_RST_REGWEN_1_REG_OFFSET,
25    SwRstCtrlN0 = bindgen::dif::RSTMGR_SW_RST_CTRL_N_0_REG_OFFSET,
26    SwRstCtrlN1 = bindgen::dif::RSTMGR_SW_RST_CTRL_N_1_REG_OFFSET,
27    ErrCode = bindgen::dif::RSTMGR_ERR_CODE_REG_OFFSET,
28}
29
30/// BitFields for the CPU_INFO_CTRL register.
31pub struct RstmgrCpuRegwen;
32
33impl RstmgrCpuRegwen {
34    pub const EN: u32 = 0b1 << bindgen::dif::RSTMGR_CPU_REGWEN_EN_BIT;
35}
36
37/// BitFields for the CPU_INFO_CTRL register.
38pub struct RstmgrCpuInfoCtrl;
39
40impl RstmgrCpuInfoCtrl {
41    pub const EN: u32 = 0b1 << bindgen::dif::RSTMGR_CPU_INFO_CTRL_EN_BIT;
42
43    pub const INDEX: BitField = BitField {
44        offset: bindgen::dif::RSTMGR_CPU_INFO_CTRL_INDEX_OFFSET,
45        // Relies on mask being continuous
46        size: bindgen::dif::RSTMGR_CPU_INFO_CTRL_INDEX_MASK.count_ones(),
47    };
48}
49
50/// BitFields for the ALERT_INFO_CTRL register.
51pub struct RstmgrAlertInfoCtrl;
52
53impl RstmgrAlertInfoCtrl {
54    pub const EN: u32 = 0b1 << bindgen::dif::RSTMGR_ALERT_INFO_CTRL_EN_BIT;
55
56    pub const INDEX: BitField = BitField {
57        offset: bindgen::dif::RSTMGR_ALERT_INFO_CTRL_INDEX_OFFSET,
58        // Relies on mask being continuous
59        size: bindgen::dif::RSTMGR_ALERT_INFO_CTRL_INDEX_MASK.count_ones(),
60    };
61}
62
63with_unknown! {
64    pub enum DifRstmgrResetInfo: u32 {
65        Por = bindgen::dif::dif_rstmgr_reset_info_kDifRstmgrResetInfoPor,
66        LowPowerExit = bindgen::dif::dif_rstmgr_reset_info_kDifRstmgrResetInfoLowPowerExit,
67        Sw = bindgen::dif::dif_rstmgr_reset_info_kDifRstmgrResetInfoSw,
68        HwReq  = bindgen::dif::dif_rstmgr_reset_info_kDifRstmgrResetInfoHwReq,
69        SysRstCtrl  = bindgen::dif::dif_rstmgr_reset_info_kDifRstmgrResetInfoSysRstCtrl,
70        Watchdog  = bindgen::dif::dif_rstmgr_reset_info_kDifRstmgrResetInfoWatchdog,
71        PowerUnstable = bindgen::dif::dif_rstmgr_reset_info_kDifRstmgrResetInfoPowerUnstable,
72        Escalation = bindgen::dif::dif_rstmgr_reset_info_kDifRstmgrResetInfoEscalation,
73        Ndm = bindgen::dif::dif_rstmgr_reset_info_kDifRstmgrResetInfoNdm,
74    }
75}
opentitanlib/dif/rstmgr.rs

opentitanlib/dif/
rstmgr.rs
