opentitanlib/chip/autogen/
earlgrey.rs

1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4
5// This file was generated automatically.
6// Please do not modify content of this file directly.
7// File generated by using template: "host_toplevel.rs.tpl"
8// To regenerate this file follow OpenTitan topgen documentations.
9
10#![allow(dead_code)]
11
12use crate::with_unknown;
13
14with_unknown! {
15    pub enum PinmuxPeripheralIn: u32 [default = Self::End] {
16        GpioGpio0 = 0,
17        GpioGpio1 = 1,
18        GpioGpio2 = 2,
19        GpioGpio3 = 3,
20        GpioGpio4 = 4,
21        GpioGpio5 = 5,
22        GpioGpio6 = 6,
23        GpioGpio7 = 7,
24        GpioGpio8 = 8,
25        GpioGpio9 = 9,
26        GpioGpio10 = 10,
27        GpioGpio11 = 11,
28        GpioGpio12 = 12,
29        GpioGpio13 = 13,
30        GpioGpio14 = 14,
31        GpioGpio15 = 15,
32        GpioGpio16 = 16,
33        GpioGpio17 = 17,
34        GpioGpio18 = 18,
35        GpioGpio19 = 19,
36        GpioGpio20 = 20,
37        GpioGpio21 = 21,
38        GpioGpio22 = 22,
39        GpioGpio23 = 23,
40        GpioGpio24 = 24,
41        GpioGpio25 = 25,
42        GpioGpio26 = 26,
43        GpioGpio27 = 27,
44        GpioGpio28 = 28,
45        GpioGpio29 = 29,
46        GpioGpio30 = 30,
47        GpioGpio31 = 31,
48        I2c0Sda = 32,
49        I2c0Scl = 33,
50        I2c1Sda = 34,
51        I2c1Scl = 35,
52        I2c2Sda = 36,
53        I2c2Scl = 37,
54        SpiHost1Sd0 = 38,
55        SpiHost1Sd1 = 39,
56        SpiHost1Sd2 = 40,
57        SpiHost1Sd3 = 41,
58        Uart0Rx = 42,
59        Uart1Rx = 43,
60        Uart2Rx = 44,
61        Uart3Rx = 45,
62        SpiDeviceTpmCsb = 46,
63        FlashCtrlTck = 47,
64        FlashCtrlTms = 48,
65        FlashCtrlTdi = 49,
66        SysrstCtrlAonAcPresent = 50,
67        SysrstCtrlAonKey0In = 51,
68        SysrstCtrlAonKey1In = 52,
69        SysrstCtrlAonKey2In = 53,
70        SysrstCtrlAonPwrbIn = 54,
71        SysrstCtrlAonLidOpen = 55,
72        UsbdevSense = 56,
73        End = 57,
74    }
75
76    pub enum PinmuxInsel: u32 [default = Self::End] {
77        ConstantZero = 0,
78        ConstantOne = 1,
79        Ioa0 = 2,
80        Ioa1 = 3,
81        Ioa2 = 4,
82        Ioa3 = 5,
83        Ioa4 = 6,
84        Ioa5 = 7,
85        Ioa6 = 8,
86        Ioa7 = 9,
87        Ioa8 = 10,
88        Iob0 = 11,
89        Iob1 = 12,
90        Iob2 = 13,
91        Iob3 = 14,
92        Iob4 = 15,
93        Iob5 = 16,
94        Iob6 = 17,
95        Iob7 = 18,
96        Iob8 = 19,
97        Iob9 = 20,
98        Iob10 = 21,
99        Iob11 = 22,
100        Iob12 = 23,
101        Ioc0 = 24,
102        Ioc1 = 25,
103        Ioc2 = 26,
104        Ioc3 = 27,
105        Ioc4 = 28,
106        Ioc5 = 29,
107        Ioc6 = 30,
108        Ioc7 = 31,
109        Ioc8 = 32,
110        Ioc9 = 33,
111        Ioc10 = 34,
112        Ioc11 = 35,
113        Ioc12 = 36,
114        Ior0 = 37,
115        Ior1 = 38,
116        Ior2 = 39,
117        Ior3 = 40,
118        Ior4 = 41,
119        Ior5 = 42,
120        Ior6 = 43,
121        Ior7 = 44,
122        Ior10 = 45,
123        Ior11 = 46,
124        Ior12 = 47,
125        Ior13 = 48,
126        End = 49,
127    }
128
129    pub enum PinmuxMioOut: u32 [default = Self::End] {
130        Ioa0 = 0,
131        Ioa1 = 1,
132        Ioa2 = 2,
133        Ioa3 = 3,
134        Ioa4 = 4,
135        Ioa5 = 5,
136        Ioa6 = 6,
137        Ioa7 = 7,
138        Ioa8 = 8,
139        Iob0 = 9,
140        Iob1 = 10,
141        Iob2 = 11,
142        Iob3 = 12,
143        Iob4 = 13,
144        Iob5 = 14,
145        Iob6 = 15,
146        Iob7 = 16,
147        Iob8 = 17,
148        Iob9 = 18,
149        Iob10 = 19,
150        Iob11 = 20,
151        Iob12 = 21,
152        Ioc0 = 22,
153        Ioc1 = 23,
154        Ioc2 = 24,
155        Ioc3 = 25,
156        Ioc4 = 26,
157        Ioc5 = 27,
158        Ioc6 = 28,
159        Ioc7 = 29,
160        Ioc8 = 30,
161        Ioc9 = 31,
162        Ioc10 = 32,
163        Ioc11 = 33,
164        Ioc12 = 34,
165        Ior0 = 35,
166        Ior1 = 36,
167        Ior2 = 37,
168        Ior3 = 38,
169        Ior4 = 39,
170        Ior5 = 40,
171        Ior6 = 41,
172        Ior7 = 42,
173        Ior10 = 43,
174        Ior11 = 44,
175        Ior12 = 45,
176        Ior13 = 46,
177        End = 47,
178    }
179
180    pub enum PinmuxOutsel: u32 [default = Self::End] {
181        ConstantZero = 0,
182        ConstantOne = 1,
183        ConstantHighZ = 2,
184        GpioGpio0 = 3,
185        GpioGpio1 = 4,
186        GpioGpio2 = 5,
187        GpioGpio3 = 6,
188        GpioGpio4 = 7,
189        GpioGpio5 = 8,
190        GpioGpio6 = 9,
191        GpioGpio7 = 10,
192        GpioGpio8 = 11,
193        GpioGpio9 = 12,
194        GpioGpio10 = 13,
195        GpioGpio11 = 14,
196        GpioGpio12 = 15,
197        GpioGpio13 = 16,
198        GpioGpio14 = 17,
199        GpioGpio15 = 18,
200        GpioGpio16 = 19,
201        GpioGpio17 = 20,
202        GpioGpio18 = 21,
203        GpioGpio19 = 22,
204        GpioGpio20 = 23,
205        GpioGpio21 = 24,
206        GpioGpio22 = 25,
207        GpioGpio23 = 26,
208        GpioGpio24 = 27,
209        GpioGpio25 = 28,
210        GpioGpio26 = 29,
211        GpioGpio27 = 30,
212        GpioGpio28 = 31,
213        GpioGpio29 = 32,
214        GpioGpio30 = 33,
215        GpioGpio31 = 34,
216        I2c0Sda = 35,
217        I2c0Scl = 36,
218        I2c1Sda = 37,
219        I2c1Scl = 38,
220        I2c2Sda = 39,
221        I2c2Scl = 40,
222        SpiHost1Sd0 = 41,
223        SpiHost1Sd1 = 42,
224        SpiHost1Sd2 = 43,
225        SpiHost1Sd3 = 44,
226        Uart0Tx = 45,
227        Uart1Tx = 46,
228        Uart2Tx = 47,
229        Uart3Tx = 48,
230        PattgenPda0Tx = 49,
231        PattgenPcl0Tx = 50,
232        PattgenPda1Tx = 51,
233        PattgenPcl1Tx = 52,
234        SpiHost1Sck = 53,
235        SpiHost1Csb = 54,
236        FlashCtrlTdo = 55,
237        SensorCtrlAonAstDebugOut0 = 56,
238        SensorCtrlAonAstDebugOut1 = 57,
239        SensorCtrlAonAstDebugOut2 = 58,
240        SensorCtrlAonAstDebugOut3 = 59,
241        SensorCtrlAonAstDebugOut4 = 60,
242        SensorCtrlAonAstDebugOut5 = 61,
243        SensorCtrlAonAstDebugOut6 = 62,
244        SensorCtrlAonAstDebugOut7 = 63,
245        SensorCtrlAonAstDebugOut8 = 64,
246        PwmAonPwm0 = 65,
247        PwmAonPwm1 = 66,
248        PwmAonPwm2 = 67,
249        PwmAonPwm3 = 68,
250        PwmAonPwm4 = 69,
251        PwmAonPwm5 = 70,
252        OtpMacroTest0 = 71,
253        SysrstCtrlAonBatDisable = 72,
254        SysrstCtrlAonKey0Out = 73,
255        SysrstCtrlAonKey1Out = 74,
256        SysrstCtrlAonKey2Out = 75,
257        SysrstCtrlAonPwrbOut = 76,
258        SysrstCtrlAonZ3Wakeup = 77,
259        End = 78,
260    }
261
262    pub enum DirectPads: u32 [default = Self::End] {
263        UsbdevUsbDp = 0,
264        UsbdevUsbDn = 1,
265        SpiHost0Sd0 = 2,
266        SpiHost0Sd1 = 3,
267        SpiHost0Sd2 = 4,
268        SpiHost0Sd3 = 5,
269        SpiDeviceSd0 = 6,
270        SpiDeviceSd1 = 7,
271        SpiDeviceSd2 = 8,
272        SpiDeviceSd3 = 9,
273        SysrstCtrlAonEcRstL = 10,
274        SysrstCtrlAonFlashWpL = 11,
275        SpiDeviceSck = 12,
276        SpiDeviceCsb = 13,
277        SpiHost0Sck = 14,
278        SpiHost0Csb = 15,
279        End = 16,
280    }
281
282    pub enum MuxedPads: u32 [default = Self::End] {
283        Ioa0 = 0,
284        Ioa1 = 1,
285        Ioa2 = 2,
286        Ioa3 = 3,
287        Ioa4 = 4,
288        Ioa5 = 5,
289        Ioa6 = 6,
290        Ioa7 = 7,
291        Ioa8 = 8,
292        Iob0 = 9,
293        Iob1 = 10,
294        Iob2 = 11,
295        Iob3 = 12,
296        Iob4 = 13,
297        Iob5 = 14,
298        Iob6 = 15,
299        Iob7 = 16,
300        Iob8 = 17,
301        Iob9 = 18,
302        Iob10 = 19,
303        Iob11 = 20,
304        Iob12 = 21,
305        Ioc0 = 22,
306        Ioc1 = 23,
307        Ioc2 = 24,
308        Ioc3 = 25,
309        Ioc4 = 26,
310        Ioc5 = 27,
311        Ioc6 = 28,
312        Ioc7 = 29,
313        Ioc8 = 30,
314        Ioc9 = 31,
315        Ioc10 = 32,
316        Ioc11 = 33,
317        Ioc12 = 34,
318        Ior0 = 35,
319        Ior1 = 36,
320        Ior2 = 37,
321        Ior3 = 38,
322        Ior4 = 39,
323        Ior5 = 40,
324        Ior6 = 41,
325        Ior7 = 42,
326        Ior10 = 43,
327        Ior11 = 44,
328        Ior12 = 45,
329        Ior13 = 46,
330        End = 47,
331    }
332}
333
334#[allow(non_camel_case_types)]
335pub mod ujson_alias {
336    use super::*;
337    // Create aliases for the C names of these types so that the ujson
338    // created structs can access these structures by their C names.
339    pub type pinmux_peripheral_in_t = PinmuxPeripheralIn;
340    pub type pinmux_insel_t = PinmuxInsel;
341    pub type pinmux_mio_out_t = PinmuxMioOut;
342    pub type pinmux_outsel_t = PinmuxOutsel;
343}
opentitanlib/chip/autogen/earlgrey.rs

opentitanlib/chip/autogen/
earlgrey.rs
