Module fpga_backdoor

Structs

LoadMemories

TargetClear

TargetWrite

VerifyMismatch

A genuine content mismatch found by verify_readback, as opposed to some other failure (e.g. a JTAG/OpenOCD communication error) that can occur while a write is being verified. Kept distinct so callers can tell “verification ran and found a real mismatch” apart from “verification didn’t get a conclusive answer at all”.

Functions

enter_backdoor

verify_readback

write_to_target