Software APIs
top_englishbreakfast_memory.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
6// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
7// util/topgen.py -t hw/top_englishbreakfast/data/top_englishbreakfast.hjson
8// -o hw/top_englishbreakfast
9
10#ifndef OPENTITAN_HW_TOP_ENGLISHBREAKFAST_SW_AUTOGEN_TOP_ENGLISHBREAKFAST_MEMORY_H_
11#define OPENTITAN_HW_TOP_ENGLISHBREAKFAST_SW_AUTOGEN_TOP_ENGLISHBREAKFAST_MEMORY_H_
12
13/**
14 * @file
15 * @brief Assembler-only Top-Specific Definitions.
16 *
17 * This file contains preprocessor definitions for use within assembly code.
18 *
19 * These are not shared with C/C++ code because these are only allowed to be
20 * preprocessor definitions, no data or type declarations are allowed. The
21 * assembler is also stricter about literals (not allowing suffixes for
22 * signed/unsigned which are sensible to use for unsigned values in C/C++).
23 */
24
25// Include guard for assembler
26#ifdef __ASSEMBLER__
27/**
28 * Memory base for flash_ctrl_eflash in top englishbreakfast.
29 */
30#define TOP_ENGLISHBREAKFAST_EFLASH_BASE_ADDR 0x20000000
31
32/**
33 * Memory size for flash_ctrl_eflash in top englishbreakfast.
34 */
35#define TOP_ENGLISHBREAKFAST_EFLASH_SIZE_BYTES 0x10000
36
37/**
38 * Memory base for sram_ctrl_main_ram_main in top englishbreakfast.
39 */
40#define TOP_ENGLISHBREAKFAST_RAM_MAIN_BASE_ADDR 0x10000000
41
42/**
43 * Memory size for sram_ctrl_main_ram_main in top englishbreakfast.
44 */
45#define TOP_ENGLISHBREAKFAST_RAM_MAIN_SIZE_BYTES 0x20000
46
47/**
48 * Memory base for rom_ctrl_rom in top englishbreakfast.
49 */
50#define TOP_ENGLISHBREAKFAST_ROM_BASE_ADDR 0x00008000
51
52/**
53 * Memory size for rom_ctrl_rom in top englishbreakfast.
54 */
55#define TOP_ENGLISHBREAKFAST_ROM_SIZE_BYTES 0x8000
56
57
58
59/**
60 * Peripheral base address for uart0 in top englishbreakfast.
61 *
62 * This should be used with #mmio_region_from_addr to access the memory-mapped
63 * registers associated with the peripheral (usually via a DIF).
64 */
65#define TOP_ENGLISHBREAKFAST_UART0_BASE_ADDR 0x40000000
66
67/**
68 * Peripheral size for uart0 in top englishbreakfast.
69 *
70 * This is the size (in bytes) of the peripheral's reserved memory area. All
71 * memory-mapped registers associated with this peripheral should have an
72 * address between #TOP_ENGLISHBREAKFAST_UART0_BASE_ADDR and
73 * `TOP_ENGLISHBREAKFAST_UART0_BASE_ADDR + TOP_ENGLISHBREAKFAST_UART0_SIZE_BYTES`.
74 */
75#define TOP_ENGLISHBREAKFAST_UART0_SIZE_BYTES 0x40
76/**
77 * Peripheral base address for uart1 in top englishbreakfast.
78 *
79 * This should be used with #mmio_region_from_addr to access the memory-mapped
80 * registers associated with the peripheral (usually via a DIF).
81 */
82#define TOP_ENGLISHBREAKFAST_UART1_BASE_ADDR 0x40010000
83
84/**
85 * Peripheral size for uart1 in top englishbreakfast.
86 *
87 * This is the size (in bytes) of the peripheral's reserved memory area. All
88 * memory-mapped registers associated with this peripheral should have an
89 * address between #TOP_ENGLISHBREAKFAST_UART1_BASE_ADDR and
90 * `TOP_ENGLISHBREAKFAST_UART1_BASE_ADDR + TOP_ENGLISHBREAKFAST_UART1_SIZE_BYTES`.
91 */
92#define TOP_ENGLISHBREAKFAST_UART1_SIZE_BYTES 0x40
93/**
94 * Peripheral base address for gpio in top englishbreakfast.
95 *
96 * This should be used with #mmio_region_from_addr to access the memory-mapped
97 * registers associated with the peripheral (usually via a DIF).
98 */
99#define TOP_ENGLISHBREAKFAST_GPIO_BASE_ADDR 0x40040000
100
101/**
102 * Peripheral size for gpio in top englishbreakfast.
103 *
104 * This is the size (in bytes) of the peripheral's reserved memory area. All
105 * memory-mapped registers associated with this peripheral should have an
106 * address between #TOP_ENGLISHBREAKFAST_GPIO_BASE_ADDR and
107 * `TOP_ENGLISHBREAKFAST_GPIO_BASE_ADDR + TOP_ENGLISHBREAKFAST_GPIO_SIZE_BYTES`.
108 */
109#define TOP_ENGLISHBREAKFAST_GPIO_SIZE_BYTES 0x80
110/**
111 * Peripheral base address for spi_device in top englishbreakfast.
112 *
113 * This should be used with #mmio_region_from_addr to access the memory-mapped
114 * registers associated with the peripheral (usually via a DIF).
115 */
116#define TOP_ENGLISHBREAKFAST_SPI_DEVICE_BASE_ADDR 0x40050000
117
118/**
119 * Peripheral size for spi_device in top englishbreakfast.
120 *
121 * This is the size (in bytes) of the peripheral's reserved memory area. All
122 * memory-mapped registers associated with this peripheral should have an
123 * address between #TOP_ENGLISHBREAKFAST_SPI_DEVICE_BASE_ADDR and
124 * `TOP_ENGLISHBREAKFAST_SPI_DEVICE_BASE_ADDR + TOP_ENGLISHBREAKFAST_SPI_DEVICE_SIZE_BYTES`.
125 */
126#define TOP_ENGLISHBREAKFAST_SPI_DEVICE_SIZE_BYTES 0x2000
127/**
128 * Peripheral base address for spi_host0 in top englishbreakfast.
129 *
130 * This should be used with #mmio_region_from_addr to access the memory-mapped
131 * registers associated with the peripheral (usually via a DIF).
132 */
133#define TOP_ENGLISHBREAKFAST_SPI_HOST0_BASE_ADDR 0x40060000
134
135/**
136 * Peripheral size for spi_host0 in top englishbreakfast.
137 *
138 * This is the size (in bytes) of the peripheral's reserved memory area. All
139 * memory-mapped registers associated with this peripheral should have an
140 * address between #TOP_ENGLISHBREAKFAST_SPI_HOST0_BASE_ADDR and
141 * `TOP_ENGLISHBREAKFAST_SPI_HOST0_BASE_ADDR + TOP_ENGLISHBREAKFAST_SPI_HOST0_SIZE_BYTES`.
142 */
143#define TOP_ENGLISHBREAKFAST_SPI_HOST0_SIZE_BYTES 0x40
144/**
145 * Peripheral base address for rv_timer in top englishbreakfast.
146 *
147 * This should be used with #mmio_region_from_addr to access the memory-mapped
148 * registers associated with the peripheral (usually via a DIF).
149 */
150#define TOP_ENGLISHBREAKFAST_RV_TIMER_BASE_ADDR 0x40100000
151
152/**
153 * Peripheral size for rv_timer in top englishbreakfast.
154 *
155 * This is the size (in bytes) of the peripheral's reserved memory area. All
156 * memory-mapped registers associated with this peripheral should have an
157 * address between #TOP_ENGLISHBREAKFAST_RV_TIMER_BASE_ADDR and
158 * `TOP_ENGLISHBREAKFAST_RV_TIMER_BASE_ADDR + TOP_ENGLISHBREAKFAST_RV_TIMER_SIZE_BYTES`.
159 */
160#define TOP_ENGLISHBREAKFAST_RV_TIMER_SIZE_BYTES 0x200
161/**
162 * Peripheral base address for usbdev in top englishbreakfast.
163 *
164 * This should be used with #mmio_region_from_addr to access the memory-mapped
165 * registers associated with the peripheral (usually via a DIF).
166 */
167#define TOP_ENGLISHBREAKFAST_USBDEV_BASE_ADDR 0x40320000
168
169/**
170 * Peripheral size for usbdev in top englishbreakfast.
171 *
172 * This is the size (in bytes) of the peripheral's reserved memory area. All
173 * memory-mapped registers associated with this peripheral should have an
174 * address between #TOP_ENGLISHBREAKFAST_USBDEV_BASE_ADDR and
175 * `TOP_ENGLISHBREAKFAST_USBDEV_BASE_ADDR + TOP_ENGLISHBREAKFAST_USBDEV_SIZE_BYTES`.
176 */
177#define TOP_ENGLISHBREAKFAST_USBDEV_SIZE_BYTES 0x1000
178/**
179 * Peripheral base address for pwrmgr_aon in top englishbreakfast.
180 *
181 * This should be used with #mmio_region_from_addr to access the memory-mapped
182 * registers associated with the peripheral (usually via a DIF).
183 */
184#define TOP_ENGLISHBREAKFAST_PWRMGR_AON_BASE_ADDR 0x40400000
185
186/**
187 * Peripheral size for pwrmgr_aon in top englishbreakfast.
188 *
189 * This is the size (in bytes) of the peripheral's reserved memory area. All
190 * memory-mapped registers associated with this peripheral should have an
191 * address between #TOP_ENGLISHBREAKFAST_PWRMGR_AON_BASE_ADDR and
192 * `TOP_ENGLISHBREAKFAST_PWRMGR_AON_BASE_ADDR + TOP_ENGLISHBREAKFAST_PWRMGR_AON_SIZE_BYTES`.
193 */
194#define TOP_ENGLISHBREAKFAST_PWRMGR_AON_SIZE_BYTES 0x80
195/**
196 * Peripheral base address for rstmgr_aon in top englishbreakfast.
197 *
198 * This should be used with #mmio_region_from_addr to access the memory-mapped
199 * registers associated with the peripheral (usually via a DIF).
200 */
201#define TOP_ENGLISHBREAKFAST_RSTMGR_AON_BASE_ADDR 0x40410000
202
203/**
204 * Peripheral size for rstmgr_aon in top englishbreakfast.
205 *
206 * This is the size (in bytes) of the peripheral's reserved memory area. All
207 * memory-mapped registers associated with this peripheral should have an
208 * address between #TOP_ENGLISHBREAKFAST_RSTMGR_AON_BASE_ADDR and
209 * `TOP_ENGLISHBREAKFAST_RSTMGR_AON_BASE_ADDR + TOP_ENGLISHBREAKFAST_RSTMGR_AON_SIZE_BYTES`.
210 */
211#define TOP_ENGLISHBREAKFAST_RSTMGR_AON_SIZE_BYTES 0x80
212/**
213 * Peripheral base address for clkmgr_aon in top englishbreakfast.
214 *
215 * This should be used with #mmio_region_from_addr to access the memory-mapped
216 * registers associated with the peripheral (usually via a DIF).
217 */
218#define TOP_ENGLISHBREAKFAST_CLKMGR_AON_BASE_ADDR 0x40420000
219
220/**
221 * Peripheral size for clkmgr_aon in top englishbreakfast.
222 *
223 * This is the size (in bytes) of the peripheral's reserved memory area. All
224 * memory-mapped registers associated with this peripheral should have an
225 * address between #TOP_ENGLISHBREAKFAST_CLKMGR_AON_BASE_ADDR and
226 * `TOP_ENGLISHBREAKFAST_CLKMGR_AON_BASE_ADDR + TOP_ENGLISHBREAKFAST_CLKMGR_AON_SIZE_BYTES`.
227 */
228#define TOP_ENGLISHBREAKFAST_CLKMGR_AON_SIZE_BYTES 0x80
229/**
230 * Peripheral base address for pinmux_aon in top englishbreakfast.
231 *
232 * This should be used with #mmio_region_from_addr to access the memory-mapped
233 * registers associated with the peripheral (usually via a DIF).
234 */
235#define TOP_ENGLISHBREAKFAST_PINMUX_AON_BASE_ADDR 0x40460000
236
237/**
238 * Peripheral size for pinmux_aon in top englishbreakfast.
239 *
240 * This is the size (in bytes) of the peripheral's reserved memory area. All
241 * memory-mapped registers associated with this peripheral should have an
242 * address between #TOP_ENGLISHBREAKFAST_PINMUX_AON_BASE_ADDR and
243 * `TOP_ENGLISHBREAKFAST_PINMUX_AON_BASE_ADDR + TOP_ENGLISHBREAKFAST_PINMUX_AON_SIZE_BYTES`.
244 */
245#define TOP_ENGLISHBREAKFAST_PINMUX_AON_SIZE_BYTES 0x1000
246/**
247 * Peripheral base address for aon_timer_aon in top englishbreakfast.
248 *
249 * This should be used with #mmio_region_from_addr to access the memory-mapped
250 * registers associated with the peripheral (usually via a DIF).
251 */
252#define TOP_ENGLISHBREAKFAST_AON_TIMER_AON_BASE_ADDR 0x40470000
253
254/**
255 * Peripheral size for aon_timer_aon in top englishbreakfast.
256 *
257 * This is the size (in bytes) of the peripheral's reserved memory area. All
258 * memory-mapped registers associated with this peripheral should have an
259 * address between #TOP_ENGLISHBREAKFAST_AON_TIMER_AON_BASE_ADDR and
260 * `TOP_ENGLISHBREAKFAST_AON_TIMER_AON_BASE_ADDR + TOP_ENGLISHBREAKFAST_AON_TIMER_AON_SIZE_BYTES`.
261 */
262#define TOP_ENGLISHBREAKFAST_AON_TIMER_AON_SIZE_BYTES 0x40
263/**
264 * Peripheral base address for ast in top englishbreakfast.
265 *
266 * This should be used with #mmio_region_from_addr to access the memory-mapped
267 * registers associated with the peripheral (usually via a DIF).
268 */
269#define TOP_ENGLISHBREAKFAST_AST_BASE_ADDR 0x40480000
270
271/**
272 * Peripheral size for ast in top englishbreakfast.
273 *
274 * This is the size (in bytes) of the peripheral's reserved memory area. All
275 * memory-mapped registers associated with this peripheral should have an
276 * address between #TOP_ENGLISHBREAKFAST_AST_BASE_ADDR and
277 * `TOP_ENGLISHBREAKFAST_AST_BASE_ADDR + TOP_ENGLISHBREAKFAST_AST_SIZE_BYTES`.
278 */
279#define TOP_ENGLISHBREAKFAST_AST_SIZE_BYTES 0x400
280/**
281 * Peripheral base address for core device on flash_ctrl in top englishbreakfast.
282 *
283 * This should be used with #mmio_region_from_addr to access the memory-mapped
284 * registers associated with the peripheral (usually via a DIF).
285 */
286#define TOP_ENGLISHBREAKFAST_FLASH_CTRL_CORE_BASE_ADDR 0x41000000
287
288/**
289 * Peripheral size for core device on flash_ctrl in top englishbreakfast.
290 *
291 * This is the size (in bytes) of the peripheral's reserved memory area. All
292 * memory-mapped registers associated with this peripheral should have an
293 * address between #TOP_ENGLISHBREAKFAST_FLASH_CTRL_CORE_BASE_ADDR and
294 * `TOP_ENGLISHBREAKFAST_FLASH_CTRL_CORE_BASE_ADDR + TOP_ENGLISHBREAKFAST_FLASH_CTRL_CORE_SIZE_BYTES`.
295 */
296#define TOP_ENGLISHBREAKFAST_FLASH_CTRL_CORE_SIZE_BYTES 0x200
297/**
298 * Peripheral base address for prim device on flash_ctrl in top englishbreakfast.
299 *
300 * This should be used with #mmio_region_from_addr to access the memory-mapped
301 * registers associated with the peripheral (usually via a DIF).
302 */
303#define TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_BASE_ADDR 0x41008000
304
305/**
306 * Peripheral size for prim device on flash_ctrl in top englishbreakfast.
307 *
308 * This is the size (in bytes) of the peripheral's reserved memory area. All
309 * memory-mapped registers associated with this peripheral should have an
310 * address between #TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_BASE_ADDR and
311 * `TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_BASE_ADDR + TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_SIZE_BYTES`.
312 */
313#define TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_SIZE_BYTES 0x80
314/**
315 * Peripheral base address for mem device on flash_ctrl in top englishbreakfast.
316 *
317 * This should be used with #mmio_region_from_addr to access the memory-mapped
318 * registers associated with the peripheral (usually via a DIF).
319 */
320#define TOP_ENGLISHBREAKFAST_FLASH_CTRL_MEM_BASE_ADDR 0x20000000
321
322/**
323 * Peripheral size for mem device on flash_ctrl in top englishbreakfast.
324 *
325 * This is the size (in bytes) of the peripheral's reserved memory area. All
326 * memory-mapped registers associated with this peripheral should have an
327 * address between #TOP_ENGLISHBREAKFAST_FLASH_CTRL_MEM_BASE_ADDR and
328 * `TOP_ENGLISHBREAKFAST_FLASH_CTRL_MEM_BASE_ADDR + TOP_ENGLISHBREAKFAST_FLASH_CTRL_MEM_SIZE_BYTES`.
329 */
330#define TOP_ENGLISHBREAKFAST_FLASH_CTRL_MEM_SIZE_BYTES 0x10000
331/**
332 * Peripheral base address for rv_plic in top englishbreakfast.
333 *
334 * This should be used with #mmio_region_from_addr to access the memory-mapped
335 * registers associated with the peripheral (usually via a DIF).
336 */
337#define TOP_ENGLISHBREAKFAST_RV_PLIC_BASE_ADDR 0x48000000
338
339/**
340 * Peripheral size for rv_plic in top englishbreakfast.
341 *
342 * This is the size (in bytes) of the peripheral's reserved memory area. All
343 * memory-mapped registers associated with this peripheral should have an
344 * address between #TOP_ENGLISHBREAKFAST_RV_PLIC_BASE_ADDR and
345 * `TOP_ENGLISHBREAKFAST_RV_PLIC_BASE_ADDR + TOP_ENGLISHBREAKFAST_RV_PLIC_SIZE_BYTES`.
346 */
347#define TOP_ENGLISHBREAKFAST_RV_PLIC_SIZE_BYTES 0x8000000
348/**
349 * Peripheral base address for aes in top englishbreakfast.
350 *
351 * This should be used with #mmio_region_from_addr to access the memory-mapped
352 * registers associated with the peripheral (usually via a DIF).
353 */
354#define TOP_ENGLISHBREAKFAST_AES_BASE_ADDR 0x41100000
355
356/**
357 * Peripheral size for aes in top englishbreakfast.
358 *
359 * This is the size (in bytes) of the peripheral's reserved memory area. All
360 * memory-mapped registers associated with this peripheral should have an
361 * address between #TOP_ENGLISHBREAKFAST_AES_BASE_ADDR and
362 * `TOP_ENGLISHBREAKFAST_AES_BASE_ADDR + TOP_ENGLISHBREAKFAST_AES_SIZE_BYTES`.
363 */
364#define TOP_ENGLISHBREAKFAST_AES_SIZE_BYTES 0x100
365/**
366 * Peripheral base address for regs device on sram_ctrl_main in top englishbreakfast.
367 *
368 * This should be used with #mmio_region_from_addr to access the memory-mapped
369 * registers associated with the peripheral (usually via a DIF).
370 */
371#define TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x411C0000
372
373/**
374 * Peripheral size for regs device on sram_ctrl_main in top englishbreakfast.
375 *
376 * This is the size (in bytes) of the peripheral's reserved memory area. All
377 * memory-mapped registers associated with this peripheral should have an
378 * address between #TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_REGS_BASE_ADDR and
379 * `TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_REGS_BASE_ADDR + TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_REGS_SIZE_BYTES`.
380 */
381#define TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x40
382/**
383 * Peripheral base address for ram device on sram_ctrl_main in top englishbreakfast.
384 *
385 * This should be used with #mmio_region_from_addr to access the memory-mapped
386 * registers associated with the peripheral (usually via a DIF).
387 */
388#define TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000
389
390/**
391 * Peripheral size for ram device on sram_ctrl_main in top englishbreakfast.
392 *
393 * This is the size (in bytes) of the peripheral's reserved memory area. All
394 * memory-mapped registers associated with this peripheral should have an
395 * address between #TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_RAM_BASE_ADDR and
396 * `TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_RAM_BASE_ADDR + TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_RAM_SIZE_BYTES`.
397 */
398#define TOP_ENGLISHBREAKFAST_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x20000
399/**
400 * Peripheral base address for regs device on rom_ctrl in top englishbreakfast.
401 *
402 * This should be used with #mmio_region_from_addr to access the memory-mapped
403 * registers associated with the peripheral (usually via a DIF).
404 */
405#define TOP_ENGLISHBREAKFAST_ROM_CTRL_REGS_BASE_ADDR 0x411E0000
406
407/**
408 * Peripheral size for regs device on rom_ctrl in top englishbreakfast.
409 *
410 * This is the size (in bytes) of the peripheral's reserved memory area. All
411 * memory-mapped registers associated with this peripheral should have an
412 * address between #TOP_ENGLISHBREAKFAST_ROM_CTRL_REGS_BASE_ADDR and
413 * `TOP_ENGLISHBREAKFAST_ROM_CTRL_REGS_BASE_ADDR + TOP_ENGLISHBREAKFAST_ROM_CTRL_REGS_SIZE_BYTES`.
414 */
415#define TOP_ENGLISHBREAKFAST_ROM_CTRL_REGS_SIZE_BYTES 0x80
416/**
417 * Peripheral base address for rom device on rom_ctrl in top englishbreakfast.
418 *
419 * This should be used with #mmio_region_from_addr to access the memory-mapped
420 * registers associated with the peripheral (usually via a DIF).
421 */
422#define TOP_ENGLISHBREAKFAST_ROM_CTRL_ROM_BASE_ADDR 0x8000
423
424/**
425 * Peripheral size for rom device on rom_ctrl in top englishbreakfast.
426 *
427 * This is the size (in bytes) of the peripheral's reserved memory area. All
428 * memory-mapped registers associated with this peripheral should have an
429 * address between #TOP_ENGLISHBREAKFAST_ROM_CTRL_ROM_BASE_ADDR and
430 * `TOP_ENGLISHBREAKFAST_ROM_CTRL_ROM_BASE_ADDR + TOP_ENGLISHBREAKFAST_ROM_CTRL_ROM_SIZE_BYTES`.
431 */
432#define TOP_ENGLISHBREAKFAST_ROM_CTRL_ROM_SIZE_BYTES 0x8000
433/**
434 * Peripheral base address for cfg device on rv_core_ibex in top englishbreakfast.
435 *
436 * This should be used with #mmio_region_from_addr to access the memory-mapped
437 * registers associated with the peripheral (usually via a DIF).
438 */
439#define TOP_ENGLISHBREAKFAST_RV_CORE_IBEX_CFG_BASE_ADDR 0x411F0000
440
441/**
442 * Peripheral size for cfg device on rv_core_ibex in top englishbreakfast.
443 *
444 * This is the size (in bytes) of the peripheral's reserved memory area. All
445 * memory-mapped registers associated with this peripheral should have an
446 * address between #TOP_ENGLISHBREAKFAST_RV_CORE_IBEX_CFG_BASE_ADDR and
447 * `TOP_ENGLISHBREAKFAST_RV_CORE_IBEX_CFG_BASE_ADDR + TOP_ENGLISHBREAKFAST_RV_CORE_IBEX_CFG_SIZE_BYTES`.
448 */
449#define TOP_ENGLISHBREAKFAST_RV_CORE_IBEX_CFG_SIZE_BYTES 0x100
450
451/**
452 * MMIO Region
453 *
454 * MMIO region excludes any memory that is separate from the module
455 * configuration space, i.e. ROM, main SRAM, and flash are excluded but
456 * retention SRAM, spi_device memory, or usbdev memory are included.
457 */
458#define TOP_ENGLISHBREAKFAST_MMIO_BASE_ADDR 0x40000000
459#define TOP_ENGLISHBREAKFAST_MMIO_SIZE_BYTES 0x10000000
460
461#endif // __ASSEMBLER__
462
463#endif // OPENTITAN_HW_TOP_ENGLISHBREAKFAST_SW_AUTOGEN_TOP_ENGLISHBREAKFAST_MEMORY_H_