Software APIs
top_earlgrey_memory.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------//
6// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
7// util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson
8// -o hw/top_earlgrey
9
10#ifndef OPENTITAN_HW_TOP_EARLGREY_SW_AUTOGEN_TOP_EARLGREY_MEMORY_H_
11#define OPENTITAN_HW_TOP_EARLGREY_SW_AUTOGEN_TOP_EARLGREY_MEMORY_H_
12
13/**
14 * @file
15 * @brief Assembler-only Top-Specific Definitions.
16 *
17 * This file contains preprocessor definitions for use within assembly code.
18 *
19 * These are not shared with C/C++ code because these are only allowed to be
20 * preprocessor definitions, no data or type declarations are allowed. The
21 * assembler is also stricter about literals (not allowing suffixes for
22 * signed/unsigned which are sensible to use for unsigned values in C/C++).
23 */
24
25// Include guard for assembler
26#ifdef __ASSEMBLER__
27/**
28 * Memory base for sram_ctrl_ret_aon_ram_ret_aon in top earlgrey.
29 */
30#define TOP_EARLGREY_RAM_RET_AON_BASE_ADDR 0x40600000
31
32/**
33 * Memory size for sram_ctrl_ret_aon_ram_ret_aon in top earlgrey.
34 */
35#define TOP_EARLGREY_RAM_RET_AON_SIZE_BYTES 0x1000
36
37/**
38 * Memory base for flash_ctrl_eflash in top earlgrey.
39 */
40#define TOP_EARLGREY_EFLASH_BASE_ADDR 0x20000000
41
42/**
43 * Memory size for flash_ctrl_eflash in top earlgrey.
44 */
45#define TOP_EARLGREY_EFLASH_SIZE_BYTES 0x100000
46
47/**
48 * Memory base for sram_ctrl_main_ram_main in top earlgrey.
49 */
50#define TOP_EARLGREY_RAM_MAIN_BASE_ADDR 0x10000000
51
52/**
53 * Memory size for sram_ctrl_main_ram_main in top earlgrey.
54 */
55#define TOP_EARLGREY_RAM_MAIN_SIZE_BYTES 0x20000
56
57/**
58 * Memory base for rom_ctrl_rom in top earlgrey.
59 */
60#define TOP_EARLGREY_ROM_BASE_ADDR 0x00008000
61
62/**
63 * Memory size for rom_ctrl_rom in top earlgrey.
64 */
65#define TOP_EARLGREY_ROM_SIZE_BYTES 0x8000
66
67
68
69/**
70 * Peripheral base address for uart0 in top earlgrey.
71 *
72 * This should be used with #mmio_region_from_addr to access the memory-mapped
73 * registers associated with the peripheral (usually via a DIF).
74 */
75#define TOP_EARLGREY_UART0_BASE_ADDR 0x40000000
76
77/**
78 * Peripheral size for uart0 in top earlgrey.
79 *
80 * This is the size (in bytes) of the peripheral's reserved memory area. All
81 * memory-mapped registers associated with this peripheral should have an
82 * address between #TOP_EARLGREY_UART0_BASE_ADDR and
83 * `TOP_EARLGREY_UART0_BASE_ADDR + TOP_EARLGREY_UART0_SIZE_BYTES`.
84 */
85#define TOP_EARLGREY_UART0_SIZE_BYTES 0x40
86/**
87 * Peripheral base address for uart1 in top earlgrey.
88 *
89 * This should be used with #mmio_region_from_addr to access the memory-mapped
90 * registers associated with the peripheral (usually via a DIF).
91 */
92#define TOP_EARLGREY_UART1_BASE_ADDR 0x40010000
93
94/**
95 * Peripheral size for uart1 in top earlgrey.
96 *
97 * This is the size (in bytes) of the peripheral's reserved memory area. All
98 * memory-mapped registers associated with this peripheral should have an
99 * address between #TOP_EARLGREY_UART1_BASE_ADDR and
100 * `TOP_EARLGREY_UART1_BASE_ADDR + TOP_EARLGREY_UART1_SIZE_BYTES`.
101 */
102#define TOP_EARLGREY_UART1_SIZE_BYTES 0x40
103/**
104 * Peripheral base address for uart2 in top earlgrey.
105 *
106 * This should be used with #mmio_region_from_addr to access the memory-mapped
107 * registers associated with the peripheral (usually via a DIF).
108 */
109#define TOP_EARLGREY_UART2_BASE_ADDR 0x40020000
110
111/**
112 * Peripheral size for uart2 in top earlgrey.
113 *
114 * This is the size (in bytes) of the peripheral's reserved memory area. All
115 * memory-mapped registers associated with this peripheral should have an
116 * address between #TOP_EARLGREY_UART2_BASE_ADDR and
117 * `TOP_EARLGREY_UART2_BASE_ADDR + TOP_EARLGREY_UART2_SIZE_BYTES`.
118 */
119#define TOP_EARLGREY_UART2_SIZE_BYTES 0x40
120/**
121 * Peripheral base address for uart3 in top earlgrey.
122 *
123 * This should be used with #mmio_region_from_addr to access the memory-mapped
124 * registers associated with the peripheral (usually via a DIF).
125 */
126#define TOP_EARLGREY_UART3_BASE_ADDR 0x40030000
127
128/**
129 * Peripheral size for uart3 in top earlgrey.
130 *
131 * This is the size (in bytes) of the peripheral's reserved memory area. All
132 * memory-mapped registers associated with this peripheral should have an
133 * address between #TOP_EARLGREY_UART3_BASE_ADDR and
134 * `TOP_EARLGREY_UART3_BASE_ADDR + TOP_EARLGREY_UART3_SIZE_BYTES`.
135 */
136#define TOP_EARLGREY_UART3_SIZE_BYTES 0x40
137/**
138 * Peripheral base address for gpio in top earlgrey.
139 *
140 * This should be used with #mmio_region_from_addr to access the memory-mapped
141 * registers associated with the peripheral (usually via a DIF).
142 */
143#define TOP_EARLGREY_GPIO_BASE_ADDR 0x40040000
144
145/**
146 * Peripheral size for gpio in top earlgrey.
147 *
148 * This is the size (in bytes) of the peripheral's reserved memory area. All
149 * memory-mapped registers associated with this peripheral should have an
150 * address between #TOP_EARLGREY_GPIO_BASE_ADDR and
151 * `TOP_EARLGREY_GPIO_BASE_ADDR + TOP_EARLGREY_GPIO_SIZE_BYTES`.
152 */
153#define TOP_EARLGREY_GPIO_SIZE_BYTES 0x80
154/**
155 * Peripheral base address for spi_device in top earlgrey.
156 *
157 * This should be used with #mmio_region_from_addr to access the memory-mapped
158 * registers associated with the peripheral (usually via a DIF).
159 */
160#define TOP_EARLGREY_SPI_DEVICE_BASE_ADDR 0x40050000
161
162/**
163 * Peripheral size for spi_device in top earlgrey.
164 *
165 * This is the size (in bytes) of the peripheral's reserved memory area. All
166 * memory-mapped registers associated with this peripheral should have an
167 * address between #TOP_EARLGREY_SPI_DEVICE_BASE_ADDR and
168 * `TOP_EARLGREY_SPI_DEVICE_BASE_ADDR + TOP_EARLGREY_SPI_DEVICE_SIZE_BYTES`.
169 */
170#define TOP_EARLGREY_SPI_DEVICE_SIZE_BYTES 0x2000
171/**
172 * Peripheral base address for i2c0 in top earlgrey.
173 *
174 * This should be used with #mmio_region_from_addr to access the memory-mapped
175 * registers associated with the peripheral (usually via a DIF).
176 */
177#define TOP_EARLGREY_I2C0_BASE_ADDR 0x40080000
178
179/**
180 * Peripheral size for i2c0 in top earlgrey.
181 *
182 * This is the size (in bytes) of the peripheral's reserved memory area. All
183 * memory-mapped registers associated with this peripheral should have an
184 * address between #TOP_EARLGREY_I2C0_BASE_ADDR and
185 * `TOP_EARLGREY_I2C0_BASE_ADDR + TOP_EARLGREY_I2C0_SIZE_BYTES`.
186 */
187#define TOP_EARLGREY_I2C0_SIZE_BYTES 0x80
188/**
189 * Peripheral base address for i2c1 in top earlgrey.
190 *
191 * This should be used with #mmio_region_from_addr to access the memory-mapped
192 * registers associated with the peripheral (usually via a DIF).
193 */
194#define TOP_EARLGREY_I2C1_BASE_ADDR 0x40090000
195
196/**
197 * Peripheral size for i2c1 in top earlgrey.
198 *
199 * This is the size (in bytes) of the peripheral's reserved memory area. All
200 * memory-mapped registers associated with this peripheral should have an
201 * address between #TOP_EARLGREY_I2C1_BASE_ADDR and
202 * `TOP_EARLGREY_I2C1_BASE_ADDR + TOP_EARLGREY_I2C1_SIZE_BYTES`.
203 */
204#define TOP_EARLGREY_I2C1_SIZE_BYTES 0x80
205/**
206 * Peripheral base address for i2c2 in top earlgrey.
207 *
208 * This should be used with #mmio_region_from_addr to access the memory-mapped
209 * registers associated with the peripheral (usually via a DIF).
210 */
211#define TOP_EARLGREY_I2C2_BASE_ADDR 0x400A0000
212
213/**
214 * Peripheral size for i2c2 in top earlgrey.
215 *
216 * This is the size (in bytes) of the peripheral's reserved memory area. All
217 * memory-mapped registers associated with this peripheral should have an
218 * address between #TOP_EARLGREY_I2C2_BASE_ADDR and
219 * `TOP_EARLGREY_I2C2_BASE_ADDR + TOP_EARLGREY_I2C2_SIZE_BYTES`.
220 */
221#define TOP_EARLGREY_I2C2_SIZE_BYTES 0x80
222/**
223 * Peripheral base address for pattgen in top earlgrey.
224 *
225 * This should be used with #mmio_region_from_addr to access the memory-mapped
226 * registers associated with the peripheral (usually via a DIF).
227 */
228#define TOP_EARLGREY_PATTGEN_BASE_ADDR 0x400E0000
229
230/**
231 * Peripheral size for pattgen in top earlgrey.
232 *
233 * This is the size (in bytes) of the peripheral's reserved memory area. All
234 * memory-mapped registers associated with this peripheral should have an
235 * address between #TOP_EARLGREY_PATTGEN_BASE_ADDR and
236 * `TOP_EARLGREY_PATTGEN_BASE_ADDR + TOP_EARLGREY_PATTGEN_SIZE_BYTES`.
237 */
238#define TOP_EARLGREY_PATTGEN_SIZE_BYTES 0x40
239/**
240 * Peripheral base address for rv_timer in top earlgrey.
241 *
242 * This should be used with #mmio_region_from_addr to access the memory-mapped
243 * registers associated with the peripheral (usually via a DIF).
244 */
245#define TOP_EARLGREY_RV_TIMER_BASE_ADDR 0x40100000
246
247/**
248 * Peripheral size for rv_timer in top earlgrey.
249 *
250 * This is the size (in bytes) of the peripheral's reserved memory area. All
251 * memory-mapped registers associated with this peripheral should have an
252 * address between #TOP_EARLGREY_RV_TIMER_BASE_ADDR and
253 * `TOP_EARLGREY_RV_TIMER_BASE_ADDR + TOP_EARLGREY_RV_TIMER_SIZE_BYTES`.
254 */
255#define TOP_EARLGREY_RV_TIMER_SIZE_BYTES 0x200
256/**
257 * Peripheral base address for core device on otp_ctrl in top earlgrey.
258 *
259 * This should be used with #mmio_region_from_addr to access the memory-mapped
260 * registers associated with the peripheral (usually via a DIF).
261 */
262#define TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR 0x40130000
263
264/**
265 * Peripheral size for core device on otp_ctrl in top earlgrey.
266 *
267 * This is the size (in bytes) of the peripheral's reserved memory area. All
268 * memory-mapped registers associated with this peripheral should have an
269 * address between #TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR and
270 * `TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR + TOP_EARLGREY_OTP_CTRL_CORE_SIZE_BYTES`.
271 */
272#define TOP_EARLGREY_OTP_CTRL_CORE_SIZE_BYTES 0x1000
273/**
274 * Peripheral base address for otp_macro in top earlgrey.
275 *
276 * This should be used with #mmio_region_from_addr to access the memory-mapped
277 * registers associated with the peripheral (usually via a DIF).
278 */
279#define TOP_EARLGREY_OTP_MACRO_BASE_ADDR 0x40138000
280
281/**
282 * Peripheral size for otp_macro in top earlgrey.
283 *
284 * This is the size (in bytes) of the peripheral's reserved memory area. All
285 * memory-mapped registers associated with this peripheral should have an
286 * address between #TOP_EARLGREY_OTP_MACRO_BASE_ADDR and
287 * `TOP_EARLGREY_OTP_MACRO_BASE_ADDR + TOP_EARLGREY_OTP_MACRO_SIZE_BYTES`.
288 */
289#define TOP_EARLGREY_OTP_MACRO_SIZE_BYTES 0x20
290/**
291 * Peripheral base address for regs device on lc_ctrl in top earlgrey.
292 *
293 * This should be used with #mmio_region_from_addr to access the memory-mapped
294 * registers associated with the peripheral (usually via a DIF).
295 */
296#define TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR 0x40140000
297
298/**
299 * Peripheral size for regs device on lc_ctrl in top earlgrey.
300 *
301 * This is the size (in bytes) of the peripheral's reserved memory area. All
302 * memory-mapped registers associated with this peripheral should have an
303 * address between #TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR and
304 * `TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR + TOP_EARLGREY_LC_CTRL_REGS_SIZE_BYTES`.
305 */
306#define TOP_EARLGREY_LC_CTRL_REGS_SIZE_BYTES 0x100
307/**
308 * Peripheral base address for dmi device on lc_ctrl in top earlgrey.
309 *
310 * This should be used with #mmio_region_from_addr to access the memory-mapped
311 * registers associated with the peripheral (usually via a DIF).
312 */
313#define TOP_EARLGREY_LC_CTRL_DMI_BASE_ADDR 0x0
314
315/**
316 * Peripheral size for dmi device on lc_ctrl in top earlgrey.
317 *
318 * This is the size (in bytes) of the peripheral's reserved memory area. All
319 * memory-mapped registers associated with this peripheral should have an
320 * address between #TOP_EARLGREY_LC_CTRL_DMI_BASE_ADDR and
321 * `TOP_EARLGREY_LC_CTRL_DMI_BASE_ADDR + TOP_EARLGREY_LC_CTRL_DMI_SIZE_BYTES`.
322 */
323#define TOP_EARLGREY_LC_CTRL_DMI_SIZE_BYTES 0x1000
324/**
325 * Peripheral base address for alert_handler in top earlgrey.
326 *
327 * This should be used with #mmio_region_from_addr to access the memory-mapped
328 * registers associated with the peripheral (usually via a DIF).
329 */
330#define TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR 0x40150000
331
332/**
333 * Peripheral size for alert_handler in top earlgrey.
334 *
335 * This is the size (in bytes) of the peripheral's reserved memory area. All
336 * memory-mapped registers associated with this peripheral should have an
337 * address between #TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR and
338 * `TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR + TOP_EARLGREY_ALERT_HANDLER_SIZE_BYTES`.
339 */
340#define TOP_EARLGREY_ALERT_HANDLER_SIZE_BYTES 0x800
341/**
342 * Peripheral base address for spi_host0 in top earlgrey.
343 *
344 * This should be used with #mmio_region_from_addr to access the memory-mapped
345 * registers associated with the peripheral (usually via a DIF).
346 */
347#define TOP_EARLGREY_SPI_HOST0_BASE_ADDR 0x40300000
348
349/**
350 * Peripheral size for spi_host0 in top earlgrey.
351 *
352 * This is the size (in bytes) of the peripheral's reserved memory area. All
353 * memory-mapped registers associated with this peripheral should have an
354 * address between #TOP_EARLGREY_SPI_HOST0_BASE_ADDR and
355 * `TOP_EARLGREY_SPI_HOST0_BASE_ADDR + TOP_EARLGREY_SPI_HOST0_SIZE_BYTES`.
356 */
357#define TOP_EARLGREY_SPI_HOST0_SIZE_BYTES 0x40
358/**
359 * Peripheral base address for spi_host1 in top earlgrey.
360 *
361 * This should be used with #mmio_region_from_addr to access the memory-mapped
362 * registers associated with the peripheral (usually via a DIF).
363 */
364#define TOP_EARLGREY_SPI_HOST1_BASE_ADDR 0x40310000
365
366/**
367 * Peripheral size for spi_host1 in top earlgrey.
368 *
369 * This is the size (in bytes) of the peripheral's reserved memory area. All
370 * memory-mapped registers associated with this peripheral should have an
371 * address between #TOP_EARLGREY_SPI_HOST1_BASE_ADDR and
372 * `TOP_EARLGREY_SPI_HOST1_BASE_ADDR + TOP_EARLGREY_SPI_HOST1_SIZE_BYTES`.
373 */
374#define TOP_EARLGREY_SPI_HOST1_SIZE_BYTES 0x40
375/**
376 * Peripheral base address for usbdev in top earlgrey.
377 *
378 * This should be used with #mmio_region_from_addr to access the memory-mapped
379 * registers associated with the peripheral (usually via a DIF).
380 */
381#define TOP_EARLGREY_USBDEV_BASE_ADDR 0x40320000
382
383/**
384 * Peripheral size for usbdev in top earlgrey.
385 *
386 * This is the size (in bytes) of the peripheral's reserved memory area. All
387 * memory-mapped registers associated with this peripheral should have an
388 * address between #TOP_EARLGREY_USBDEV_BASE_ADDR and
389 * `TOP_EARLGREY_USBDEV_BASE_ADDR + TOP_EARLGREY_USBDEV_SIZE_BYTES`.
390 */
391#define TOP_EARLGREY_USBDEV_SIZE_BYTES 0x1000
392/**
393 * Peripheral base address for pwrmgr_aon in top earlgrey.
394 *
395 * This should be used with #mmio_region_from_addr to access the memory-mapped
396 * registers associated with the peripheral (usually via a DIF).
397 */
398#define TOP_EARLGREY_PWRMGR_AON_BASE_ADDR 0x40400000
399
400/**
401 * Peripheral size for pwrmgr_aon in top earlgrey.
402 *
403 * This is the size (in bytes) of the peripheral's reserved memory area. All
404 * memory-mapped registers associated with this peripheral should have an
405 * address between #TOP_EARLGREY_PWRMGR_AON_BASE_ADDR and
406 * `TOP_EARLGREY_PWRMGR_AON_BASE_ADDR + TOP_EARLGREY_PWRMGR_AON_SIZE_BYTES`.
407 */
408#define TOP_EARLGREY_PWRMGR_AON_SIZE_BYTES 0x80
409/**
410 * Peripheral base address for rstmgr_aon in top earlgrey.
411 *
412 * This should be used with #mmio_region_from_addr to access the memory-mapped
413 * registers associated with the peripheral (usually via a DIF).
414 */
415#define TOP_EARLGREY_RSTMGR_AON_BASE_ADDR 0x40410000
416
417/**
418 * Peripheral size for rstmgr_aon in top earlgrey.
419 *
420 * This is the size (in bytes) of the peripheral's reserved memory area. All
421 * memory-mapped registers associated with this peripheral should have an
422 * address between #TOP_EARLGREY_RSTMGR_AON_BASE_ADDR and
423 * `TOP_EARLGREY_RSTMGR_AON_BASE_ADDR + TOP_EARLGREY_RSTMGR_AON_SIZE_BYTES`.
424 */
425#define TOP_EARLGREY_RSTMGR_AON_SIZE_BYTES 0x80
426/**
427 * Peripheral base address for clkmgr_aon in top earlgrey.
428 *
429 * This should be used with #mmio_region_from_addr to access the memory-mapped
430 * registers associated with the peripheral (usually via a DIF).
431 */
432#define TOP_EARLGREY_CLKMGR_AON_BASE_ADDR 0x40420000
433
434/**
435 * Peripheral size for clkmgr_aon in top earlgrey.
436 *
437 * This is the size (in bytes) of the peripheral's reserved memory area. All
438 * memory-mapped registers associated with this peripheral should have an
439 * address between #TOP_EARLGREY_CLKMGR_AON_BASE_ADDR and
440 * `TOP_EARLGREY_CLKMGR_AON_BASE_ADDR + TOP_EARLGREY_CLKMGR_AON_SIZE_BYTES`.
441 */
442#define TOP_EARLGREY_CLKMGR_AON_SIZE_BYTES 0x80
443/**
444 * Peripheral base address for sysrst_ctrl_aon in top earlgrey.
445 *
446 * This should be used with #mmio_region_from_addr to access the memory-mapped
447 * registers associated with the peripheral (usually via a DIF).
448 */
449#define TOP_EARLGREY_SYSRST_CTRL_AON_BASE_ADDR 0x40430000
450
451/**
452 * Peripheral size for sysrst_ctrl_aon in top earlgrey.
453 *
454 * This is the size (in bytes) of the peripheral's reserved memory area. All
455 * memory-mapped registers associated with this peripheral should have an
456 * address between #TOP_EARLGREY_SYSRST_CTRL_AON_BASE_ADDR and
457 * `TOP_EARLGREY_SYSRST_CTRL_AON_BASE_ADDR + TOP_EARLGREY_SYSRST_CTRL_AON_SIZE_BYTES`.
458 */
459#define TOP_EARLGREY_SYSRST_CTRL_AON_SIZE_BYTES 0x100
460/**
461 * Peripheral base address for adc_ctrl_aon in top earlgrey.
462 *
463 * This should be used with #mmio_region_from_addr to access the memory-mapped
464 * registers associated with the peripheral (usually via a DIF).
465 */
466#define TOP_EARLGREY_ADC_CTRL_AON_BASE_ADDR 0x40440000
467
468/**
469 * Peripheral size for adc_ctrl_aon in top earlgrey.
470 *
471 * This is the size (in bytes) of the peripheral's reserved memory area. All
472 * memory-mapped registers associated with this peripheral should have an
473 * address between #TOP_EARLGREY_ADC_CTRL_AON_BASE_ADDR and
474 * `TOP_EARLGREY_ADC_CTRL_AON_BASE_ADDR + TOP_EARLGREY_ADC_CTRL_AON_SIZE_BYTES`.
475 */
476#define TOP_EARLGREY_ADC_CTRL_AON_SIZE_BYTES 0x80
477/**
478 * Peripheral base address for pwm_aon in top earlgrey.
479 *
480 * This should be used with #mmio_region_from_addr to access the memory-mapped
481 * registers associated with the peripheral (usually via a DIF).
482 */
483#define TOP_EARLGREY_PWM_AON_BASE_ADDR 0x40450000
484
485/**
486 * Peripheral size for pwm_aon in top earlgrey.
487 *
488 * This is the size (in bytes) of the peripheral's reserved memory area. All
489 * memory-mapped registers associated with this peripheral should have an
490 * address between #TOP_EARLGREY_PWM_AON_BASE_ADDR and
491 * `TOP_EARLGREY_PWM_AON_BASE_ADDR + TOP_EARLGREY_PWM_AON_SIZE_BYTES`.
492 */
493#define TOP_EARLGREY_PWM_AON_SIZE_BYTES 0x80
494/**
495 * Peripheral base address for pinmux_aon in top earlgrey.
496 *
497 * This should be used with #mmio_region_from_addr to access the memory-mapped
498 * registers associated with the peripheral (usually via a DIF).
499 */
500#define TOP_EARLGREY_PINMUX_AON_BASE_ADDR 0x40460000
501
502/**
503 * Peripheral size for pinmux_aon in top earlgrey.
504 *
505 * This is the size (in bytes) of the peripheral's reserved memory area. All
506 * memory-mapped registers associated with this peripheral should have an
507 * address between #TOP_EARLGREY_PINMUX_AON_BASE_ADDR and
508 * `TOP_EARLGREY_PINMUX_AON_BASE_ADDR + TOP_EARLGREY_PINMUX_AON_SIZE_BYTES`.
509 */
510#define TOP_EARLGREY_PINMUX_AON_SIZE_BYTES 0x1000
511/**
512 * Peripheral base address for aon_timer_aon in top earlgrey.
513 *
514 * This should be used with #mmio_region_from_addr to access the memory-mapped
515 * registers associated with the peripheral (usually via a DIF).
516 */
517#define TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR 0x40470000
518
519/**
520 * Peripheral size for aon_timer_aon in top earlgrey.
521 *
522 * This is the size (in bytes) of the peripheral's reserved memory area. All
523 * memory-mapped registers associated with this peripheral should have an
524 * address between #TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR and
525 * `TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR + TOP_EARLGREY_AON_TIMER_AON_SIZE_BYTES`.
526 */
527#define TOP_EARLGREY_AON_TIMER_AON_SIZE_BYTES 0x40
528/**
529 * Peripheral base address for ast in top earlgrey.
530 *
531 * This should be used with #mmio_region_from_addr to access the memory-mapped
532 * registers associated with the peripheral (usually via a DIF).
533 */
534#define TOP_EARLGREY_AST_BASE_ADDR 0x40480000
535
536/**
537 * Peripheral size for ast in top earlgrey.
538 *
539 * This is the size (in bytes) of the peripheral's reserved memory area. All
540 * memory-mapped registers associated with this peripheral should have an
541 * address between #TOP_EARLGREY_AST_BASE_ADDR and
542 * `TOP_EARLGREY_AST_BASE_ADDR + TOP_EARLGREY_AST_SIZE_BYTES`.
543 */
544#define TOP_EARLGREY_AST_SIZE_BYTES 0x400
545/**
546 * Peripheral base address for sensor_ctrl_aon in top earlgrey.
547 *
548 * This should be used with #mmio_region_from_addr to access the memory-mapped
549 * registers associated with the peripheral (usually via a DIF).
550 */
551#define TOP_EARLGREY_SENSOR_CTRL_AON_BASE_ADDR 0x40490000
552
553/**
554 * Peripheral size for sensor_ctrl_aon in top earlgrey.
555 *
556 * This is the size (in bytes) of the peripheral's reserved memory area. All
557 * memory-mapped registers associated with this peripheral should have an
558 * address between #TOP_EARLGREY_SENSOR_CTRL_AON_BASE_ADDR and
559 * `TOP_EARLGREY_SENSOR_CTRL_AON_BASE_ADDR + TOP_EARLGREY_SENSOR_CTRL_AON_SIZE_BYTES`.
560 */
561#define TOP_EARLGREY_SENSOR_CTRL_AON_SIZE_BYTES 0x80
562/**
563 * Peripheral base address for regs device on sram_ctrl_ret_aon in top earlgrey.
564 *
565 * This should be used with #mmio_region_from_addr to access the memory-mapped
566 * registers associated with the peripheral (usually via a DIF).
567 */
568#define TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR 0x40500000
569
570/**
571 * Peripheral size for regs device on sram_ctrl_ret_aon in top earlgrey.
572 *
573 * This is the size (in bytes) of the peripheral's reserved memory area. All
574 * memory-mapped registers associated with this peripheral should have an
575 * address between #TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR and
576 * `TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES`.
577 */
578#define TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES 0x40
579/**
580 * Peripheral base address for ram device on sram_ctrl_ret_aon in top earlgrey.
581 *
582 * This should be used with #mmio_region_from_addr to access the memory-mapped
583 * registers associated with the peripheral (usually via a DIF).
584 */
585#define TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_BASE_ADDR 0x40600000
586
587/**
588 * Peripheral size for ram device on sram_ctrl_ret_aon in top earlgrey.
589 *
590 * This is the size (in bytes) of the peripheral's reserved memory area. All
591 * memory-mapped registers associated with this peripheral should have an
592 * address between #TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_BASE_ADDR and
593 * `TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES`.
594 */
595#define TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES 0x1000
596/**
597 * Peripheral base address for core device on flash_ctrl in top earlgrey.
598 *
599 * This should be used with #mmio_region_from_addr to access the memory-mapped
600 * registers associated with the peripheral (usually via a DIF).
601 */
602#define TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR 0x41000000
603
604/**
605 * Peripheral size for core device on flash_ctrl in top earlgrey.
606 *
607 * This is the size (in bytes) of the peripheral's reserved memory area. All
608 * memory-mapped registers associated with this peripheral should have an
609 * address between #TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR and
610 * `TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR + TOP_EARLGREY_FLASH_CTRL_CORE_SIZE_BYTES`.
611 */
612#define TOP_EARLGREY_FLASH_CTRL_CORE_SIZE_BYTES 0x200
613/**
614 * Peripheral base address for prim device on flash_ctrl in top earlgrey.
615 *
616 * This should be used with #mmio_region_from_addr to access the memory-mapped
617 * registers associated with the peripheral (usually via a DIF).
618 */
619#define TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR 0x41008000
620
621/**
622 * Peripheral size for prim device on flash_ctrl in top earlgrey.
623 *
624 * This is the size (in bytes) of the peripheral's reserved memory area. All
625 * memory-mapped registers associated with this peripheral should have an
626 * address between #TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR and
627 * `TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR + TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES`.
628 */
629#define TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES 0x80
630/**
631 * Peripheral base address for mem device on flash_ctrl in top earlgrey.
632 *
633 * This should be used with #mmio_region_from_addr to access the memory-mapped
634 * registers associated with the peripheral (usually via a DIF).
635 */
636#define TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR 0x20000000
637
638/**
639 * Peripheral size for mem device on flash_ctrl in top earlgrey.
640 *
641 * This is the size (in bytes) of the peripheral's reserved memory area. All
642 * memory-mapped registers associated with this peripheral should have an
643 * address between #TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR and
644 * `TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR + TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES`.
645 */
646#define TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES 0x100000
647/**
648 * Peripheral base address for regs device on rv_dm in top earlgrey.
649 *
650 * This should be used with #mmio_region_from_addr to access the memory-mapped
651 * registers associated with the peripheral (usually via a DIF).
652 */
653#define TOP_EARLGREY_RV_DM_REGS_BASE_ADDR 0x41200000
654
655/**
656 * Peripheral size for regs device on rv_dm in top earlgrey.
657 *
658 * This is the size (in bytes) of the peripheral's reserved memory area. All
659 * memory-mapped registers associated with this peripheral should have an
660 * address between #TOP_EARLGREY_RV_DM_REGS_BASE_ADDR and
661 * `TOP_EARLGREY_RV_DM_REGS_BASE_ADDR + TOP_EARLGREY_RV_DM_REGS_SIZE_BYTES`.
662 */
663#define TOP_EARLGREY_RV_DM_REGS_SIZE_BYTES 0x10
664/**
665 * Peripheral base address for mem device on rv_dm in top earlgrey.
666 *
667 * This should be used with #mmio_region_from_addr to access the memory-mapped
668 * registers associated with the peripheral (usually via a DIF).
669 */
670#define TOP_EARLGREY_RV_DM_MEM_BASE_ADDR 0x10000
671
672/**
673 * Peripheral size for mem device on rv_dm in top earlgrey.
674 *
675 * This is the size (in bytes) of the peripheral's reserved memory area. All
676 * memory-mapped registers associated with this peripheral should have an
677 * address between #TOP_EARLGREY_RV_DM_MEM_BASE_ADDR and
678 * `TOP_EARLGREY_RV_DM_MEM_BASE_ADDR + TOP_EARLGREY_RV_DM_MEM_SIZE_BYTES`.
679 */
680#define TOP_EARLGREY_RV_DM_MEM_SIZE_BYTES 0x1000
681/**
682 * Peripheral base address for dbg device on rv_dm in top earlgrey.
683 *
684 * This should be used with #mmio_region_from_addr to access the memory-mapped
685 * registers associated with the peripheral (usually via a DIF).
686 */
687#define TOP_EARLGREY_RV_DM_DBG_BASE_ADDR 0x1000
688
689/**
690 * Peripheral size for dbg device on rv_dm in top earlgrey.
691 *
692 * This is the size (in bytes) of the peripheral's reserved memory area. All
693 * memory-mapped registers associated with this peripheral should have an
694 * address between #TOP_EARLGREY_RV_DM_DBG_BASE_ADDR and
695 * `TOP_EARLGREY_RV_DM_DBG_BASE_ADDR + TOP_EARLGREY_RV_DM_DBG_SIZE_BYTES`.
696 */
697#define TOP_EARLGREY_RV_DM_DBG_SIZE_BYTES 0x200
698/**
699 * Peripheral base address for rv_plic in top earlgrey.
700 *
701 * This should be used with #mmio_region_from_addr to access the memory-mapped
702 * registers associated with the peripheral (usually via a DIF).
703 */
704#define TOP_EARLGREY_RV_PLIC_BASE_ADDR 0x48000000
705
706/**
707 * Peripheral size for rv_plic in top earlgrey.
708 *
709 * This is the size (in bytes) of the peripheral's reserved memory area. All
710 * memory-mapped registers associated with this peripheral should have an
711 * address between #TOP_EARLGREY_RV_PLIC_BASE_ADDR and
712 * `TOP_EARLGREY_RV_PLIC_BASE_ADDR + TOP_EARLGREY_RV_PLIC_SIZE_BYTES`.
713 */
714#define TOP_EARLGREY_RV_PLIC_SIZE_BYTES 0x8000000
715/**
716 * Peripheral base address for aes in top earlgrey.
717 *
718 * This should be used with #mmio_region_from_addr to access the memory-mapped
719 * registers associated with the peripheral (usually via a DIF).
720 */
721#define TOP_EARLGREY_AES_BASE_ADDR 0x41100000
722
723/**
724 * Peripheral size for aes in top earlgrey.
725 *
726 * This is the size (in bytes) of the peripheral's reserved memory area. All
727 * memory-mapped registers associated with this peripheral should have an
728 * address between #TOP_EARLGREY_AES_BASE_ADDR and
729 * `TOP_EARLGREY_AES_BASE_ADDR + TOP_EARLGREY_AES_SIZE_BYTES`.
730 */
731#define TOP_EARLGREY_AES_SIZE_BYTES 0x100
732/**
733 * Peripheral base address for hmac in top earlgrey.
734 *
735 * This should be used with #mmio_region_from_addr to access the memory-mapped
736 * registers associated with the peripheral (usually via a DIF).
737 */
738#define TOP_EARLGREY_HMAC_BASE_ADDR 0x41110000
739
740/**
741 * Peripheral size for hmac in top earlgrey.
742 *
743 * This is the size (in bytes) of the peripheral's reserved memory area. All
744 * memory-mapped registers associated with this peripheral should have an
745 * address between #TOP_EARLGREY_HMAC_BASE_ADDR and
746 * `TOP_EARLGREY_HMAC_BASE_ADDR + TOP_EARLGREY_HMAC_SIZE_BYTES`.
747 */
748#define TOP_EARLGREY_HMAC_SIZE_BYTES 0x2000
749/**
750 * Peripheral base address for kmac in top earlgrey.
751 *
752 * This should be used with #mmio_region_from_addr to access the memory-mapped
753 * registers associated with the peripheral (usually via a DIF).
754 */
755#define TOP_EARLGREY_KMAC_BASE_ADDR 0x41120000
756
757/**
758 * Peripheral size for kmac in top earlgrey.
759 *
760 * This is the size (in bytes) of the peripheral's reserved memory area. All
761 * memory-mapped registers associated with this peripheral should have an
762 * address between #TOP_EARLGREY_KMAC_BASE_ADDR and
763 * `TOP_EARLGREY_KMAC_BASE_ADDR + TOP_EARLGREY_KMAC_SIZE_BYTES`.
764 */
765#define TOP_EARLGREY_KMAC_SIZE_BYTES 0x1000
766/**
767 * Peripheral base address for otbn in top earlgrey.
768 *
769 * This should be used with #mmio_region_from_addr to access the memory-mapped
770 * registers associated with the peripheral (usually via a DIF).
771 */
772#define TOP_EARLGREY_OTBN_BASE_ADDR 0x41130000
773
774/**
775 * Peripheral size for otbn in top earlgrey.
776 *
777 * This is the size (in bytes) of the peripheral's reserved memory area. All
778 * memory-mapped registers associated with this peripheral should have an
779 * address between #TOP_EARLGREY_OTBN_BASE_ADDR and
780 * `TOP_EARLGREY_OTBN_BASE_ADDR + TOP_EARLGREY_OTBN_SIZE_BYTES`.
781 */
782#define TOP_EARLGREY_OTBN_SIZE_BYTES 0x10000
783/**
784 * Peripheral base address for keymgr in top earlgrey.
785 *
786 * This should be used with #mmio_region_from_addr to access the memory-mapped
787 * registers associated with the peripheral (usually via a DIF).
788 */
789#define TOP_EARLGREY_KEYMGR_BASE_ADDR 0x41140000
790
791/**
792 * Peripheral size for keymgr in top earlgrey.
793 *
794 * This is the size (in bytes) of the peripheral's reserved memory area. All
795 * memory-mapped registers associated with this peripheral should have an
796 * address between #TOP_EARLGREY_KEYMGR_BASE_ADDR and
797 * `TOP_EARLGREY_KEYMGR_BASE_ADDR + TOP_EARLGREY_KEYMGR_SIZE_BYTES`.
798 */
799#define TOP_EARLGREY_KEYMGR_SIZE_BYTES 0x100
800/**
801 * Peripheral base address for csrng in top earlgrey.
802 *
803 * This should be used with #mmio_region_from_addr to access the memory-mapped
804 * registers associated with the peripheral (usually via a DIF).
805 */
806#define TOP_EARLGREY_CSRNG_BASE_ADDR 0x41150000
807
808/**
809 * Peripheral size for csrng in top earlgrey.
810 *
811 * This is the size (in bytes) of the peripheral's reserved memory area. All
812 * memory-mapped registers associated with this peripheral should have an
813 * address between #TOP_EARLGREY_CSRNG_BASE_ADDR and
814 * `TOP_EARLGREY_CSRNG_BASE_ADDR + TOP_EARLGREY_CSRNG_SIZE_BYTES`.
815 */
816#define TOP_EARLGREY_CSRNG_SIZE_BYTES 0x80
817/**
818 * Peripheral base address for entropy_src in top earlgrey.
819 *
820 * This should be used with #mmio_region_from_addr to access the memory-mapped
821 * registers associated with the peripheral (usually via a DIF).
822 */
823#define TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR 0x41160000
824
825/**
826 * Peripheral size for entropy_src in top earlgrey.
827 *
828 * This is the size (in bytes) of the peripheral's reserved memory area. All
829 * memory-mapped registers associated with this peripheral should have an
830 * address between #TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR and
831 * `TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR + TOP_EARLGREY_ENTROPY_SRC_SIZE_BYTES`.
832 */
833#define TOP_EARLGREY_ENTROPY_SRC_SIZE_BYTES 0x100
834/**
835 * Peripheral base address for edn0 in top earlgrey.
836 *
837 * This should be used with #mmio_region_from_addr to access the memory-mapped
838 * registers associated with the peripheral (usually via a DIF).
839 */
840#define TOP_EARLGREY_EDN0_BASE_ADDR 0x41170000
841
842/**
843 * Peripheral size for edn0 in top earlgrey.
844 *
845 * This is the size (in bytes) of the peripheral's reserved memory area. All
846 * memory-mapped registers associated with this peripheral should have an
847 * address between #TOP_EARLGREY_EDN0_BASE_ADDR and
848 * `TOP_EARLGREY_EDN0_BASE_ADDR + TOP_EARLGREY_EDN0_SIZE_BYTES`.
849 */
850#define TOP_EARLGREY_EDN0_SIZE_BYTES 0x80
851/**
852 * Peripheral base address for edn1 in top earlgrey.
853 *
854 * This should be used with #mmio_region_from_addr to access the memory-mapped
855 * registers associated with the peripheral (usually via a DIF).
856 */
857#define TOP_EARLGREY_EDN1_BASE_ADDR 0x41180000
858
859/**
860 * Peripheral size for edn1 in top earlgrey.
861 *
862 * This is the size (in bytes) of the peripheral's reserved memory area. All
863 * memory-mapped registers associated with this peripheral should have an
864 * address between #TOP_EARLGREY_EDN1_BASE_ADDR and
865 * `TOP_EARLGREY_EDN1_BASE_ADDR + TOP_EARLGREY_EDN1_SIZE_BYTES`.
866 */
867#define TOP_EARLGREY_EDN1_SIZE_BYTES 0x80
868/**
869 * Peripheral base address for regs device on sram_ctrl_main in top earlgrey.
870 *
871 * This should be used with #mmio_region_from_addr to access the memory-mapped
872 * registers associated with the peripheral (usually via a DIF).
873 */
874#define TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x411C0000
875
876/**
877 * Peripheral size for regs device on sram_ctrl_main in top earlgrey.
878 *
879 * This is the size (in bytes) of the peripheral's reserved memory area. All
880 * memory-mapped registers associated with this peripheral should have an
881 * address between #TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR and
882 * `TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_SIZE_BYTES`.
883 */
884#define TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x40
885/**
886 * Peripheral base address for ram device on sram_ctrl_main in top earlgrey.
887 *
888 * This should be used with #mmio_region_from_addr to access the memory-mapped
889 * registers associated with the peripheral (usually via a DIF).
890 */
891#define TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000
892
893/**
894 * Peripheral size for ram device on sram_ctrl_main in top earlgrey.
895 *
896 * This is the size (in bytes) of the peripheral's reserved memory area. All
897 * memory-mapped registers associated with this peripheral should have an
898 * address between #TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_BASE_ADDR and
899 * `TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_BASE_ADDR + TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_SIZE_BYTES`.
900 */
901#define TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x20000
902/**
903 * Peripheral base address for regs device on rom_ctrl in top earlgrey.
904 *
905 * This should be used with #mmio_region_from_addr to access the memory-mapped
906 * registers associated with the peripheral (usually via a DIF).
907 */
908#define TOP_EARLGREY_ROM_CTRL_REGS_BASE_ADDR 0x411E0000
909
910/**
911 * Peripheral size for regs device on rom_ctrl in top earlgrey.
912 *
913 * This is the size (in bytes) of the peripheral's reserved memory area. All
914 * memory-mapped registers associated with this peripheral should have an
915 * address between #TOP_EARLGREY_ROM_CTRL_REGS_BASE_ADDR and
916 * `TOP_EARLGREY_ROM_CTRL_REGS_BASE_ADDR + TOP_EARLGREY_ROM_CTRL_REGS_SIZE_BYTES`.
917 */
918#define TOP_EARLGREY_ROM_CTRL_REGS_SIZE_BYTES 0x80
919/**
920 * Peripheral base address for rom device on rom_ctrl in top earlgrey.
921 *
922 * This should be used with #mmio_region_from_addr to access the memory-mapped
923 * registers associated with the peripheral (usually via a DIF).
924 */
925#define TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR 0x8000
926
927/**
928 * Peripheral size for rom device on rom_ctrl in top earlgrey.
929 *
930 * This is the size (in bytes) of the peripheral's reserved memory area. All
931 * memory-mapped registers associated with this peripheral should have an
932 * address between #TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR and
933 * `TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR + TOP_EARLGREY_ROM_CTRL_ROM_SIZE_BYTES`.
934 */
935#define TOP_EARLGREY_ROM_CTRL_ROM_SIZE_BYTES 0x8000
936/**
937 * Peripheral base address for cfg device on rv_core_ibex in top earlgrey.
938 *
939 * This should be used with #mmio_region_from_addr to access the memory-mapped
940 * registers associated with the peripheral (usually via a DIF).
941 */
942#define TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR 0x411F0000
943
944/**
945 * Peripheral size for cfg device on rv_core_ibex in top earlgrey.
946 *
947 * This is the size (in bytes) of the peripheral's reserved memory area. All
948 * memory-mapped registers associated with this peripheral should have an
949 * address between #TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR and
950 * `TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR + TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES`.
951 */
952#define TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES 0x100
953
954/**
955 * MMIO Region
956 *
957 * MMIO region excludes any memory that is separate from the module
958 * configuration space, i.e. ROM, main SRAM, and flash are excluded but
959 * retention SRAM, spi_device memory, or usbdev memory are included.
960 */
961#define TOP_EARLGREY_MMIO_BASE_ADDR 0x40000000
962#define TOP_EARLGREY_MMIO_SIZE_BYTES 0x10000000
963
964#endif // __ASSEMBLER__
965
966#endif // OPENTITAN_HW_TOP_EARLGREY_SW_AUTOGEN_TOP_EARLGREY_MEMORY_H_