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10#ifndef OPENTITAN_HW_TOP_EARLGREY_SW_AUTOGEN_TOP_EARLGREY_MEMORY_H_
11#define OPENTITAN_HW_TOP_EARLGREY_SW_AUTOGEN_TOP_EARLGREY_MEMORY_H_
30#define TOP_EARLGREY_RAM_RET_AON_BASE_ADDR 0x40600000
35#define TOP_EARLGREY_RAM_RET_AON_SIZE_BYTES 0x1000
40#define TOP_EARLGREY_EFLASH_BASE_ADDR 0x20000000
45#define TOP_EARLGREY_EFLASH_SIZE_BYTES 0x100000
50#define TOP_EARLGREY_RAM_MAIN_BASE_ADDR 0x10000000
55#define TOP_EARLGREY_RAM_MAIN_SIZE_BYTES 0x20000
60#define TOP_EARLGREY_ROM_BASE_ADDR 0x00008000
65#define TOP_EARLGREY_ROM_SIZE_BYTES 0x8000
75#define TOP_EARLGREY_UART0_BASE_ADDR 0x40000000
85#define TOP_EARLGREY_UART0_SIZE_BYTES 0x40
92#define TOP_EARLGREY_UART1_BASE_ADDR 0x40010000
102#define TOP_EARLGREY_UART1_SIZE_BYTES 0x40
109#define TOP_EARLGREY_UART2_BASE_ADDR 0x40020000
119#define TOP_EARLGREY_UART2_SIZE_BYTES 0x40
126#define TOP_EARLGREY_UART3_BASE_ADDR 0x40030000
136#define TOP_EARLGREY_UART3_SIZE_BYTES 0x40
143#define TOP_EARLGREY_GPIO_BASE_ADDR 0x40040000
153#define TOP_EARLGREY_GPIO_SIZE_BYTES 0x80
160#define TOP_EARLGREY_SPI_DEVICE_BASE_ADDR 0x40050000
170#define TOP_EARLGREY_SPI_DEVICE_SIZE_BYTES 0x2000
177#define TOP_EARLGREY_I2C0_BASE_ADDR 0x40080000
187#define TOP_EARLGREY_I2C0_SIZE_BYTES 0x80
194#define TOP_EARLGREY_I2C1_BASE_ADDR 0x40090000
204#define TOP_EARLGREY_I2C1_SIZE_BYTES 0x80
211#define TOP_EARLGREY_I2C2_BASE_ADDR 0x400A0000
221#define TOP_EARLGREY_I2C2_SIZE_BYTES 0x80
228#define TOP_EARLGREY_PATTGEN_BASE_ADDR 0x400E0000
238#define TOP_EARLGREY_PATTGEN_SIZE_BYTES 0x40
245#define TOP_EARLGREY_RV_TIMER_BASE_ADDR 0x40100000
255#define TOP_EARLGREY_RV_TIMER_SIZE_BYTES 0x200
262#define TOP_EARLGREY_OTP_CTRL_CORE_BASE_ADDR 0x40130000
272#define TOP_EARLGREY_OTP_CTRL_CORE_SIZE_BYTES 0x1000
279#define TOP_EARLGREY_OTP_MACRO_BASE_ADDR 0x40138000
289#define TOP_EARLGREY_OTP_MACRO_SIZE_BYTES 0x20
296#define TOP_EARLGREY_LC_CTRL_REGS_BASE_ADDR 0x40140000
306#define TOP_EARLGREY_LC_CTRL_REGS_SIZE_BYTES 0x100
313#define TOP_EARLGREY_LC_CTRL_DMI_BASE_ADDR 0x0
323#define TOP_EARLGREY_LC_CTRL_DMI_SIZE_BYTES 0x1000
330#define TOP_EARLGREY_ALERT_HANDLER_BASE_ADDR 0x40150000
340#define TOP_EARLGREY_ALERT_HANDLER_SIZE_BYTES 0x800
347#define TOP_EARLGREY_SPI_HOST0_BASE_ADDR 0x40300000
357#define TOP_EARLGREY_SPI_HOST0_SIZE_BYTES 0x40
364#define TOP_EARLGREY_SPI_HOST1_BASE_ADDR 0x40310000
374#define TOP_EARLGREY_SPI_HOST1_SIZE_BYTES 0x40
381#define TOP_EARLGREY_USBDEV_BASE_ADDR 0x40320000
391#define TOP_EARLGREY_USBDEV_SIZE_BYTES 0x1000
398#define TOP_EARLGREY_PWRMGR_AON_BASE_ADDR 0x40400000
408#define TOP_EARLGREY_PWRMGR_AON_SIZE_BYTES 0x80
415#define TOP_EARLGREY_RSTMGR_AON_BASE_ADDR 0x40410000
425#define TOP_EARLGREY_RSTMGR_AON_SIZE_BYTES 0x80
432#define TOP_EARLGREY_CLKMGR_AON_BASE_ADDR 0x40420000
442#define TOP_EARLGREY_CLKMGR_AON_SIZE_BYTES 0x80
449#define TOP_EARLGREY_SYSRST_CTRL_AON_BASE_ADDR 0x40430000
459#define TOP_EARLGREY_SYSRST_CTRL_AON_SIZE_BYTES 0x100
466#define TOP_EARLGREY_ADC_CTRL_AON_BASE_ADDR 0x40440000
476#define TOP_EARLGREY_ADC_CTRL_AON_SIZE_BYTES 0x80
483#define TOP_EARLGREY_PWM_AON_BASE_ADDR 0x40450000
493#define TOP_EARLGREY_PWM_AON_SIZE_BYTES 0x80
500#define TOP_EARLGREY_PINMUX_AON_BASE_ADDR 0x40460000
510#define TOP_EARLGREY_PINMUX_AON_SIZE_BYTES 0x1000
517#define TOP_EARLGREY_AON_TIMER_AON_BASE_ADDR 0x40470000
527#define TOP_EARLGREY_AON_TIMER_AON_SIZE_BYTES 0x40
534#define TOP_EARLGREY_AST_BASE_ADDR 0x40480000
544#define TOP_EARLGREY_AST_SIZE_BYTES 0x400
551#define TOP_EARLGREY_SENSOR_CTRL_AON_BASE_ADDR 0x40490000
561#define TOP_EARLGREY_SENSOR_CTRL_AON_SIZE_BYTES 0x80
568#define TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_BASE_ADDR 0x40500000
578#define TOP_EARLGREY_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES 0x40
585#define TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_BASE_ADDR 0x40600000
595#define TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES 0x1000
602#define TOP_EARLGREY_FLASH_CTRL_CORE_BASE_ADDR 0x41000000
612#define TOP_EARLGREY_FLASH_CTRL_CORE_SIZE_BYTES 0x200
619#define TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR 0x41008000
629#define TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES 0x80
636#define TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR 0x20000000
646#define TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES 0x100000
653#define TOP_EARLGREY_RV_DM_REGS_BASE_ADDR 0x41200000
663#define TOP_EARLGREY_RV_DM_REGS_SIZE_BYTES 0x10
670#define TOP_EARLGREY_RV_DM_MEM_BASE_ADDR 0x10000
680#define TOP_EARLGREY_RV_DM_MEM_SIZE_BYTES 0x1000
687#define TOP_EARLGREY_RV_DM_DBG_BASE_ADDR 0x1000
697#define TOP_EARLGREY_RV_DM_DBG_SIZE_BYTES 0x200
704#define TOP_EARLGREY_RV_PLIC_BASE_ADDR 0x48000000
714#define TOP_EARLGREY_RV_PLIC_SIZE_BYTES 0x8000000
721#define TOP_EARLGREY_AES_BASE_ADDR 0x41100000
731#define TOP_EARLGREY_AES_SIZE_BYTES 0x100
738#define TOP_EARLGREY_HMAC_BASE_ADDR 0x41110000
748#define TOP_EARLGREY_HMAC_SIZE_BYTES 0x2000
755#define TOP_EARLGREY_KMAC_BASE_ADDR 0x41120000
765#define TOP_EARLGREY_KMAC_SIZE_BYTES 0x1000
772#define TOP_EARLGREY_OTBN_BASE_ADDR 0x41130000
782#define TOP_EARLGREY_OTBN_SIZE_BYTES 0x10000
789#define TOP_EARLGREY_KEYMGR_BASE_ADDR 0x41140000
799#define TOP_EARLGREY_KEYMGR_SIZE_BYTES 0x100
806#define TOP_EARLGREY_CSRNG_BASE_ADDR 0x41150000
816#define TOP_EARLGREY_CSRNG_SIZE_BYTES 0x80
823#define TOP_EARLGREY_ENTROPY_SRC_BASE_ADDR 0x41160000
833#define TOP_EARLGREY_ENTROPY_SRC_SIZE_BYTES 0x100
840#define TOP_EARLGREY_EDN0_BASE_ADDR 0x41170000
850#define TOP_EARLGREY_EDN0_SIZE_BYTES 0x80
857#define TOP_EARLGREY_EDN1_BASE_ADDR 0x41180000
867#define TOP_EARLGREY_EDN1_SIZE_BYTES 0x80
874#define TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x411C0000
884#define TOP_EARLGREY_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x40
891#define TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000
901#define TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x20000
908#define TOP_EARLGREY_ROM_CTRL_REGS_BASE_ADDR 0x411E0000
918#define TOP_EARLGREY_ROM_CTRL_REGS_SIZE_BYTES 0x80
925#define TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR 0x8000
935#define TOP_EARLGREY_ROM_CTRL_ROM_SIZE_BYTES 0x8000
942#define TOP_EARLGREY_RV_CORE_IBEX_CFG_BASE_ADDR 0x411F0000
952#define TOP_EARLGREY_RV_CORE_IBEX_CFG_SIZE_BYTES 0x100
961#define TOP_EARLGREY_MMIO_BASE_ADDR 0x40000000
962#define TOP_EARLGREY_MMIO_SIZE_BYTES 0x10000000