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10#ifndef OPENTITAN_HW_TOP_DARJEELING_SW_AUTOGEN_TOP_DARJEELING_MEMORY_H_
11#define OPENTITAN_HW_TOP_DARJEELING_SW_AUTOGEN_TOP_DARJEELING_MEMORY_H_
31#define TOP_DARJEELING_SOC_PROXY_CTN_BASE_ADDR 0x40000000
36#define TOP_DARJEELING_SOC_PROXY_CTN_SIZE_BYTES 0x80000000
41#define TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_BASE_ADDR 0x30600000
46#define TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_SIZE_BYTES 0x1000
51#define TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_BASE_ADDR 0x10000000
56#define TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_SIZE_BYTES 0x10000
61#define TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_BASE_ADDR 0x11000000
66#define TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_SIZE_BYTES 0x1000
71#define TOP_DARJEELING_ROM_CTRL0_ROM_BASE_ADDR 0x8000
76#define TOP_DARJEELING_ROM_CTRL0_ROM_SIZE_BYTES 0x8000
81#define TOP_DARJEELING_ROM_CTRL1_ROM_BASE_ADDR 0x20000
86#define TOP_DARJEELING_ROM_CTRL1_ROM_SIZE_BYTES 0x10000
95#define TOP_DARJEELING_UART0_BASE_ADDR 0x30010000
105#define TOP_DARJEELING_UART0_SIZE_BYTES 0x40
112#define TOP_DARJEELING_GPIO_BASE_ADDR 0x30000000
122#define TOP_DARJEELING_GPIO_SIZE_BYTES 0x100
129#define TOP_DARJEELING_SPI_DEVICE_BASE_ADDR 0x30310000
139#define TOP_DARJEELING_SPI_DEVICE_SIZE_BYTES 0x2000
146#define TOP_DARJEELING_I2C0_BASE_ADDR 0x30080000
156#define TOP_DARJEELING_I2C0_SIZE_BYTES 0x80
163#define TOP_DARJEELING_RV_TIMER_BASE_ADDR 0x30100000
173#define TOP_DARJEELING_RV_TIMER_SIZE_BYTES 0x200
180#define TOP_DARJEELING_OTP_CTRL_CORE_BASE_ADDR 0x30130000
190#define TOP_DARJEELING_OTP_CTRL_CORE_SIZE_BYTES 0x8000
197#define TOP_DARJEELING_OTP_MACRO_PRIM_BASE_ADDR 0x30140000
207#define TOP_DARJEELING_OTP_MACRO_PRIM_SIZE_BYTES 0x20
214#define TOP_DARJEELING_LC_CTRL_REGS_BASE_ADDR 0x30150000
224#define TOP_DARJEELING_LC_CTRL_REGS_SIZE_BYTES 0x100
231#define TOP_DARJEELING_ALERT_HANDLER_BASE_ADDR 0x30160000
241#define TOP_DARJEELING_ALERT_HANDLER_SIZE_BYTES 0x800
248#define TOP_DARJEELING_SPI_HOST0_BASE_ADDR 0x30300000
258#define TOP_DARJEELING_SPI_HOST0_SIZE_BYTES 0x40
265#define TOP_DARJEELING_PWRMGR_AON_BASE_ADDR 0x30400000
275#define TOP_DARJEELING_PWRMGR_AON_SIZE_BYTES 0x80
282#define TOP_DARJEELING_RSTMGR_AON_BASE_ADDR 0x30410000
292#define TOP_DARJEELING_RSTMGR_AON_SIZE_BYTES 0x80
299#define TOP_DARJEELING_CLKMGR_AON_BASE_ADDR 0x30420000
309#define TOP_DARJEELING_CLKMGR_AON_SIZE_BYTES 0x40
316#define TOP_DARJEELING_PINMUX_AON_BASE_ADDR 0x30460000
326#define TOP_DARJEELING_PINMUX_AON_SIZE_BYTES 0x800
333#define TOP_DARJEELING_AON_TIMER_AON_BASE_ADDR 0x30470000
343#define TOP_DARJEELING_AON_TIMER_AON_SIZE_BYTES 0x40
350#define TOP_DARJEELING_AST_BASE_ADDR 0x30480000
360#define TOP_DARJEELING_AST_SIZE_BYTES 0x400
367#define TOP_DARJEELING_SOC_PROXY_CORE_BASE_ADDR 0x22030000
377#define TOP_DARJEELING_SOC_PROXY_CORE_SIZE_BYTES 0x10
384#define TOP_DARJEELING_SRAM_CTRL_RET_AON_REGS_BASE_ADDR 0x30500000
394#define TOP_DARJEELING_SRAM_CTRL_RET_AON_REGS_SIZE_BYTES 0x40
401#define TOP_DARJEELING_RV_DM_REGS_BASE_ADDR 0x21200000
411#define TOP_DARJEELING_RV_DM_REGS_SIZE_BYTES 0x10
418#define TOP_DARJEELING_RV_DM_MEM_BASE_ADDR 0x40000
428#define TOP_DARJEELING_RV_DM_MEM_SIZE_BYTES 0x1000
435#define TOP_DARJEELING_RV_PLIC_BASE_ADDR 0x28000000
445#define TOP_DARJEELING_RV_PLIC_SIZE_BYTES 0x8000000
452#define TOP_DARJEELING_AES_BASE_ADDR 0x21100000
462#define TOP_DARJEELING_AES_SIZE_BYTES 0x100
469#define TOP_DARJEELING_HMAC_BASE_ADDR 0x21110000
479#define TOP_DARJEELING_HMAC_SIZE_BYTES 0x2000
486#define TOP_DARJEELING_KMAC_BASE_ADDR 0x21120000
496#define TOP_DARJEELING_KMAC_SIZE_BYTES 0x1000
503#define TOP_DARJEELING_OTBN_BASE_ADDR 0x21130000
513#define TOP_DARJEELING_OTBN_SIZE_BYTES 0x10000
520#define TOP_DARJEELING_KEYMGR_DPE_BASE_ADDR 0x21140000
530#define TOP_DARJEELING_KEYMGR_DPE_SIZE_BYTES 0x100
537#define TOP_DARJEELING_CSRNG_BASE_ADDR 0x21150000
547#define TOP_DARJEELING_CSRNG_SIZE_BYTES 0x80
554#define TOP_DARJEELING_ENTROPY_SRC_BASE_ADDR 0x21160000
564#define TOP_DARJEELING_ENTROPY_SRC_SIZE_BYTES 0x100
571#define TOP_DARJEELING_EDN0_BASE_ADDR 0x21170000
581#define TOP_DARJEELING_EDN0_SIZE_BYTES 0x80
588#define TOP_DARJEELING_EDN1_BASE_ADDR 0x21180000
598#define TOP_DARJEELING_EDN1_SIZE_BYTES 0x80
605#define TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_BASE_ADDR 0x211C0000
615#define TOP_DARJEELING_SRAM_CTRL_MAIN_REGS_SIZE_BYTES 0x40
622#define TOP_DARJEELING_SRAM_CTRL_MBOX_REGS_BASE_ADDR 0x211D0000
632#define TOP_DARJEELING_SRAM_CTRL_MBOX_REGS_SIZE_BYTES 0x40
639#define TOP_DARJEELING_ROM_CTRL0_REGS_BASE_ADDR 0x211E0000
649#define TOP_DARJEELING_ROM_CTRL0_REGS_SIZE_BYTES 0x80
656#define TOP_DARJEELING_ROM_CTRL1_REGS_BASE_ADDR 0x211E1000
666#define TOP_DARJEELING_ROM_CTRL1_REGS_SIZE_BYTES 0x80
673#define TOP_DARJEELING_DMA_BASE_ADDR 0x22010000
683#define TOP_DARJEELING_DMA_SIZE_BYTES 0x200
690#define TOP_DARJEELING_MBX0_CORE_BASE_ADDR 0x22000000
700#define TOP_DARJEELING_MBX0_CORE_SIZE_BYTES 0x80
707#define TOP_DARJEELING_MBX1_CORE_BASE_ADDR 0x22000100
717#define TOP_DARJEELING_MBX1_CORE_SIZE_BYTES 0x80
724#define TOP_DARJEELING_MBX2_CORE_BASE_ADDR 0x22000200
734#define TOP_DARJEELING_MBX2_CORE_SIZE_BYTES 0x80
741#define TOP_DARJEELING_MBX3_CORE_BASE_ADDR 0x22000300
751#define TOP_DARJEELING_MBX3_CORE_SIZE_BYTES 0x80
758#define TOP_DARJEELING_MBX4_CORE_BASE_ADDR 0x22000400
768#define TOP_DARJEELING_MBX4_CORE_SIZE_BYTES 0x80
775#define TOP_DARJEELING_MBX5_CORE_BASE_ADDR 0x22000500
785#define TOP_DARJEELING_MBX5_CORE_SIZE_BYTES 0x80
792#define TOP_DARJEELING_MBX6_CORE_BASE_ADDR 0x22000600
802#define TOP_DARJEELING_MBX6_CORE_SIZE_BYTES 0x80
809#define TOP_DARJEELING_MBX_JTAG_CORE_BASE_ADDR 0x22000800
819#define TOP_DARJEELING_MBX_JTAG_CORE_SIZE_BYTES 0x80
826#define TOP_DARJEELING_MBX_PCIE0_CORE_BASE_ADDR 0x22040000
836#define TOP_DARJEELING_MBX_PCIE0_CORE_SIZE_BYTES 0x80
843#define TOP_DARJEELING_MBX_PCIE1_CORE_BASE_ADDR 0x22040100
853#define TOP_DARJEELING_MBX_PCIE1_CORE_SIZE_BYTES 0x80
860#define TOP_DARJEELING_SOC_DBG_CTRL_CORE_BASE_ADDR 0x30170000
870#define TOP_DARJEELING_SOC_DBG_CTRL_CORE_SIZE_BYTES 0x20
877#define TOP_DARJEELING_RV_CORE_IBEX_CFG_BASE_ADDR 0x211F0000
887#define TOP_DARJEELING_RV_CORE_IBEX_CFG_SIZE_BYTES 0x800
896#define TOP_DARJEELING_MMIO_BASE_ADDR 0x21100000
897#define TOP_DARJEELING_MMIO_SIZE_BYTES 0xF501000