sysrst_ctrl_regs.h

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/**
 * @file
 * @brief Generated register defines for sysrst_ctrl
 */
 
// Copyright information found in source file:
// Copyright lowRISC contributors (OpenTitan project).
 
// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#ifndef _SYSRST_CTRL_REG_DEFS_
#define _SYSRST_CTRL_REG_DEFS_
 
#ifdef __cplusplus
extern "C" {
#endif
// Number of keyboard combos
#define SYSRST_CTRL_PARAM_NUM_COMBO 4
 
// Number of keys that can trigger interrupts
#define SYSRST_CTRL_PARAM_NUM_KEY_INTR 7
 
// Number of timer bits
#define SYSRST_CTRL_PARAM_TIMER_WIDTH 16
 
// Number of detection timer bits
#define SYSRST_CTRL_PARAM_DET_TIMER_WIDTH 32
 
// Number of alerts
#define SYSRST_CTRL_PARAM_NUM_ALERTS 1
 
// Register width
#define SYSRST_CTRL_PARAM_REG_WIDTH 32
 
// Common Interrupt Offsets
#define SYSRST_CTRL_INTR_COMMON_EVENT_DETECTED_BIT 0
 
// Interrupt State Register
#define SYSRST_CTRL_INTR_STATE_REG_OFFSET 0x0
#define SYSRST_CTRL_INTR_STATE_REG_RESVAL 0x0u
#define SYSRST_CTRL_INTR_STATE_EVENT_DETECTED_BIT 0
 
// Interrupt Enable Register
#define SYSRST_CTRL_INTR_ENABLE_REG_OFFSET 0x4
#define SYSRST_CTRL_INTR_ENABLE_REG_RESVAL 0x0u
#define SYSRST_CTRL_INTR_ENABLE_EVENT_DETECTED_BIT 0
 
// Interrupt Test Register
#define SYSRST_CTRL_INTR_TEST_REG_OFFSET 0x8
#define SYSRST_CTRL_INTR_TEST_REG_RESVAL 0x0u
#define SYSRST_CTRL_INTR_TEST_EVENT_DETECTED_BIT 0
 
// Alert Test Register
#define SYSRST_CTRL_ALERT_TEST_REG_OFFSET 0xc
#define SYSRST_CTRL_ALERT_TEST_REG_RESVAL 0x0u
#define SYSRST_CTRL_ALERT_TEST_FATAL_FAULT_BIT 0
 
// Configuration write enable control register
#define SYSRST_CTRL_REGWEN_REG_OFFSET 0x10
#define SYSRST_CTRL_REGWEN_REG_RESVAL 0x1u
#define SYSRST_CTRL_REGWEN_WRITE_EN_BIT 0
 
// EC reset control register
#define SYSRST_CTRL_EC_RST_CTL_REG_OFFSET 0x14
#define SYSRST_CTRL_EC_RST_CTL_REG_RESVAL 0x7d0u
#define SYSRST_CTRL_EC_RST_CTL_EC_RST_PULSE_MASK 0xffffu
#define SYSRST_CTRL_EC_RST_CTL_EC_RST_PULSE_OFFSET 0
#define SYSRST_CTRL_EC_RST_CTL_EC_RST_PULSE_FIELD \
  ((bitfield_field32_t) { .mask = SYSRST_CTRL_EC_RST_CTL_EC_RST_PULSE_MASK, .index = SYSRST_CTRL_EC_RST_CTL_EC_RST_PULSE_OFFSET })
 
// Ultra low power AC debounce control register
#define SYSRST_CTRL_ULP_AC_DEBOUNCE_CTL_REG_OFFSET 0x18
#define SYSRST_CTRL_ULP_AC_DEBOUNCE_CTL_REG_RESVAL 0x1f40u
#define SYSRST_CTRL_ULP_AC_DEBOUNCE_CTL_ULP_AC_DEBOUNCE_TIMER_MASK 0xffffu
#define SYSRST_CTRL_ULP_AC_DEBOUNCE_CTL_ULP_AC_DEBOUNCE_TIMER_OFFSET 0
#define SYSRST_CTRL_ULP_AC_DEBOUNCE_CTL_ULP_AC_DEBOUNCE_TIMER_FIELD \
  ((bitfield_field32_t) { .mask = SYSRST_CTRL_ULP_AC_DEBOUNCE_CTL_ULP_AC_DEBOUNCE_TIMER_MASK, .index = SYSRST_CTRL_ULP_AC_DEBOUNCE_CTL_ULP_AC_DEBOUNCE_TIMER_OFFSET })
 
// Ultra low power lid debounce control register
#define SYSRST_CTRL_ULP_LID_DEBOUNCE_CTL_REG_OFFSET 0x1c
#define SYSRST_CTRL_ULP_LID_DEBOUNCE_CTL_REG_RESVAL 0x1f40u
#define SYSRST_CTRL_ULP_LID_DEBOUNCE_CTL_ULP_LID_DEBOUNCE_TIMER_MASK 0xffffu
#define SYSRST_CTRL_ULP_LID_DEBOUNCE_CTL_ULP_LID_DEBOUNCE_TIMER_OFFSET 0
#define SYSRST_CTRL_ULP_LID_DEBOUNCE_CTL_ULP_LID_DEBOUNCE_TIMER_FIELD \
  ((bitfield_field32_t) { .mask = SYSRST_CTRL_ULP_LID_DEBOUNCE_CTL_ULP_LID_DEBOUNCE_TIMER_MASK, .index = SYSRST_CTRL_ULP_LID_DEBOUNCE_CTL_ULP_LID_DEBOUNCE_TIMER_OFFSET })
 
// Ultra low power pwrb debounce control register
#define SYSRST_CTRL_ULP_PWRB_DEBOUNCE_CTL_REG_OFFSET 0x20
#define SYSRST_CTRL_ULP_PWRB_DEBOUNCE_CTL_REG_RESVAL 0x1f40u
#define SYSRST_CTRL_ULP_PWRB_DEBOUNCE_CTL_ULP_PWRB_DEBOUNCE_TIMER_MASK 0xffffu
#define SYSRST_CTRL_ULP_PWRB_DEBOUNCE_CTL_ULP_PWRB_DEBOUNCE_TIMER_OFFSET 0
#define SYSRST_CTRL_ULP_PWRB_DEBOUNCE_CTL_ULP_PWRB_DEBOUNCE_TIMER_FIELD \
  ((bitfield_field32_t) { .mask = SYSRST_CTRL_ULP_PWRB_DEBOUNCE_CTL_ULP_PWRB_DEBOUNCE_TIMER_MASK, .index = SYSRST_CTRL_ULP_PWRB_DEBOUNCE_CTL_ULP_PWRB_DEBOUNCE_TIMER_OFFSET })
 
// Ultra low power control register
#define SYSRST_CTRL_ULP_CTL_REG_OFFSET 0x24
#define SYSRST_CTRL_ULP_CTL_REG_RESVAL 0x0u
#define SYSRST_CTRL_ULP_CTL_ULP_ENABLE_BIT 0
 
// Ultra low power status
#define SYSRST_CTRL_ULP_STATUS_REG_OFFSET 0x28
#define SYSRST_CTRL_ULP_STATUS_REG_RESVAL 0x0u
#define SYSRST_CTRL_ULP_STATUS_ULP_WAKEUP_BIT 0
 
// wakeup status
#define SYSRST_CTRL_WKUP_STATUS_REG_OFFSET 0x2c
#define SYSRST_CTRL_WKUP_STATUS_REG_RESVAL 0x0u
#define SYSRST_CTRL_WKUP_STATUS_WAKEUP_STS_BIT 0
 
// configure key input output invert property
#define SYSRST_CTRL_KEY_INVERT_CTL_REG_OFFSET 0x30
#define SYSRST_CTRL_KEY_INVERT_CTL_REG_RESVAL 0x0u
#define SYSRST_CTRL_KEY_INVERT_CTL_KEY0_IN_BIT 0
#define SYSRST_CTRL_KEY_INVERT_CTL_KEY0_OUT_BIT 1
#define SYSRST_CTRL_KEY_INVERT_CTL_KEY1_IN_BIT 2
#define SYSRST_CTRL_KEY_INVERT_CTL_KEY1_OUT_BIT 3
#define SYSRST_CTRL_KEY_INVERT_CTL_KEY2_IN_BIT 4
#define SYSRST_CTRL_KEY_INVERT_CTL_KEY2_OUT_BIT 5
#define SYSRST_CTRL_KEY_INVERT_CTL_PWRB_IN_BIT 6
#define SYSRST_CTRL_KEY_INVERT_CTL_PWRB_OUT_BIT 7
#define SYSRST_CTRL_KEY_INVERT_CTL_AC_PRESENT_BIT 8
#define SYSRST_CTRL_KEY_INVERT_CTL_BAT_DISABLE_BIT 9
#define SYSRST_CTRL_KEY_INVERT_CTL_LID_OPEN_BIT 10
#define SYSRST_CTRL_KEY_INVERT_CTL_Z3_WAKEUP_BIT 11
 
// This register determines which override values are allowed for a given
// output.
#define SYSRST_CTRL_PIN_ALLOWED_CTL_REG_OFFSET 0x34
#define SYSRST_CTRL_PIN_ALLOWED_CTL_REG_RESVAL 0x82u
#define SYSRST_CTRL_PIN_ALLOWED_CTL_BAT_DISABLE_0_BIT 0
#define SYSRST_CTRL_PIN_ALLOWED_CTL_EC_RST_L_0_BIT 1
#define SYSRST_CTRL_PIN_ALLOWED_CTL_PWRB_OUT_0_BIT 2
#define SYSRST_CTRL_PIN_ALLOWED_CTL_KEY0_OUT_0_BIT 3
#define SYSRST_CTRL_PIN_ALLOWED_CTL_KEY1_OUT_0_BIT 4
#define SYSRST_CTRL_PIN_ALLOWED_CTL_KEY2_OUT_0_BIT 5
#define SYSRST_CTRL_PIN_ALLOWED_CTL_Z3_WAKEUP_0_BIT 6
#define SYSRST_CTRL_PIN_ALLOWED_CTL_FLASH_WP_L_0_BIT 7
#define SYSRST_CTRL_PIN_ALLOWED_CTL_BAT_DISABLE_1_BIT 8
#define SYSRST_CTRL_PIN_ALLOWED_CTL_EC_RST_L_1_BIT 9
#define SYSRST_CTRL_PIN_ALLOWED_CTL_PWRB_OUT_1_BIT 10
#define SYSRST_CTRL_PIN_ALLOWED_CTL_KEY0_OUT_1_BIT 11
#define SYSRST_CTRL_PIN_ALLOWED_CTL_KEY1_OUT_1_BIT 12
#define SYSRST_CTRL_PIN_ALLOWED_CTL_KEY2_OUT_1_BIT 13
#define SYSRST_CTRL_PIN_ALLOWED_CTL_Z3_WAKEUP_1_BIT 14
#define SYSRST_CTRL_PIN_ALLOWED_CTL_FLASH_WP_L_1_BIT 15
 
// Enables the override function for a specific pin.
#define SYSRST_CTRL_PIN_OUT_CTL_REG_OFFSET 0x38
#define SYSRST_CTRL_PIN_OUT_CTL_REG_RESVAL 0x82u
#define SYSRST_CTRL_PIN_OUT_CTL_BAT_DISABLE_BIT 0
#define SYSRST_CTRL_PIN_OUT_CTL_EC_RST_L_BIT 1
#define SYSRST_CTRL_PIN_OUT_CTL_PWRB_OUT_BIT 2
#define SYSRST_CTRL_PIN_OUT_CTL_KEY0_OUT_BIT 3
#define SYSRST_CTRL_PIN_OUT_CTL_KEY1_OUT_BIT 4
#define SYSRST_CTRL_PIN_OUT_CTL_KEY2_OUT_BIT 5
#define SYSRST_CTRL_PIN_OUT_CTL_Z3_WAKEUP_BIT 6
#define SYSRST_CTRL_PIN_OUT_CTL_FLASH_WP_L_BIT 7
 
// Sets the pin override value. Note that only the values
#define SYSRST_CTRL_PIN_OUT_VALUE_REG_OFFSET 0x3c
#define SYSRST_CTRL_PIN_OUT_VALUE_REG_RESVAL 0x0u
#define SYSRST_CTRL_PIN_OUT_VALUE_BAT_DISABLE_BIT 0
#define SYSRST_CTRL_PIN_OUT_VALUE_EC_RST_L_BIT 1
#define SYSRST_CTRL_PIN_OUT_VALUE_PWRB_OUT_BIT 2
#define SYSRST_CTRL_PIN_OUT_VALUE_KEY0_OUT_BIT 3
#define SYSRST_CTRL_PIN_OUT_VALUE_KEY1_OUT_BIT 4
#define SYSRST_CTRL_PIN_OUT_VALUE_KEY2_OUT_BIT 5
#define SYSRST_CTRL_PIN_OUT_VALUE_Z3_WAKEUP_BIT 6
#define SYSRST_CTRL_PIN_OUT_VALUE_FLASH_WP_L_BIT 7
 
// For SW to read the sysrst_ctrl inputs like GPIO
#define SYSRST_CTRL_PIN_IN_VALUE_REG_OFFSET 0x40
#define SYSRST_CTRL_PIN_IN_VALUE_REG_RESVAL 0x0u
#define SYSRST_CTRL_PIN_IN_VALUE_PWRB_IN_BIT 0
#define SYSRST_CTRL_PIN_IN_VALUE_KEY0_IN_BIT 1
#define SYSRST_CTRL_PIN_IN_VALUE_KEY1_IN_BIT 2
#define SYSRST_CTRL_PIN_IN_VALUE_KEY2_IN_BIT 3
#define SYSRST_CTRL_PIN_IN_VALUE_LID_OPEN_BIT 4
#define SYSRST_CTRL_PIN_IN_VALUE_AC_PRESENT_BIT 5
#define SYSRST_CTRL_PIN_IN_VALUE_EC_RST_L_BIT 6
#define SYSRST_CTRL_PIN_IN_VALUE_FLASH_WP_L_BIT 7
 
// Define the keys or inputs that can trigger the interrupt
#define SYSRST_CTRL_KEY_INTR_CTL_REG_OFFSET 0x44
#define SYSRST_CTRL_KEY_INTR_CTL_REG_RESVAL 0x0u
#define SYSRST_CTRL_KEY_INTR_CTL_PWRB_IN_H2L_BIT 0
#define SYSRST_CTRL_KEY_INTR_CTL_KEY0_IN_H2L_BIT 1
#define SYSRST_CTRL_KEY_INTR_CTL_KEY1_IN_H2L_BIT 2
#define SYSRST_CTRL_KEY_INTR_CTL_KEY2_IN_H2L_BIT 3
#define SYSRST_CTRL_KEY_INTR_CTL_AC_PRESENT_H2L_BIT 4
#define SYSRST_CTRL_KEY_INTR_CTL_EC_RST_L_H2L_BIT 5
#define SYSRST_CTRL_KEY_INTR_CTL_FLASH_WP_L_H2L_BIT 6
#define SYSRST_CTRL_KEY_INTR_CTL_PWRB_IN_L2H_BIT 7
#define SYSRST_CTRL_KEY_INTR_CTL_KEY0_IN_L2H_BIT 8
#define SYSRST_CTRL_KEY_INTR_CTL_KEY1_IN_L2H_BIT 9
#define SYSRST_CTRL_KEY_INTR_CTL_KEY2_IN_L2H_BIT 10
#define SYSRST_CTRL_KEY_INTR_CTL_AC_PRESENT_L2H_BIT 11
#define SYSRST_CTRL_KEY_INTR_CTL_EC_RST_L_L2H_BIT 12
#define SYSRST_CTRL_KEY_INTR_CTL_FLASH_WP_L_L2H_BIT 13
 
// Debounce timer control register for key-triggered interrupt
#define SYSRST_CTRL_KEY_INTR_DEBOUNCE_CTL_REG_OFFSET 0x48
#define SYSRST_CTRL_KEY_INTR_DEBOUNCE_CTL_REG_RESVAL 0x7d0u
#define SYSRST_CTRL_KEY_INTR_DEBOUNCE_CTL_DEBOUNCE_TIMER_MASK 0xffffu
#define SYSRST_CTRL_KEY_INTR_DEBOUNCE_CTL_DEBOUNCE_TIMER_OFFSET 0
#define SYSRST_CTRL_KEY_INTR_DEBOUNCE_CTL_DEBOUNCE_TIMER_FIELD \
  ((bitfield_field32_t) { .mask = SYSRST_CTRL_KEY_INTR_DEBOUNCE_CTL_DEBOUNCE_TIMER_MASK, .index = SYSRST_CTRL_KEY_INTR_DEBOUNCE_CTL_DEBOUNCE_TIMER_OFFSET })
 
// Debounce timer control register for pwrb_in H2L transition
#define SYSRST_CTRL_AUTO_BLOCK_DEBOUNCE_CTL_REG_OFFSET 0x4c
#define SYSRST_CTRL_AUTO_BLOCK_DEBOUNCE_CTL_REG_RESVAL 0x7d0u
#define SYSRST_CTRL_AUTO_BLOCK_DEBOUNCE_CTL_DEBOUNCE_TIMER_MASK 0xffffu
#define SYSRST_CTRL_AUTO_BLOCK_DEBOUNCE_CTL_DEBOUNCE_TIMER_OFFSET 0
#define SYSRST_CTRL_AUTO_BLOCK_DEBOUNCE_CTL_DEBOUNCE_TIMER_FIELD \
  ((bitfield_field32_t) { .mask = SYSRST_CTRL_AUTO_BLOCK_DEBOUNCE_CTL_DEBOUNCE_TIMER_MASK, .index = SYSRST_CTRL_AUTO_BLOCK_DEBOUNCE_CTL_DEBOUNCE_TIMER_OFFSET })
#define SYSRST_CTRL_AUTO_BLOCK_DEBOUNCE_CTL_AUTO_BLOCK_ENABLE_BIT 16
 
// configure the key outputs to auto-override and their value
#define SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_REG_OFFSET 0x50
#define SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_REG_RESVAL 0x0u
#define SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY0_OUT_SEL_BIT 0
#define SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY1_OUT_SEL_BIT 1
#define SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY2_OUT_SEL_BIT 2
#define SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY0_OUT_VALUE_BIT 4
#define SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY1_OUT_VALUE_BIT 5
#define SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY2_OUT_VALUE_BIT 6
 
// To define the keys that define the pre-condition of the combo
#define SYSRST_CTRL_COM_PRE_SEL_CTL_KEY0_IN_SEL_FIELD_WIDTH 1
#define SYSRST_CTRL_COM_PRE_SEL_CTL_KEY1_IN_SEL_FIELD_WIDTH 1
#define SYSRST_CTRL_COM_PRE_SEL_CTL_KEY2_IN_SEL_FIELD_WIDTH 1
#define SYSRST_CTRL_COM_PRE_SEL_CTL_PWRB_IN_SEL_FIELD_WIDTH 1
#define SYSRST_CTRL_COM_PRE_SEL_CTL_AC_PRESENT_SEL_FIELD_WIDTH 1
#define SYSRST_CTRL_COM_PRE_SEL_CTL_MULTIREG_COUNT 4
 
// To define the keys that define the pre-condition of the combo
#define SYSRST_CTRL_COM_PRE_SEL_CTL_0_REG_OFFSET 0x54
#define SYSRST_CTRL_COM_PRE_SEL_CTL_0_REG_RESVAL 0x0u
#define SYSRST_CTRL_COM_PRE_SEL_CTL_0_KEY0_IN_SEL_0_BIT 0
#define SYSRST_CTRL_COM_PRE_SEL_CTL_0_KEY1_IN_SEL_0_BIT 1
#define SYSRST_CTRL_COM_PRE_SEL_CTL_0_KEY2_IN_SEL_0_BIT 2
#define SYSRST_CTRL_COM_PRE_SEL_CTL_0_PWRB_IN_SEL_0_BIT 3
#define SYSRST_CTRL_COM_PRE_SEL_CTL_0_AC_PRESENT_SEL_0_BIT 4
 
// To define the keys that define the pre-condition of the combo
#define SYSRST_CTRL_COM_PRE_SEL_CTL_1_REG_OFFSET 0x58
#define SYSRST_CTRL_COM_PRE_SEL_CTL_1_REG_RESVAL 0x0u
#define SYSRST_CTRL_COM_PRE_SEL_CTL_1_KEY0_IN_SEL_1_BIT 0
#define SYSRST_CTRL_COM_PRE_SEL_CTL_1_KEY1_IN_SEL_1_BIT 1
#define SYSRST_CTRL_COM_PRE_SEL_CTL_1_KEY2_IN_SEL_1_BIT 2
#define SYSRST_CTRL_COM_PRE_SEL_CTL_1_PWRB_IN_SEL_1_BIT 3
#define SYSRST_CTRL_COM_PRE_SEL_CTL_1_AC_PRESENT_SEL_1_BIT 4
 
// To define the keys that define the pre-condition of the combo
#define SYSRST_CTRL_COM_PRE_SEL_CTL_2_REG_OFFSET 0x5c
#define SYSRST_CTRL_COM_PRE_SEL_CTL_2_REG_RESVAL 0x0u
#define SYSRST_CTRL_COM_PRE_SEL_CTL_2_KEY0_IN_SEL_2_BIT 0
#define SYSRST_CTRL_COM_PRE_SEL_CTL_2_KEY1_IN_SEL_2_BIT 1
#define SYSRST_CTRL_COM_PRE_SEL_CTL_2_KEY2_IN_SEL_2_BIT 2
#define SYSRST_CTRL_COM_PRE_SEL_CTL_2_PWRB_IN_SEL_2_BIT 3
#define SYSRST_CTRL_COM_PRE_SEL_CTL_2_AC_PRESENT_SEL_2_BIT 4
 
// To define the keys that define the pre-condition of the combo
#define SYSRST_CTRL_COM_PRE_SEL_CTL_3_REG_OFFSET 0x60
#define SYSRST_CTRL_COM_PRE_SEL_CTL_3_REG_RESVAL 0x0u
#define SYSRST_CTRL_COM_PRE_SEL_CTL_3_KEY0_IN_SEL_3_BIT 0
#define SYSRST_CTRL_COM_PRE_SEL_CTL_3_KEY1_IN_SEL_3_BIT 1
#define SYSRST_CTRL_COM_PRE_SEL_CTL_3_KEY2_IN_SEL_3_BIT 2
#define SYSRST_CTRL_COM_PRE_SEL_CTL_3_PWRB_IN_SEL_3_BIT 3
#define SYSRST_CTRL_COM_PRE_SEL_CTL_3_AC_PRESENT_SEL_3_BIT 4
 
// To define the duration that the combo pre-condition should be pressed
#define SYSRST_CTRL_COM_PRE_DET_CTL_PRECONDITION_TIMER_FIELD_WIDTH 32
#define SYSRST_CTRL_COM_PRE_DET_CTL_MULTIREG_COUNT 4
 
// To define the duration that the combo pre-condition should be pressed
#define SYSRST_CTRL_COM_PRE_DET_CTL_0_REG_OFFSET 0x64
#define SYSRST_CTRL_COM_PRE_DET_CTL_0_REG_RESVAL 0x0u
 
// To define the duration that the combo pre-condition should be pressed
#define SYSRST_CTRL_COM_PRE_DET_CTL_1_REG_OFFSET 0x68
#define SYSRST_CTRL_COM_PRE_DET_CTL_1_REG_RESVAL 0x0u
 
// To define the duration that the combo pre-condition should be pressed
#define SYSRST_CTRL_COM_PRE_DET_CTL_2_REG_OFFSET 0x6c
#define SYSRST_CTRL_COM_PRE_DET_CTL_2_REG_RESVAL 0x0u
 
// To define the duration that the combo pre-condition should be pressed
#define SYSRST_CTRL_COM_PRE_DET_CTL_3_REG_OFFSET 0x70
#define SYSRST_CTRL_COM_PRE_DET_CTL_3_REG_RESVAL 0x0u
 
// To define the keys that trigger the combo
#define SYSRST_CTRL_COM_SEL_CTL_KEY0_IN_SEL_FIELD_WIDTH 1
#define SYSRST_CTRL_COM_SEL_CTL_KEY1_IN_SEL_FIELD_WIDTH 1
#define SYSRST_CTRL_COM_SEL_CTL_KEY2_IN_SEL_FIELD_WIDTH 1
#define SYSRST_CTRL_COM_SEL_CTL_PWRB_IN_SEL_FIELD_WIDTH 1
#define SYSRST_CTRL_COM_SEL_CTL_AC_PRESENT_SEL_FIELD_WIDTH 1
#define SYSRST_CTRL_COM_SEL_CTL_MULTIREG_COUNT 4
 
// To define the keys that trigger the combo
#define SYSRST_CTRL_COM_SEL_CTL_0_REG_OFFSET 0x74
#define SYSRST_CTRL_COM_SEL_CTL_0_REG_RESVAL 0x0u
#define SYSRST_CTRL_COM_SEL_CTL_0_KEY0_IN_SEL_0_BIT 0
#define SYSRST_CTRL_COM_SEL_CTL_0_KEY1_IN_SEL_0_BIT 1
#define SYSRST_CTRL_COM_SEL_CTL_0_KEY2_IN_SEL_0_BIT 2
#define SYSRST_CTRL_COM_SEL_CTL_0_PWRB_IN_SEL_0_BIT 3
#define SYSRST_CTRL_COM_SEL_CTL_0_AC_PRESENT_SEL_0_BIT 4
 
// To define the keys that trigger the combo
#define SYSRST_CTRL_COM_SEL_CTL_1_REG_OFFSET 0x78
#define SYSRST_CTRL_COM_SEL_CTL_1_REG_RESVAL 0x0u
#define SYSRST_CTRL_COM_SEL_CTL_1_KEY0_IN_SEL_1_BIT 0
#define SYSRST_CTRL_COM_SEL_CTL_1_KEY1_IN_SEL_1_BIT 1
#define SYSRST_CTRL_COM_SEL_CTL_1_KEY2_IN_SEL_1_BIT 2
#define SYSRST_CTRL_COM_SEL_CTL_1_PWRB_IN_SEL_1_BIT 3
#define SYSRST_CTRL_COM_SEL_CTL_1_AC_PRESENT_SEL_1_BIT 4
 
// To define the keys that trigger the combo
#define SYSRST_CTRL_COM_SEL_CTL_2_REG_OFFSET 0x7c
#define SYSRST_CTRL_COM_SEL_CTL_2_REG_RESVAL 0x0u
#define SYSRST_CTRL_COM_SEL_CTL_2_KEY0_IN_SEL_2_BIT 0
#define SYSRST_CTRL_COM_SEL_CTL_2_KEY1_IN_SEL_2_BIT 1
#define SYSRST_CTRL_COM_SEL_CTL_2_KEY2_IN_SEL_2_BIT 2
#define SYSRST_CTRL_COM_SEL_CTL_2_PWRB_IN_SEL_2_BIT 3
#define SYSRST_CTRL_COM_SEL_CTL_2_AC_PRESENT_SEL_2_BIT 4
 
// To define the keys that trigger the combo
#define SYSRST_CTRL_COM_SEL_CTL_3_REG_OFFSET 0x80
#define SYSRST_CTRL_COM_SEL_CTL_3_REG_RESVAL 0x0u
#define SYSRST_CTRL_COM_SEL_CTL_3_KEY0_IN_SEL_3_BIT 0
#define SYSRST_CTRL_COM_SEL_CTL_3_KEY1_IN_SEL_3_BIT 1
#define SYSRST_CTRL_COM_SEL_CTL_3_KEY2_IN_SEL_3_BIT 2
#define SYSRST_CTRL_COM_SEL_CTL_3_PWRB_IN_SEL_3_BIT 3
#define SYSRST_CTRL_COM_SEL_CTL_3_AC_PRESENT_SEL_3_BIT 4
 
// To define the duration that the combo should be pressed
#define SYSRST_CTRL_COM_DET_CTL_DETECTION_TIMER_FIELD_WIDTH 32
#define SYSRST_CTRL_COM_DET_CTL_MULTIREG_COUNT 4
 
// To define the duration that the combo should be pressed
#define SYSRST_CTRL_COM_DET_CTL_0_REG_OFFSET 0x84
#define SYSRST_CTRL_COM_DET_CTL_0_REG_RESVAL 0x0u
 
// To define the duration that the combo should be pressed
#define SYSRST_CTRL_COM_DET_CTL_1_REG_OFFSET 0x88
#define SYSRST_CTRL_COM_DET_CTL_1_REG_RESVAL 0x0u
 
// To define the duration that the combo should be pressed
#define SYSRST_CTRL_COM_DET_CTL_2_REG_OFFSET 0x8c
#define SYSRST_CTRL_COM_DET_CTL_2_REG_RESVAL 0x0u
 
// To define the duration that the combo should be pressed
#define SYSRST_CTRL_COM_DET_CTL_3_REG_OFFSET 0x90
#define SYSRST_CTRL_COM_DET_CTL_3_REG_RESVAL 0x0u
 
// To define the actions once the combo is detected
#define SYSRST_CTRL_COM_OUT_CTL_BAT_DISABLE_FIELD_WIDTH 1
#define SYSRST_CTRL_COM_OUT_CTL_INTERRUPT_FIELD_WIDTH 1
#define SYSRST_CTRL_COM_OUT_CTL_EC_RST_FIELD_WIDTH 1
#define SYSRST_CTRL_COM_OUT_CTL_RST_REQ_FIELD_WIDTH 1
#define SYSRST_CTRL_COM_OUT_CTL_MULTIREG_COUNT 4
 
// To define the actions once the combo is detected
#define SYSRST_CTRL_COM_OUT_CTL_0_REG_OFFSET 0x94
#define SYSRST_CTRL_COM_OUT_CTL_0_REG_RESVAL 0x0u
#define SYSRST_CTRL_COM_OUT_CTL_0_BAT_DISABLE_0_BIT 0
#define SYSRST_CTRL_COM_OUT_CTL_0_INTERRUPT_0_BIT 1
#define SYSRST_CTRL_COM_OUT_CTL_0_EC_RST_0_BIT 2
#define SYSRST_CTRL_COM_OUT_CTL_0_RST_REQ_0_BIT 3
 
// To define the actions once the combo is detected
#define SYSRST_CTRL_COM_OUT_CTL_1_REG_OFFSET 0x98
#define SYSRST_CTRL_COM_OUT_CTL_1_REG_RESVAL 0x0u
#define SYSRST_CTRL_COM_OUT_CTL_1_BAT_DISABLE_1_BIT 0
#define SYSRST_CTRL_COM_OUT_CTL_1_INTERRUPT_1_BIT 1
#define SYSRST_CTRL_COM_OUT_CTL_1_EC_RST_1_BIT 2
#define SYSRST_CTRL_COM_OUT_CTL_1_RST_REQ_1_BIT 3
 
// To define the actions once the combo is detected
#define SYSRST_CTRL_COM_OUT_CTL_2_REG_OFFSET 0x9c
#define SYSRST_CTRL_COM_OUT_CTL_2_REG_RESVAL 0x0u
#define SYSRST_CTRL_COM_OUT_CTL_2_BAT_DISABLE_2_BIT 0
#define SYSRST_CTRL_COM_OUT_CTL_2_INTERRUPT_2_BIT 1
#define SYSRST_CTRL_COM_OUT_CTL_2_EC_RST_2_BIT 2
#define SYSRST_CTRL_COM_OUT_CTL_2_RST_REQ_2_BIT 3
 
// To define the actions once the combo is detected
#define SYSRST_CTRL_COM_OUT_CTL_3_REG_OFFSET 0xa0
#define SYSRST_CTRL_COM_OUT_CTL_3_REG_RESVAL 0x0u
#define SYSRST_CTRL_COM_OUT_CTL_3_BAT_DISABLE_3_BIT 0
#define SYSRST_CTRL_COM_OUT_CTL_3_INTERRUPT_3_BIT 1
#define SYSRST_CTRL_COM_OUT_CTL_3_EC_RST_3_BIT 2
#define SYSRST_CTRL_COM_OUT_CTL_3_RST_REQ_3_BIT 3
 
// Combo interrupt source. These registers will only be set if the
#define SYSRST_CTRL_COMBO_INTR_STATUS_REG_OFFSET 0xa4
#define SYSRST_CTRL_COMBO_INTR_STATUS_REG_RESVAL 0x0u
#define SYSRST_CTRL_COMBO_INTR_STATUS_COMBO0_H2L_BIT 0
#define SYSRST_CTRL_COMBO_INTR_STATUS_COMBO1_H2L_BIT 1
#define SYSRST_CTRL_COMBO_INTR_STATUS_COMBO2_H2L_BIT 2
#define SYSRST_CTRL_COMBO_INTR_STATUS_COMBO3_H2L_BIT 3
 
// key interrupt source
#define SYSRST_CTRL_KEY_INTR_STATUS_REG_OFFSET 0xa8
#define SYSRST_CTRL_KEY_INTR_STATUS_REG_RESVAL 0x0u
#define SYSRST_CTRL_KEY_INTR_STATUS_PWRB_H2L_BIT 0
#define SYSRST_CTRL_KEY_INTR_STATUS_KEY0_IN_H2L_BIT 1
#define SYSRST_CTRL_KEY_INTR_STATUS_KEY1_IN_H2L_BIT 2
#define SYSRST_CTRL_KEY_INTR_STATUS_KEY2_IN_H2L_BIT 3
#define SYSRST_CTRL_KEY_INTR_STATUS_AC_PRESENT_H2L_BIT 4
#define SYSRST_CTRL_KEY_INTR_STATUS_EC_RST_L_H2L_BIT 5
#define SYSRST_CTRL_KEY_INTR_STATUS_FLASH_WP_L_H2L_BIT 6
#define SYSRST_CTRL_KEY_INTR_STATUS_PWRB_L2H_BIT 7
#define SYSRST_CTRL_KEY_INTR_STATUS_KEY0_IN_L2H_BIT 8
#define SYSRST_CTRL_KEY_INTR_STATUS_KEY1_IN_L2H_BIT 9
#define SYSRST_CTRL_KEY_INTR_STATUS_KEY2_IN_L2H_BIT 10
#define SYSRST_CTRL_KEY_INTR_STATUS_AC_PRESENT_L2H_BIT 11
#define SYSRST_CTRL_KEY_INTR_STATUS_EC_RST_L_L2H_BIT 12
#define SYSRST_CTRL_KEY_INTR_STATUS_FLASH_WP_L_L2H_BIT 13
 
#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _SYSRST_CTRL_REG_DEFS_
// End generated register defines for sysrst_ctrl