Software APIs
sysrst_ctrl.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7#ifndef OPENTITAN_DT_SYSRST_CTRL_H_
8#define OPENTITAN_DT_SYSRST_CTRL_H_
9
10#ifdef __cplusplus
11extern "C" {
12#endif // __cplusplus
13
14/**
15 * @file
16 * @brief Device Tables (DT) for IP sysrst_ctrl and top earlgrey.
17 *
18 * This file contains the type definitions and global functions of the sysrst_ctrl.
19 */
20
21#include "hw/top/dt/api.h"
22#include <stdint.h>
23
24
25
26/**
27 * List of instances.
28 */
29typedef enum dt_sysrst_ctrl {
30 kDtSysrstCtrlFirst = 0, /**< First instance */
31 kDtSysrstCtrlAon = 0, /**< sysrst_ctrl_aon */
33
34enum {
35 kDtSysrstCtrlCount = 1, /**< Number of instances */
36};
37
38
39/**
40 * List of register blocks.
41 *
42 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
43 */
45 kDtSysrstCtrlRegBlockCore = 0, /**< */
47
48enum {
49 kDtSysrstCtrlRegBlockCount = 1, /**< Number of register blocks */
50};
51
52
53/** Primary register block (associated with the "primary" set of registers that control the IP). */
54static const dt_sysrst_ctrl_reg_block_t kDtSysrstCtrlRegBlockPrimary = kDtSysrstCtrlRegBlockCore;
55
56/**
57 * List of IRQs.
58 *
59 * IRQs are guaranteed to be numbered consecutively from 0.
60 */
61typedef enum dt_sysrst_ctrl_irq {
62 kDtSysrstCtrlIrqEventDetected = 0, /**< Common interrupt triggered by combo or keyboard events. */
64
65enum {
66 kDtSysrstCtrlIrqCount = 1, /**< Number of IRQs */
67};
68
69
70/**
71 * List of Alerts.
72 *
73 * Alerts are guaranteed to be numbered consecutively from 0.
74 */
76 kDtSysrstCtrlAlertFatalFault = 0, /**< This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. */
78
79enum {
80 kDtSysrstCtrlAlertCount = 1, /**< Number of Alerts */
81};
82
83
84/**
85 * List of clock ports.
86 *
87 * Clock ports are guaranteed to be numbered consecutively from 0.
88 */
90 kDtSysrstCtrlClockClk = 0, /**< Clock port clk_i */
91 kDtSysrstCtrlClockAon = 1, /**< Clock port clk_aon_i */
93
94enum {
95 kDtSysrstCtrlClockCount = 2, /**< Number of clock ports */
96};
97
98
99/**
100 * List of reset requests.
101 *
102 * Reset requests are guaranteed to be numbered consecutively from 0.
103 */
105 kDtSysrstCtrlResetReqRstReq = 0, /**< OpenTitan reset request to `rstmgr` (running on AON clock). */
107
108enum {
109 kDtSysrstCtrlResetReqCount = 1, /**< Number of reset requests */
110};
111
112
113/**
114 * List of reset ports.
115 *
116 * Reset ports are guaranteed to be numbered consecutively from 0.
117 */
119 kDtSysrstCtrlResetRst = 0, /**< Reset port rst_ni */
120 kDtSysrstCtrlResetAon = 1, /**< Reset port rst_aon_ni */
122
123enum {
124 kDtSysrstCtrlResetCount = 2, /**< Number of reset ports */
125};
126
127
128/**
129 * List of peripheral I/O.
130 *
131 * Peripheral I/O are guaranteed to be numbered consecutively from 0.
132 */
134 kDtSysrstCtrlPeriphIoAcPresent = 0, /**< */
135 kDtSysrstCtrlPeriphIoKey0In = 1, /**< */
136 kDtSysrstCtrlPeriphIoKey1In = 2, /**< */
137 kDtSysrstCtrlPeriphIoKey2In = 3, /**< */
138 kDtSysrstCtrlPeriphIoPwrbIn = 4, /**< */
139 kDtSysrstCtrlPeriphIoLidOpen = 5, /**< */
140 kDtSysrstCtrlPeriphIoBatDisable = 6, /**< */
141 kDtSysrstCtrlPeriphIoKey0Out = 7, /**< */
142 kDtSysrstCtrlPeriphIoKey1Out = 8, /**< */
143 kDtSysrstCtrlPeriphIoKey2Out = 9, /**< */
144 kDtSysrstCtrlPeriphIoPwrbOut = 10, /**< */
145 kDtSysrstCtrlPeriphIoZ3Wakeup = 11, /**< */
146 kDtSysrstCtrlPeriphIoEcRstL = 12, /**< */
147 kDtSysrstCtrlPeriphIoFlashWpL = 13, /**< */
149
150enum {
151 kDtSysrstCtrlPeriphIoCount = 14, /**< Number of peripheral I/O */
152};
153
154
155/**
156 * List of wakeups.
157 *
158 * Wakeups are guaranteed to be numbered consecutively from 0.
159 */
161 kDtSysrstCtrlWakeupWkupReq = 0, /**< OpenTitan wake request signal to `pwrmgr` (running on AON clock). */
163
164enum {
165 kDtSysrstCtrlWakeupCount = 1, /**< Number of wakeups */
166};
167
168
169/**
170 * List of supported hardware features.
171 */
172#define OPENTITAN_SYSRST_CTRL_HAS_COMBO_DETECT 1
173#define OPENTITAN_SYSRST_CTRL_HAS_AUTO_BLOCK_KEY_OUTPUT 1
174#define OPENTITAN_SYSRST_CTRL_HAS_INPUT_TRIGGERED_INTERRUPT 1
175#define OPENTITAN_SYSRST_CTRL_HAS_ULTRA_LOW_POWER_WAKEUP 1
176#define OPENTITAN_SYSRST_CTRL_HAS_PINOUT_KEY_INVERSION_CONTROL 1
177#define OPENTITAN_SYSRST_CTRL_HAS_HARDWARE_RESET_STRETCH 1
178#define OPENTITAN_SYSRST_CTRL_HAS_FLASH_WRITE_PROTECT 1
179#define OPENTITAN_SYSRST_CTRL_HAS_PIN_INPUT_VALUE_ACCESS 1
180
181
182
183/**
184 * Get the sysrst_ctrl instance from an instance ID
185 *
186 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
187 *
188 * @param inst_id Instance ID.
189 * @return A sysrst_ctrl instance.
190 *
191 * **Note:** This function only makes sense if the instance ID has device type sysrst_ctrl,
192 * otherwise the returned value is unspecified.
193 */
195
196/**
197 * Get the instance ID of an instance.
198 *
199 * @param dt Instance of sysrst_ctrl.
200 * @return The instance ID of that instance.
201 */
203
204/**
205 * Get the register base address of an instance.
206 *
207 * @param dt Instance of sysrst_ctrl.
208 * @param reg_block The register block requested.
209 * @return The register base address of the requested block.
210 */
214
215/**
216 * Get the primary register base address of an instance.
217 *
218 * This is just a convenience function, equivalent to
219 * `dt_sysrst_ctrl_reg_block(dt, kDtSysrstCtrlRegBlockCore)`
220 *
221 * @param dt Instance of sysrst_ctrl.
222 * @return The register base address of the primary register block.
223 */
224static inline uint32_t dt_sysrst_ctrl_primary_reg_block(
225 dt_sysrst_ctrl_t dt) {
226 return dt_sysrst_ctrl_reg_block(dt, kDtSysrstCtrlRegBlockCore);
227}
228
229/**
230 * Get the PLIC ID of a sysrst_ctrl IRQ for a given instance.
231 *
232 * If the instance is not connected to the PLIC, this function
233 * will return `kDtPlicIrqIdNone`.
234 *
235 * @param dt Instance of sysrst_ctrl.
236 * @param irq A sysrst_ctrl IRQ.
237 * @return The PLIC ID of the IRQ of this instance.
238 */
242
243/**
244 * Convert a global IRQ ID to a local sysrst_ctrl IRQ type.
245 *
246 * @param dt Instance of sysrst_ctrl.
247 * @param irq A PLIC ID that belongs to this instance.
248 * @return The sysrst_ctrl IRQ, or `kDtSysrstCtrlIrqCount`.
249 *
250 * **Note:** This function assumes that the PLIC ID belongs to the instance
251 * of sysrst_ctrl passed in parameter. In other words, it must be the case that
252 * `dt_sysrst_ctrl_instance_id(dt) == dt_plic_id_to_instance_id(irq)`. Otherwise, this function
253 * will return `kDtSysrstCtrlIrqCount`.
254 */
257 dt_plic_irq_id_t irq);
258
259
260/**
261 * Get the alert ID of a sysrst_ctrl alert for a given instance.
262 *
263 * **Note:** This function only makes sense if the instance is connected to the Alert Handler. For any
264 * instances where the instance is not connected, the return value is unspecified.
265 *
266 * @param dt Instance of sysrst_ctrl.
267 * @param alert A sysrst_ctrl alert.
268 * @return The Alert Handler alert ID of the alert of this instance.
269 */
273
274/**
275 * Convert a global alert ID to a local sysrst_ctrl alert type.
276 *
277 * @param dt Instance of sysrst_ctrl.
278 * @param alert A global alert ID that belongs to this instance.
279 * @return The sysrst_ctrl alert, or `kDtSysrstCtrlAlertCount`.
280 *
281 * **Note:** This function assumes that the global alert ID belongs to the
282 * instance of sysrst_ctrl passed in parameter. In other words, it must be the case
283 * that `dt_sysrst_ctrl_instance_id(dt) == dt_alert_id_to_instance_id(alert)`. Otherwise,
284 * this function will return `kDtSysrstCtrlAlertCount`.
285 */
288 dt_alert_id_t alert);
289
290
291/**
292 * Get the peripheral I/O description of an instance.
293 *
294 * @param dt Instance of sysrst_ctrl.
295 * @param sig Requested peripheral I/O.
296 * @return Description of the requested peripheral I/O for this instance.
297 */
301
302/**
303 * Get the clock signal connected to a clock port of an instance.
304 *
305 * @param dt Instance of sysrst_ctrl.
306 * @param clk Clock port.
307 * @return Clock signal.
308 */
312
313/**
314 * Get the reset signal connected to a reset port of an instance.
315 *
316 * @param dt Instance of sysrst_ctrl.
317 * @param rst Reset port.
318 * @return Reset signal.
319 */
323
324
325
326#ifdef __cplusplus
327} // extern "C"
328#endif // __cplusplus
329
330#endif // OPENTITAN_DT_SYSRST_CTRL_H_