soc_dbg_ctrl_regs.h

Go to the documentation of this file.

/**
 * @file
 * @brief Generated register defines for soc_dbg_ctrl
 */
 
// Copyright information found in source file:
// Copyright lowRISC contributors (OpenTitan project).
 
// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#ifndef _SOC_DBG_CTRL_REG_DEFS_
#define _SOC_DBG_CTRL_REG_DEFS_
 
#ifdef __cplusplus
extern "C" {
#endif
// Number of alerts
#define SOC_DBG_CTRL_PARAM_NUM_ALERTS 2
 
// Register width
#define SOC_DBG_CTRL_PARAM_REG_WIDTH 32
 
// Alert Test Register
#define SOC_DBG_CTRL_ALERT_TEST_REG_OFFSET 0x0
#define SOC_DBG_CTRL_ALERT_TEST_REG_RESVAL 0x80000000u
#define SOC_DBG_CTRL_ALERT_TEST_FATAL_FAULT_BIT 0
#define SOC_DBG_CTRL_ALERT_TEST_RECOV_CTRL_UPDATE_ERR_BIT 1
#define SOC_DBG_CTRL_ALERT_TEST_REGWEN_BIT 31
 
// Debug Policy Valid.
#define SOC_DBG_CTRL_DEBUG_POLICY_VALID_SHADOWED_REG_OFFSET 0x4
#define SOC_DBG_CTRL_DEBUG_POLICY_VALID_SHADOWED_REG_RESVAL 0x9u
#define SOC_DBG_CTRL_DEBUG_POLICY_VALID_SHADOWED_DEBUG_POLICY_VALID_MASK 0xfu
#define SOC_DBG_CTRL_DEBUG_POLICY_VALID_SHADOWED_DEBUG_POLICY_VALID_OFFSET 0
#define SOC_DBG_CTRL_DEBUG_POLICY_VALID_SHADOWED_DEBUG_POLICY_VALID_FIELD \
  ((bitfield_field32_t) { .mask = SOC_DBG_CTRL_DEBUG_POLICY_VALID_SHADOWED_DEBUG_POLICY_VALID_MASK, .index = SOC_DBG_CTRL_DEBUG_POLICY_VALID_SHADOWED_DEBUG_POLICY_VALID_OFFSET })
 
// Debug Policy category
#define SOC_DBG_CTRL_DEBUG_POLICY_CATEGORY_SHADOWED_REG_OFFSET 0x8
#define SOC_DBG_CTRL_DEBUG_POLICY_CATEGORY_SHADOWED_REG_RESVAL 0x50u
#define SOC_DBG_CTRL_DEBUG_POLICY_CATEGORY_SHADOWED_DEBUG_POLICY_CATEGORY_MASK \
  0x7fu
#define SOC_DBG_CTRL_DEBUG_POLICY_CATEGORY_SHADOWED_DEBUG_POLICY_CATEGORY_OFFSET \
  0
#define SOC_DBG_CTRL_DEBUG_POLICY_CATEGORY_SHADOWED_DEBUG_POLICY_CATEGORY_FIELD \
  ((bitfield_field32_t) { .mask = SOC_DBG_CTRL_DEBUG_POLICY_CATEGORY_SHADOWED_DEBUG_POLICY_CATEGORY_MASK, .index = SOC_DBG_CTRL_DEBUG_POLICY_CATEGORY_SHADOWED_DEBUG_POLICY_CATEGORY_OFFSET })
 
// Debug Policy relocked
#define SOC_DBG_CTRL_DEBUG_POLICY_RELOCKED_REG_OFFSET 0xc
#define SOC_DBG_CTRL_DEBUG_POLICY_RELOCKED_REG_RESVAL 0x9u
#define SOC_DBG_CTRL_DEBUG_POLICY_RELOCKED_DEBUG_POLICY_RELOCKED_MASK 0xfu
#define SOC_DBG_CTRL_DEBUG_POLICY_RELOCKED_DEBUG_POLICY_RELOCKED_OFFSET 0
#define SOC_DBG_CTRL_DEBUG_POLICY_RELOCKED_DEBUG_POLICY_RELOCKED_FIELD \
  ((bitfield_field32_t) { .mask = SOC_DBG_CTRL_DEBUG_POLICY_RELOCKED_DEBUG_POLICY_RELOCKED_MASK, .index = SOC_DBG_CTRL_DEBUG_POLICY_RELOCKED_DEBUG_POLICY_RELOCKED_OFFSET })
 
// Trace register to observe the debug category that is determined either by
// hardware or by software.
#define SOC_DBG_CTRL_TRACE_DEBUG_POLICY_CATEGORY_REG_OFFSET 0x10
#define SOC_DBG_CTRL_TRACE_DEBUG_POLICY_CATEGORY_REG_RESVAL 0x50u
#define SOC_DBG_CTRL_TRACE_DEBUG_POLICY_CATEGORY_CATEGORY_MASK 0x7fu
#define SOC_DBG_CTRL_TRACE_DEBUG_POLICY_CATEGORY_CATEGORY_OFFSET 0
#define SOC_DBG_CTRL_TRACE_DEBUG_POLICY_CATEGORY_CATEGORY_FIELD \
  ((bitfield_field32_t) { .mask = SOC_DBG_CTRL_TRACE_DEBUG_POLICY_CATEGORY_CATEGORY_MASK, .index = SOC_DBG_CTRL_TRACE_DEBUG_POLICY_CATEGORY_CATEGORY_OFFSET })
 
// Trace register to observe the valid or relocked state that is determined
// either by hardware or by software.
#define SOC_DBG_CTRL_TRACE_DEBUG_POLICY_VALID_RELOCKED_REG_OFFSET 0x14
#define SOC_DBG_CTRL_TRACE_DEBUG_POLICY_VALID_RELOCKED_REG_RESVAL 0x99u
#define SOC_DBG_CTRL_TRACE_DEBUG_POLICY_VALID_RELOCKED_VALID_MASK 0xfu
#define SOC_DBG_CTRL_TRACE_DEBUG_POLICY_VALID_RELOCKED_VALID_OFFSET 0
#define SOC_DBG_CTRL_TRACE_DEBUG_POLICY_VALID_RELOCKED_VALID_FIELD \
  ((bitfield_field32_t) { .mask = SOC_DBG_CTRL_TRACE_DEBUG_POLICY_VALID_RELOCKED_VALID_MASK, .index = SOC_DBG_CTRL_TRACE_DEBUG_POLICY_VALID_RELOCKED_VALID_OFFSET })
#define SOC_DBG_CTRL_TRACE_DEBUG_POLICY_VALID_RELOCKED_RELOCKED_MASK 0xfu
#define SOC_DBG_CTRL_TRACE_DEBUG_POLICY_VALID_RELOCKED_RELOCKED_OFFSET 4
#define SOC_DBG_CTRL_TRACE_DEBUG_POLICY_VALID_RELOCKED_RELOCKED_FIELD \
  ((bitfield_field32_t) { .mask = SOC_DBG_CTRL_TRACE_DEBUG_POLICY_VALID_RELOCKED_RELOCKED_MASK, .index = SOC_DBG_CTRL_TRACE_DEBUG_POLICY_VALID_RELOCKED_RELOCKED_OFFSET })
 
// Debug Status Register
#define SOC_DBG_CTRL_STATUS_REG_OFFSET 0x18
#define SOC_DBG_CTRL_STATUS_REG_RESVAL 0x0u
#define SOC_DBG_CTRL_STATUS_AUTH_DEBUG_INTENT_SET_BIT 0
#define SOC_DBG_CTRL_STATUS_AUTH_WINDOW_OPEN_BIT 4
#define SOC_DBG_CTRL_STATUS_AUTH_WINDOW_CLOSED_BIT 5
#define SOC_DBG_CTRL_STATUS_AUTH_UNLOCK_SUCCESS_BIT 6
#define SOC_DBG_CTRL_STATUS_AUTH_UNLOCK_FAILED_BIT 7
 
// Trace register to observe the debug category that is determined either by
// hardware or by software.
#define SOC_DBG_CTRL_JTAG_TRACE_DEBUG_POLICY_CATEGORY_REG_OFFSET 0x0
#define SOC_DBG_CTRL_JTAG_TRACE_DEBUG_POLICY_CATEGORY_REG_RESVAL 0x50u
#define SOC_DBG_CTRL_JTAG_TRACE_DEBUG_POLICY_CATEGORY_CATEGORY_MASK 0x7fu
#define SOC_DBG_CTRL_JTAG_TRACE_DEBUG_POLICY_CATEGORY_CATEGORY_OFFSET 0
#define SOC_DBG_CTRL_JTAG_TRACE_DEBUG_POLICY_CATEGORY_CATEGORY_FIELD \
  ((bitfield_field32_t) { .mask = SOC_DBG_CTRL_JTAG_TRACE_DEBUG_POLICY_CATEGORY_CATEGORY_MASK, .index = SOC_DBG_CTRL_JTAG_TRACE_DEBUG_POLICY_CATEGORY_CATEGORY_OFFSET })
 
// Trace register to observe the valid or relocked state that is determined
// either by hardware or by software.
#define SOC_DBG_CTRL_JTAG_TRACE_DEBUG_POLICY_VALID_RELOCKED_REG_OFFSET 0x4
#define SOC_DBG_CTRL_JTAG_TRACE_DEBUG_POLICY_VALID_RELOCKED_REG_RESVAL 0x99u
#define SOC_DBG_CTRL_JTAG_TRACE_DEBUG_POLICY_VALID_RELOCKED_VALID_MASK 0xfu
#define SOC_DBG_CTRL_JTAG_TRACE_DEBUG_POLICY_VALID_RELOCKED_VALID_OFFSET 0
#define SOC_DBG_CTRL_JTAG_TRACE_DEBUG_POLICY_VALID_RELOCKED_VALID_FIELD \
  ((bitfield_field32_t) { .mask = SOC_DBG_CTRL_JTAG_TRACE_DEBUG_POLICY_VALID_RELOCKED_VALID_MASK, .index = SOC_DBG_CTRL_JTAG_TRACE_DEBUG_POLICY_VALID_RELOCKED_VALID_OFFSET })
#define SOC_DBG_CTRL_JTAG_TRACE_DEBUG_POLICY_VALID_RELOCKED_RELOCKED_MASK 0xfu
#define SOC_DBG_CTRL_JTAG_TRACE_DEBUG_POLICY_VALID_RELOCKED_RELOCKED_OFFSET 4
#define SOC_DBG_CTRL_JTAG_TRACE_DEBUG_POLICY_VALID_RELOCKED_RELOCKED_FIELD \
  ((bitfield_field32_t) { .mask = SOC_DBG_CTRL_JTAG_TRACE_DEBUG_POLICY_VALID_RELOCKED_RELOCKED_MASK, .index = SOC_DBG_CTRL_JTAG_TRACE_DEBUG_POLICY_VALID_RELOCKED_RELOCKED_OFFSET })
 
// JTAG control register to interact with the boot flow.
#define SOC_DBG_CTRL_JTAG_CONTROL_REG_OFFSET 0x8
#define SOC_DBG_CTRL_JTAG_CONTROL_REG_RESVAL 0x0u
#define SOC_DBG_CTRL_JTAG_CONTROL_BOOT_CONTINUE_BIT 0
 
// Debug Status Register
#define SOC_DBG_CTRL_JTAG_STATUS_REG_OFFSET 0xc
#define SOC_DBG_CTRL_JTAG_STATUS_REG_RESVAL 0x0u
#define SOC_DBG_CTRL_JTAG_STATUS_AUTH_DEBUG_INTENT_SET_BIT 0
#define SOC_DBG_CTRL_JTAG_STATUS_AUTH_WINDOW_OPEN_BIT 4
#define SOC_DBG_CTRL_JTAG_STATUS_AUTH_WINDOW_CLOSED_BIT 5
#define SOC_DBG_CTRL_JTAG_STATUS_AUTH_UNLOCK_SUCCESS_BIT 6
#define SOC_DBG_CTRL_JTAG_STATUS_AUTH_UNLOCK_FAILED_BIT 7
 
// Debug boot status register that tells important boot state information.
#define SOC_DBG_CTRL_JTAG_BOOT_STATUS_REG_OFFSET 0x10
#define SOC_DBG_CTRL_JTAG_BOOT_STATUS_REG_RESVAL 0x0u
#define SOC_DBG_CTRL_JTAG_BOOT_STATUS_MAIN_CLK_STATUS_BIT 0
#define SOC_DBG_CTRL_JTAG_BOOT_STATUS_IO_CLK_STATUS_BIT 1
#define SOC_DBG_CTRL_JTAG_BOOT_STATUS_OTP_DONE_BIT 2
#define SOC_DBG_CTRL_JTAG_BOOT_STATUS_LC_DONE_BIT 3
#define SOC_DBG_CTRL_JTAG_BOOT_STATUS_CPU_FETCH_EN_BIT 4
#define SOC_DBG_CTRL_JTAG_BOOT_STATUS_HALT_FSM_STATE_MASK 0x3fu
#define SOC_DBG_CTRL_JTAG_BOOT_STATUS_HALT_FSM_STATE_OFFSET 5
#define SOC_DBG_CTRL_JTAG_BOOT_STATUS_HALT_FSM_STATE_FIELD \
  ((bitfield_field32_t) { .mask = SOC_DBG_CTRL_JTAG_BOOT_STATUS_HALT_FSM_STATE_MASK, .index = SOC_DBG_CTRL_JTAG_BOOT_STATUS_HALT_FSM_STATE_OFFSET })
#define SOC_DBG_CTRL_JTAG_BOOT_STATUS_BOOT_GREENLIGHT_DONE_MASK 0x7u
#define SOC_DBG_CTRL_JTAG_BOOT_STATUS_BOOT_GREENLIGHT_DONE_OFFSET 11
#define SOC_DBG_CTRL_JTAG_BOOT_STATUS_BOOT_GREENLIGHT_DONE_FIELD \
  ((bitfield_field32_t) { .mask = SOC_DBG_CTRL_JTAG_BOOT_STATUS_BOOT_GREENLIGHT_DONE_MASK, .index = SOC_DBG_CTRL_JTAG_BOOT_STATUS_BOOT_GREENLIGHT_DONE_OFFSET })
#define SOC_DBG_CTRL_JTAG_BOOT_STATUS_BOOT_GREENLIGHT_GOOD_MASK 0x7u
#define SOC_DBG_CTRL_JTAG_BOOT_STATUS_BOOT_GREENLIGHT_GOOD_OFFSET 14
#define SOC_DBG_CTRL_JTAG_BOOT_STATUS_BOOT_GREENLIGHT_GOOD_FIELD \
  ((bitfield_field32_t) { .mask = SOC_DBG_CTRL_JTAG_BOOT_STATUS_BOOT_GREENLIGHT_GOOD_MASK, .index = SOC_DBG_CTRL_JTAG_BOOT_STATUS_BOOT_GREENLIGHT_GOOD_OFFSET })
 
// Reports the current debug state coming from OTP.
#define SOC_DBG_CTRL_JTAG_TRACE_SOC_DBG_STATE_REG_OFFSET 0x14
#define SOC_DBG_CTRL_JTAG_TRACE_SOC_DBG_STATE_REG_RESVAL 0x0u
 
#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _SOC_DBG_CTRL_REG_DEFS_
// End generated register defines for soc_dbg_ctrl