rram_ctrl.h

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// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Device table API auto-generated by `dtgen`
 
#ifndef OPENTITAN_DT_RRAM_CTRL_H_
#define OPENTITAN_DT_RRAM_CTRL_H_
 
#ifdef __cplusplus
extern "C" {
#endif  // __cplusplus
 
/**
 * @file
 * @brief Device Tables (DT) for IP rram_ctrl and top earlgrey.
 *
 * This file contains the type definitions and global functions of the rram_ctrl.
 */
 
#include "hw/top/dt/api.h"
#include <stdint.h>
 
 
 
/**
 * List of instances.
 */
typedef enum dt_rram_ctrl {
  kDtRramCtrlFirst = 0, /**< First instance */
  kDtRramCtrl = 0, /**< rram_ctrl */
} dt_rram_ctrl_t;
 
enum {
  kDtRramCtrlCount = 1, /**< Number of instances */
};
 
 
/**
 * List of register blocks.
 *
 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
 */
typedef enum dt_rram_ctrl_reg_block {
  kDtRramCtrlRegBlockCore = 0, /**<  */
} dt_rram_ctrl_reg_block_t;
 
enum {
  kDtRramCtrlRegBlockCount = 1, /**< Number of register blocks */
};
 
 
/** Primary register block (associated with the "primary" set of registers that control the IP). */
static const dt_rram_ctrl_reg_block_t kDtRramCtrlRegBlockPrimary = kDtRramCtrlRegBlockCore;
 
/**
 * List of memories.
 *
 * Memories are guaranteed to start at 0 and to be consecutively numbered.
 */
typedef enum dt_rram_ctrl_memory {
  kDtRramCtrlMemoryHost = 0, /**<  */
} dt_rram_ctrl_memory_t;
 
enum {
  kDtRramCtrlMemoryCount = 1, /**< Number of memories */
};
 
 
/**
 * List of IRQs.
 *
 * IRQs are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_rram_ctrl_irq {
  kDtRramCtrlIrqWrEmpty = 0, /**< Write FIFO empty */
  kDtRramCtrlIrqWrLvl = 1, /**< Write FIFO drained to level */
  kDtRramCtrlIrqRdFull = 2, /**< Read FIFO full */
  kDtRramCtrlIrqRdLvl = 3, /**< Read FIFO filled to level */
  kDtRramCtrlIrqOpDone = 4, /**< Operation complete */
  kDtRramCtrlIrqCorrErr = 5, /**< Correctable error encountered */
} dt_rram_ctrl_irq_t;
 
enum {
  kDtRramCtrlIrqCount = 6, /**< Number of IRQs */
};
 
 
/**
 * List of Alerts.
 *
 * Alerts are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_rram_ctrl_alert {
  kDtRramCtrlAlertRecovErr = 0, /**< RRAM recoverable errors */
  kDtRramCtrlAlertFatalStdErr = 1, /**< RRAM standard fatal errors */
  kDtRramCtrlAlertFatalErr = 2, /**< RRAM fatal errors including uncorrectable ECC errors.
  
  Note that this alert is not always fatal.
  The underlying error bits in the !!FAULT_STATUS register remain set until reset, meaning the alert keeps firing.
  This doesn't hold for !!FAULT_STATUS.PHY_RELBL_ERR.
  To enable firmware dealing with multi-bit ECC errors during firmware selection and verification, these error bits can be cleared.
  After passing this stage, it is recommended that firmware classifies the corresponding alert as fatal on the receiver end, i.e, inside the alert handler. */
  kDtRramCtrlAlertFatalMacroErr = 3, /**< Fatal errors triggered inside the RRAM macro, including fatal TL-UL bus integrity faults of the test interface. */
  kDtRramCtrlAlertRecovMacroErr = 4, /**< Recoverable errors triggered inside the RRAM macro. */
} dt_rram_ctrl_alert_t;
 
enum {
  kDtRramCtrlAlertCount = 5, /**< Number of Alerts */
};
 
 
/**
 * List of clock ports.
 *
 * Clock ports are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_rram_ctrl_clock {
  kDtRramCtrlClockClk = 0, /**< Clock port clk_i */
  kDtRramCtrlClockOtp = 1, /**< Clock port clk_otp_i */
} dt_rram_ctrl_clock_t;
 
enum {
  kDtRramCtrlClockCount = 2, /**< Number of clock ports */
};
 
 
/**
 * List of reset ports.
 *
 * Reset ports are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_rram_ctrl_reset {
  kDtRramCtrlResetRst = 0, /**< Reset port rst_ni */
  kDtRramCtrlResetOtp = 1, /**< Reset port rst_otp_ni */
} dt_rram_ctrl_reset_t;
 
enum {
  kDtRramCtrlResetCount = 2, /**< Number of reset ports */
};
 
 
/**
 * List of supported hardware features.
 */
#define OPENTITAN_RRAM_CTRL_HAS_ESCALATION 1
#define OPENTITAN_RRAM_CTRL_HAS_FETCH_CODE 1
#define OPENTITAN_RRAM_CTRL_HAS_INFO_CREATOR_PARTITION 1
#define OPENTITAN_RRAM_CTRL_HAS_INFO_ISOLATED_PARTITION 1
#define OPENTITAN_RRAM_CTRL_HAS_INFO_OWNER_PARTITION 1
#define OPENTITAN_RRAM_CTRL_HAS_INIT_ROOT_SEEDS 1
#define OPENTITAN_RRAM_CTRL_HAS_INIT_SCRAMBLING_KEYS 1
#define OPENTITAN_RRAM_CTRL_HAS_MEM_PROTECTION 1
#define OPENTITAN_RRAM_CTRL_HAS_OP_HOST_READ 1
#define OPENTITAN_RRAM_CTRL_HAS_OP_PROTOCOL_CTRL 1
#define OPENTITAN_RRAM_CTRL_HAS_RMA 1
 
 
 
/**
 * Get the rram_ctrl instance from an instance ID
 *
 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
 *
 * @param inst_id Instance ID.
 * @return A rram_ctrl instance.
 *
 * **Note:** This function only makes sense if the instance ID has device type rram_ctrl,
 * otherwise the returned value is unspecified.
 */
dt_rram_ctrl_t dt_rram_ctrl_from_instance_id(dt_instance_id_t inst_id);
 
/**
 * Get the instance ID of an instance.
 *
 * @param dt Instance of rram_ctrl.
 * @return The instance ID of that instance.
 */
dt_instance_id_t dt_rram_ctrl_instance_id(dt_rram_ctrl_t dt);
 
/**
 * Get the register base address of an instance.
 *
 * @param dt Instance of rram_ctrl.
 * @param reg_block The register block requested.
 * @return The register base address of the requested block.
 */
uint32_t dt_rram_ctrl_reg_block(
    dt_rram_ctrl_t dt,
    dt_rram_ctrl_reg_block_t reg_block);
 
/**
 * Get the primary register base address of an instance.
 *
 * This is just a convenience function, equivalent to
 * `dt_rram_ctrl_reg_block(dt, kDtRramCtrlRegBlockCore)`
 *
 * @param dt Instance of rram_ctrl.
 * @return The register base address of the primary register block.
 */
static inline uint32_t dt_rram_ctrl_primary_reg_block(
    dt_rram_ctrl_t dt) {
  return dt_rram_ctrl_reg_block(dt, kDtRramCtrlRegBlockCore);
}
 
/**
 * Get the base address of a memory.
 *
 * @param dt Instance of rram_ctrl.
 * @param mem The memory requested.
 * @return The base address of the requested memory.
 */
uint32_t dt_rram_ctrl_memory_base(
    dt_rram_ctrl_t dt,
    dt_rram_ctrl_memory_t mem);
 
/**
 * Get the size of a memory.
 *
 * @param dt Instance of rram_ctrl.
 * @param mem The memory requested.
 * @return The size of the requested memory.
 */
uint32_t dt_rram_ctrl_memory_size(
    dt_rram_ctrl_t dt,
    dt_rram_ctrl_memory_t mem);
 
/**
 * Get the PLIC ID of a rram_ctrl IRQ for a given instance.
 *
 * If the instance is not connected to the PLIC, this function
 * will return `kDtPlicIrqIdNone`.
 *
 * @param dt Instance of rram_ctrl.
 * @param irq A rram_ctrl IRQ.
 * @return The PLIC ID of the IRQ of this instance.
 */
dt_plic_irq_id_t dt_rram_ctrl_irq_to_plic_id(
    dt_rram_ctrl_t dt,
    dt_rram_ctrl_irq_t irq);
 
/**
 * Convert a global IRQ ID to a local rram_ctrl IRQ type.
 *
 * @param dt Instance of rram_ctrl.
 * @param irq A PLIC ID that belongs to this instance.
 * @return The rram_ctrl IRQ, or `kDtRramCtrlIrqCount`.
 *
 * **Note:** This function assumes that the PLIC ID belongs to the instance
 * of rram_ctrl passed in parameter. In other words, it must be the case that
 * `dt_rram_ctrl_instance_id(dt) == dt_plic_id_to_instance_id(irq)`. Otherwise, this function
 * will return `kDtRramCtrlIrqCount`.
 */
dt_rram_ctrl_irq_t dt_rram_ctrl_irq_from_plic_id(
    dt_rram_ctrl_t dt,
    dt_plic_irq_id_t irq);
 
 
/**
 * Get the alert ID of a rram_ctrl alert for a given instance.
 *
 * **Note:** This function only makes sense if the instance is connected to the Alert Handler. For any
 * instances where the instance is not connected, the return value is unspecified.
 *
 * @param dt Instance of rram_ctrl.
 * @param alert A rram_ctrl alert.
 * @return The Alert Handler alert ID of the alert of this instance.
 */
dt_alert_id_t dt_rram_ctrl_alert_to_alert_id(
    dt_rram_ctrl_t dt,
    dt_rram_ctrl_alert_t alert);
 
/**
 * Convert a global alert ID to a local rram_ctrl alert type.
 *
 * @param dt Instance of rram_ctrl.
 * @param alert A global alert ID that belongs to this instance.
 * @return The rram_ctrl alert, or `kDtRramCtrlAlertCount`.
 *
 * **Note:** This function assumes that the global alert ID belongs to the
 * instance of rram_ctrl passed in parameter. In other words, it must be the case
 * that `dt_rram_ctrl_instance_id(dt) == dt_alert_id_to_instance_id(alert)`. Otherwise,
 * this function will return `kDtRramCtrlAlertCount`.
 */
dt_rram_ctrl_alert_t dt_rram_ctrl_alert_from_alert_id(
    dt_rram_ctrl_t dt,
    dt_alert_id_t alert);
 
 
 
/**
 * Get the clock signal connected to a clock port of an instance.
 *
 * @param dt Instance of rram_ctrl.
 * @param clk Clock port.
 * @return Clock signal.
 */
dt_clock_t dt_rram_ctrl_clock(
    dt_rram_ctrl_t dt,
    dt_rram_ctrl_clock_t clk);
 
/**
 * Get the reset signal connected to a reset port of an instance.
 *
 * @param dt Instance of rram_ctrl.
 * @param rst Reset port.
 * @return Reset signal.
 */
dt_reset_t dt_rram_ctrl_reset(
    dt_rram_ctrl_t dt,
    dt_rram_ctrl_reset_t rst);
 
 
 
#ifdef __cplusplus
}  // extern "C"
#endif  // __cplusplus
 
#endif  // OPENTITAN_DT_RRAM_CTRL_H_