mbx_regs.h

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/**
 * @file
 * @brief Generated register defines for mbx
 */
 
// Copyright information found in source file:
// Copyright lowRISC contributors (OpenTitan project).
 
// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#ifndef _MBX_REG_DEFS_
#define _MBX_REG_DEFS_
 
#ifdef __cplusplus
extern "C" {
#endif
// Number of alerts
#define MBX_PARAM_NUM_ALERTS 2
 
// Register width
#define MBX_PARAM_REG_WIDTH 32
 
// Common Interrupt Offsets
#define MBX_INTR_COMMON_MBX_READY_BIT 0
#define MBX_INTR_COMMON_MBX_ABORT_BIT 1
#define MBX_INTR_COMMON_MBX_ERROR_BIT 2
 
// Interrupt State Register
#define MBX_INTR_STATE_REG_OFFSET 0x0
#define MBX_INTR_STATE_REG_RESVAL 0x0u
#define MBX_INTR_STATE_MBX_READY_BIT 0
#define MBX_INTR_STATE_MBX_ABORT_BIT 1
#define MBX_INTR_STATE_MBX_ERROR_BIT 2
 
// Interrupt Enable Register
#define MBX_INTR_ENABLE_REG_OFFSET 0x4
#define MBX_INTR_ENABLE_REG_RESVAL 0x0u
#define MBX_INTR_ENABLE_MBX_READY_BIT 0
#define MBX_INTR_ENABLE_MBX_ABORT_BIT 1
#define MBX_INTR_ENABLE_MBX_ERROR_BIT 2
 
// Interrupt Test Register
#define MBX_INTR_TEST_REG_OFFSET 0x8
#define MBX_INTR_TEST_REG_RESVAL 0x0u
#define MBX_INTR_TEST_MBX_READY_BIT 0
#define MBX_INTR_TEST_MBX_ABORT_BIT 1
#define MBX_INTR_TEST_MBX_ERROR_BIT 2
 
// Alert Test Register
#define MBX_ALERT_TEST_REG_OFFSET 0xc
#define MBX_ALERT_TEST_REG_RESVAL 0x80000000u
#define MBX_ALERT_TEST_FATAL_FAULT_BIT 0
#define MBX_ALERT_TEST_RECOV_FAULT_BIT 1
#define MBX_ALERT_TEST_REGWEN_BIT 31
 
// DOE mailbox control register visible to OpenTitan
#define MBX_CONTROL_REG_OFFSET 0x10
#define MBX_CONTROL_REG_RESVAL 0x0u
#define MBX_CONTROL_ABORT_BIT 0
#define MBX_CONTROL_ERROR_BIT 1
#define MBX_CONTROL_SYS_ASYNC_MSG_BIT 3
 
// DOE mailbox status register visible to OpenTitan
#define MBX_STATUS_REG_OFFSET 0x14
#define MBX_STATUS_REG_RESVAL 0x1u
#define MBX_STATUS_BUSY_BIT 0
#define MBX_STATUS_SYS_INTR_STATE_BIT 1
#define MBX_STATUS_SYS_INTR_ENABLE_BIT 2
#define MBX_STATUS_SYS_ASYNC_ENABLE_BIT 3
 
// Used to lock the inbound/outbound base/limit configuration registers.
#define MBX_ADDRESS_RANGE_REGWEN_REG_OFFSET 0x18
#define MBX_ADDRESS_RANGE_REGWEN_REG_RESVAL 0x6u
#define MBX_ADDRESS_RANGE_REGWEN_REGWEN_MASK 0xfu
#define MBX_ADDRESS_RANGE_REGWEN_REGWEN_OFFSET 0
#define MBX_ADDRESS_RANGE_REGWEN_REGWEN_FIELD \
  ((bitfield_field32_t) { .mask = MBX_ADDRESS_RANGE_REGWEN_REGWEN_MASK, .index = MBX_ADDRESS_RANGE_REGWEN_REGWEN_OFFSET })
 
// Used to mark the inbound/outbound base/limit configuration registers to
// have a valid configuration.
#define MBX_ADDRESS_RANGE_VALID_REG_OFFSET 0x1c
#define MBX_ADDRESS_RANGE_VALID_REG_RESVAL 0x0u
#define MBX_ADDRESS_RANGE_VALID_RANGE_VALID_BIT 0
 
// Base address of SRAM region, which is used to back up the inbound mailbox
// data.
#define MBX_INBOUND_BASE_ADDRESS_REG_OFFSET 0x20
#define MBX_INBOUND_BASE_ADDRESS_REG_RESVAL 0x0u
#define MBX_INBOUND_BASE_ADDRESS_BASE_ADDRESS_MASK 0x3fffffffu
#define MBX_INBOUND_BASE_ADDRESS_BASE_ADDRESS_OFFSET 2
#define MBX_INBOUND_BASE_ADDRESS_BASE_ADDRESS_FIELD \
  ((bitfield_field32_t) { .mask = MBX_INBOUND_BASE_ADDRESS_BASE_ADDRESS_MASK, .index = MBX_INBOUND_BASE_ADDRESS_BASE_ADDRESS_OFFSET })
 
// Inclusive end address of the inbound mailbox memory range in the private
// SRAM.
#define MBX_INBOUND_LIMIT_ADDRESS_REG_OFFSET 0x24
#define MBX_INBOUND_LIMIT_ADDRESS_REG_RESVAL 0x0u
#define MBX_INBOUND_LIMIT_ADDRESS_LIMIT_MASK 0x3fffffffu
#define MBX_INBOUND_LIMIT_ADDRESS_LIMIT_OFFSET 2
#define MBX_INBOUND_LIMIT_ADDRESS_LIMIT_FIELD \
  ((bitfield_field32_t) { .mask = MBX_INBOUND_LIMIT_ADDRESS_LIMIT_MASK, .index = MBX_INBOUND_LIMIT_ADDRESS_LIMIT_OFFSET })
 
// Write pointer for the next inbound DWORD write (32 bits).
#define MBX_INBOUND_WRITE_PTR_REG_OFFSET 0x28
#define MBX_INBOUND_WRITE_PTR_REG_RESVAL 0x0u
#define MBX_INBOUND_WRITE_PTR_INBOUND_WRITE_PTR_MASK 0x3fffffffu
#define MBX_INBOUND_WRITE_PTR_INBOUND_WRITE_PTR_OFFSET 2
#define MBX_INBOUND_WRITE_PTR_INBOUND_WRITE_PTR_FIELD \
  ((bitfield_field32_t) { .mask = MBX_INBOUND_WRITE_PTR_INBOUND_WRITE_PTR_MASK, .index = MBX_INBOUND_WRITE_PTR_INBOUND_WRITE_PTR_OFFSET })
 
// Base address of SRAM region, which is used to buffer the outbound mailbox
// data.
#define MBX_OUTBOUND_BASE_ADDRESS_REG_OFFSET 0x2c
#define MBX_OUTBOUND_BASE_ADDRESS_REG_RESVAL 0x0u
#define MBX_OUTBOUND_BASE_ADDRESS_BASE_ADDRESS_MASK 0x3fffffffu
#define MBX_OUTBOUND_BASE_ADDRESS_BASE_ADDRESS_OFFSET 2
#define MBX_OUTBOUND_BASE_ADDRESS_BASE_ADDRESS_FIELD \
  ((bitfield_field32_t) { .mask = MBX_OUTBOUND_BASE_ADDRESS_BASE_ADDRESS_MASK, .index = MBX_OUTBOUND_BASE_ADDRESS_BASE_ADDRESS_OFFSET })
 
// Inclusive end address of the outbound mailbox memory range in the private
// SRAM.
#define MBX_OUTBOUND_LIMIT_ADDRESS_REG_OFFSET 0x30
#define MBX_OUTBOUND_LIMIT_ADDRESS_REG_RESVAL 0x0u
#define MBX_OUTBOUND_LIMIT_ADDRESS_LIMIT_MASK 0x3fffffffu
#define MBX_OUTBOUND_LIMIT_ADDRESS_LIMIT_OFFSET 2
#define MBX_OUTBOUND_LIMIT_ADDRESS_LIMIT_FIELD \
  ((bitfield_field32_t) { .mask = MBX_OUTBOUND_LIMIT_ADDRESS_LIMIT_MASK, .index = MBX_OUTBOUND_LIMIT_ADDRESS_LIMIT_OFFSET })
 
// Read pointer for the next outbound DWORD read.
#define MBX_OUTBOUND_READ_PTR_REG_OFFSET 0x34
#define MBX_OUTBOUND_READ_PTR_REG_RESVAL 0x0u
#define MBX_OUTBOUND_READ_PTR_OUTBOUND_READ_PTR_MASK 0x3fffffffu
#define MBX_OUTBOUND_READ_PTR_OUTBOUND_READ_PTR_OFFSET 2
#define MBX_OUTBOUND_READ_PTR_OUTBOUND_READ_PTR_FIELD \
  ((bitfield_field32_t) { .mask = MBX_OUTBOUND_READ_PTR_OUTBOUND_READ_PTR_MASK, .index = MBX_OUTBOUND_READ_PTR_OUTBOUND_READ_PTR_OFFSET })
 
// Indicates the size of the data object to be transferred out.
#define MBX_OUTBOUND_OBJECT_SIZE_REG_OFFSET 0x38
#define MBX_OUTBOUND_OBJECT_SIZE_REG_RESVAL 0x0u
#define MBX_OUTBOUND_OBJECT_SIZE_CNT_MASK 0x7ffu
#define MBX_OUTBOUND_OBJECT_SIZE_CNT_OFFSET 0
#define MBX_OUTBOUND_OBJECT_SIZE_CNT_FIELD \
  ((bitfield_field32_t) { .mask = MBX_OUTBOUND_OBJECT_SIZE_CNT_MASK, .index = MBX_OUTBOUND_OBJECT_SIZE_CNT_OFFSET })
 
// Software read-only alias of the DOE_INTR_MSG_ADDR register of the SoC
// interface for convenient access of the OT firmware.
#define MBX_DOE_INTR_MSG_ADDR_REG_OFFSET 0x3c
#define MBX_DOE_INTR_MSG_ADDR_REG_RESVAL 0x0u
 
// Software read-only alias of the DOE_INTR_MSG_DATA register of the SoC
// interface for convenient access of the OT firmware.
#define MBX_DOE_INTR_MSG_DATA_REG_OFFSET 0x40
#define MBX_DOE_INTR_MSG_DATA_REG_RESVAL 0x0u
 
// DOE mailbox control register.
#define MBX_SOC_CONTROL_REG_OFFSET 0x8
#define MBX_SOC_CONTROL_REG_RESVAL 0x0u
#define MBX_SOC_CONTROL_ABORT_BIT 0
#define MBX_SOC_CONTROL_DOE_INTR_EN_BIT 1
#define MBX_SOC_CONTROL_DOE_ASYNC_MSG_EN_BIT 3
#define MBX_SOC_CONTROL_GO_BIT 31
 
// DOE mailbox status register
#define MBX_SOC_STATUS_REG_OFFSET 0xc
#define MBX_SOC_STATUS_REG_RESVAL 0x1u
#define MBX_SOC_STATUS_BUSY_BIT 0
#define MBX_SOC_STATUS_DOE_INTR_STATUS_BIT 1
#define MBX_SOC_STATUS_ERROR_BIT 2
#define MBX_SOC_STATUS_DOE_ASYNC_MSG_STATUS_BIT 3
#define MBX_SOC_STATUS_READY_BIT 31
 
// Memory area: DOE mailbox write data register.
#define MBX_WDATA_REG_OFFSET 0x10
#define MBX_WDATA_SIZE_WORDS 1
#define MBX_WDATA_SIZE_BYTES 4
// Memory area: DOE mailbox read data register
#define MBX_RDATA_REG_OFFSET 0x14
#define MBX_RDATA_SIZE_WORDS 1
#define MBX_RDATA_SIZE_BYTES 4
// Utilized by the mailbox responder to send an interrupt message to the
// requester via a write to the configured address.
#define MBX_SOC_DOE_INTR_MSG_ADDR_REG_OFFSET 0x18
#define MBX_SOC_DOE_INTR_MSG_ADDR_REG_RESVAL 0x0u
 
// Interrupt message data to be sent to the address configured in the
// DOE_INTR_MSG_ADDR register.
#define MBX_SOC_DOE_INTR_MSG_DATA_REG_OFFSET 0x1c
#define MBX_SOC_DOE_INTR_MSG_DATA_REG_RESVAL 0x0u
 
#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _MBX_REG_DEFS_
// End generated register defines for mbx