flash_ctrl_regs.h

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/**
 * @file
 * @brief Generated register defines for flash_ctrl
 */
 
// Copyright information found in source file:
// Copyright lowRISC contributors (OpenTitan project).
 
// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
 
#ifndef _FLASH_CTRL_REG_DEFS_
#define _FLASH_CTRL_REG_DEFS_
 
#ifdef __cplusplus
extern "C" {
#endif
// Number of flash banks
#define FLASH_CTRL_PARAM_REG_NUM_BANKS 2
 
// Number of pages per bank
#define FLASH_CTRL_PARAM_REG_PAGES_PER_BANK 16
 
// Program resolution window in bytes
#define FLASH_CTRL_PARAM_REG_BUS_PGM_RES_BYTES 64
 
// Number of bits needed to represent the pages within a bank
#define FLASH_CTRL_PARAM_REG_PAGE_WIDTH 4
 
// Number of bits needed to represent the number of banks
#define FLASH_CTRL_PARAM_REG_BANK_WIDTH 1
 
// Number of configurable flash regions
#define FLASH_CTRL_PARAM_NUM_REGIONS 8
 
// Number of info partition types
#define FLASH_CTRL_PARAM_NUM_INFO_TYPES 3
 
// Number of configurable flash info pages for info type 0
#define FLASH_CTRL_PARAM_NUM_INFOS0 10
 
// Number of configurable flash info pages for info type 1
#define FLASH_CTRL_PARAM_NUM_INFOS1 1
 
// Number of configurable flash info pages for info type 2
#define FLASH_CTRL_PARAM_NUM_INFOS2 2
 
// Number of words per page
#define FLASH_CTRL_PARAM_WORDS_PER_PAGE 256
 
// Number of bytes per word
#define FLASH_CTRL_PARAM_BYTES_PER_WORD 8
 
// Number of bytes per page
#define FLASH_CTRL_PARAM_BYTES_PER_PAGE 2048
 
// Number of bytes per bank
#define FLASH_CTRL_PARAM_BYTES_PER_BANK 32768
 
// Constant value that enables flash execution
#define FLASH_CTRL_PARAM_EXEC_EN 2724870391
 
// Maximum depth for read / program FIFOs
#define FLASH_CTRL_PARAM_MAX_FIFO_DEPTH 16
 
// Maximum depth for read / program FIFOs
#define FLASH_CTRL_PARAM_MAX_FIFO_WIDTH 5
 
// Number of alerts
#define FLASH_CTRL_PARAM_NUM_ALERTS 5
 
// Register width
#define FLASH_CTRL_PARAM_REG_WIDTH 32
 
// Common Interrupt Offsets
#define FLASH_CTRL_INTR_COMMON_PROG_EMPTY_BIT 0
#define FLASH_CTRL_INTR_COMMON_PROG_LVL_BIT 1
#define FLASH_CTRL_INTR_COMMON_RD_FULL_BIT 2
#define FLASH_CTRL_INTR_COMMON_RD_LVL_BIT 3
#define FLASH_CTRL_INTR_COMMON_OP_DONE_BIT 4
#define FLASH_CTRL_INTR_COMMON_CORR_ERR_BIT 5
 
// Interrupt State Register
#define FLASH_CTRL_INTR_STATE_REG_OFFSET 0x0
#define FLASH_CTRL_INTR_STATE_REG_RESVAL 0x3u
#define FLASH_CTRL_INTR_STATE_PROG_EMPTY_BIT 0
#define FLASH_CTRL_INTR_STATE_PROG_LVL_BIT 1
#define FLASH_CTRL_INTR_STATE_RD_FULL_BIT 2
#define FLASH_CTRL_INTR_STATE_RD_LVL_BIT 3
#define FLASH_CTRL_INTR_STATE_OP_DONE_BIT 4
#define FLASH_CTRL_INTR_STATE_CORR_ERR_BIT 5
 
// Interrupt Enable Register
#define FLASH_CTRL_INTR_ENABLE_REG_OFFSET 0x4
#define FLASH_CTRL_INTR_ENABLE_REG_RESVAL 0x0u
#define FLASH_CTRL_INTR_ENABLE_PROG_EMPTY_BIT 0
#define FLASH_CTRL_INTR_ENABLE_PROG_LVL_BIT 1
#define FLASH_CTRL_INTR_ENABLE_RD_FULL_BIT 2
#define FLASH_CTRL_INTR_ENABLE_RD_LVL_BIT 3
#define FLASH_CTRL_INTR_ENABLE_OP_DONE_BIT 4
#define FLASH_CTRL_INTR_ENABLE_CORR_ERR_BIT 5
 
// Interrupt Test Register
#define FLASH_CTRL_INTR_TEST_REG_OFFSET 0x8
#define FLASH_CTRL_INTR_TEST_REG_RESVAL 0x0u
#define FLASH_CTRL_INTR_TEST_PROG_EMPTY_BIT 0
#define FLASH_CTRL_INTR_TEST_PROG_LVL_BIT 1
#define FLASH_CTRL_INTR_TEST_RD_FULL_BIT 2
#define FLASH_CTRL_INTR_TEST_RD_LVL_BIT 3
#define FLASH_CTRL_INTR_TEST_OP_DONE_BIT 4
#define FLASH_CTRL_INTR_TEST_CORR_ERR_BIT 5
 
// Alert Test Register
#define FLASH_CTRL_ALERT_TEST_REG_OFFSET 0xc
#define FLASH_CTRL_ALERT_TEST_REG_RESVAL 0x80000000u
#define FLASH_CTRL_ALERT_TEST_RECOV_ERR_BIT 0
#define FLASH_CTRL_ALERT_TEST_FATAL_STD_ERR_BIT 1
#define FLASH_CTRL_ALERT_TEST_FATAL_ERR_BIT 2
#define FLASH_CTRL_ALERT_TEST_FATAL_PRIM_FLASH_ALERT_BIT 3
#define FLASH_CTRL_ALERT_TEST_RECOV_PRIM_FLASH_ALERT_BIT 4
#define FLASH_CTRL_ALERT_TEST_REGWEN_BIT 31
 
// Disable flash functionality
#define FLASH_CTRL_DIS_REG_OFFSET 0x10
#define FLASH_CTRL_DIS_REG_RESVAL 0x9u
#define FLASH_CTRL_DIS_VAL_MASK 0xfu
#define FLASH_CTRL_DIS_VAL_OFFSET 0
#define FLASH_CTRL_DIS_VAL_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_DIS_VAL_MASK, .index = FLASH_CTRL_DIS_VAL_OFFSET })
 
// Controls whether flash can be used for code execution fetches
#define FLASH_CTRL_EXEC_REG_OFFSET 0x14
#define FLASH_CTRL_EXEC_REG_RESVAL 0x0u
 
// Controller init register
#define FLASH_CTRL_INIT_REG_OFFSET 0x18
#define FLASH_CTRL_INIT_REG_RESVAL 0x0u
#define FLASH_CTRL_INIT_VAL_BIT 0
 
// Controls the configurability of the !!CONTROL register.
#define FLASH_CTRL_CTRL_REGWEN_REG_OFFSET 0x1c
#define FLASH_CTRL_CTRL_REGWEN_REG_RESVAL 0x1u
#define FLASH_CTRL_CTRL_REGWEN_EN_BIT 0
 
// Control register
#define FLASH_CTRL_CONTROL_REG_OFFSET 0x20
#define FLASH_CTRL_CONTROL_REG_RESVAL 0x0u
#define FLASH_CTRL_CONTROL_START_BIT 0
#define FLASH_CTRL_CONTROL_OP_MASK 0x3u
#define FLASH_CTRL_CONTROL_OP_OFFSET 4
#define FLASH_CTRL_CONTROL_OP_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CONTROL_OP_MASK, .index = FLASH_CTRL_CONTROL_OP_OFFSET })
#define FLASH_CTRL_CONTROL_OP_VALUE_READ 0x0
#define FLASH_CTRL_CONTROL_OP_VALUE_PROG 0x1
#define FLASH_CTRL_CONTROL_OP_VALUE_ERASE 0x2
#define FLASH_CTRL_CONTROL_PROG_SEL_BIT 6
#define FLASH_CTRL_CONTROL_PROG_SEL_VALUE_NORMAL_PROGRAM 0x0
#define FLASH_CTRL_CONTROL_PROG_SEL_VALUE_PROGRAM_REPAIR 0x1
#define FLASH_CTRL_CONTROL_ERASE_SEL_BIT 7
#define FLASH_CTRL_CONTROL_ERASE_SEL_VALUE_PAGE_ERASE 0x0
#define FLASH_CTRL_CONTROL_ERASE_SEL_VALUE_BANK_ERASE 0x1
#define FLASH_CTRL_CONTROL_PARTITION_SEL_BIT 8
#define FLASH_CTRL_CONTROL_INFO_SEL_MASK 0x3u
#define FLASH_CTRL_CONTROL_INFO_SEL_OFFSET 9
#define FLASH_CTRL_CONTROL_INFO_SEL_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CONTROL_INFO_SEL_MASK, .index = FLASH_CTRL_CONTROL_INFO_SEL_OFFSET })
#define FLASH_CTRL_CONTROL_NUM_MASK 0xfffu
#define FLASH_CTRL_CONTROL_NUM_OFFSET 16
#define FLASH_CTRL_CONTROL_NUM_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CONTROL_NUM_MASK, .index = FLASH_CTRL_CONTROL_NUM_OFFSET })
 
// Address for flash operation
#define FLASH_CTRL_ADDR_REG_OFFSET 0x24
#define FLASH_CTRL_ADDR_REG_RESVAL 0x0u
#define FLASH_CTRL_ADDR_START_MASK 0xffffu
#define FLASH_CTRL_ADDR_START_OFFSET 0
#define FLASH_CTRL_ADDR_START_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_ADDR_START_MASK, .index = FLASH_CTRL_ADDR_START_OFFSET })
 
// Enable different program types
#define FLASH_CTRL_PROG_TYPE_EN_REG_OFFSET 0x28
#define FLASH_CTRL_PROG_TYPE_EN_REG_RESVAL 0x3u
#define FLASH_CTRL_PROG_TYPE_EN_NORMAL_BIT 0
#define FLASH_CTRL_PROG_TYPE_EN_REPAIR_BIT 1
 
// Suspend erase
#define FLASH_CTRL_ERASE_SUSPEND_REG_OFFSET 0x2c
#define FLASH_CTRL_ERASE_SUSPEND_REG_RESVAL 0x0u
#define FLASH_CTRL_ERASE_SUSPEND_REQ_BIT 0
 
// Memory region registers configuration enable. (common parameters)
#define FLASH_CTRL_REGION_CFG_REGWEN_REGION_FIELD_WIDTH 1
#define FLASH_CTRL_REGION_CFG_REGWEN_MULTIREG_COUNT 8
 
// Memory region registers configuration enable.
#define FLASH_CTRL_REGION_CFG_REGWEN_0_REG_OFFSET 0x30
#define FLASH_CTRL_REGION_CFG_REGWEN_0_REG_RESVAL 0x1u
#define FLASH_CTRL_REGION_CFG_REGWEN_0_REGION_0_BIT 0
#define FLASH_CTRL_REGION_CFG_REGWEN_0_REGION_0_VALUE_REGION_LOCKED 0x0
#define FLASH_CTRL_REGION_CFG_REGWEN_0_REGION_0_VALUE_REGION_ENABLED 0x1
 
// Memory region registers configuration enable.
#define FLASH_CTRL_REGION_CFG_REGWEN_1_REG_OFFSET 0x34
#define FLASH_CTRL_REGION_CFG_REGWEN_1_REG_RESVAL 0x1u
#define FLASH_CTRL_REGION_CFG_REGWEN_1_REGION_1_BIT 0
 
// Memory region registers configuration enable.
#define FLASH_CTRL_REGION_CFG_REGWEN_2_REG_OFFSET 0x38
#define FLASH_CTRL_REGION_CFG_REGWEN_2_REG_RESVAL 0x1u
#define FLASH_CTRL_REGION_CFG_REGWEN_2_REGION_2_BIT 0
 
// Memory region registers configuration enable.
#define FLASH_CTRL_REGION_CFG_REGWEN_3_REG_OFFSET 0x3c
#define FLASH_CTRL_REGION_CFG_REGWEN_3_REG_RESVAL 0x1u
#define FLASH_CTRL_REGION_CFG_REGWEN_3_REGION_3_BIT 0
 
// Memory region registers configuration enable.
#define FLASH_CTRL_REGION_CFG_REGWEN_4_REG_OFFSET 0x40
#define FLASH_CTRL_REGION_CFG_REGWEN_4_REG_RESVAL 0x1u
#define FLASH_CTRL_REGION_CFG_REGWEN_4_REGION_4_BIT 0
 
// Memory region registers configuration enable.
#define FLASH_CTRL_REGION_CFG_REGWEN_5_REG_OFFSET 0x44
#define FLASH_CTRL_REGION_CFG_REGWEN_5_REG_RESVAL 0x1u
#define FLASH_CTRL_REGION_CFG_REGWEN_5_REGION_5_BIT 0
 
// Memory region registers configuration enable.
#define FLASH_CTRL_REGION_CFG_REGWEN_6_REG_OFFSET 0x48
#define FLASH_CTRL_REGION_CFG_REGWEN_6_REG_RESVAL 0x1u
#define FLASH_CTRL_REGION_CFG_REGWEN_6_REGION_6_BIT 0
 
// Memory region registers configuration enable.
#define FLASH_CTRL_REGION_CFG_REGWEN_7_REG_OFFSET 0x4c
#define FLASH_CTRL_REGION_CFG_REGWEN_7_REG_RESVAL 0x1u
#define FLASH_CTRL_REGION_CFG_REGWEN_7_REGION_7_BIT 0
 
// Memory property configuration for data partition (common parameters)
#define FLASH_CTRL_MP_REGION_CFG_EN_FIELD_WIDTH 4
#define FLASH_CTRL_MP_REGION_CFG_RD_EN_FIELD_WIDTH 4
#define FLASH_CTRL_MP_REGION_CFG_PROG_EN_FIELD_WIDTH 4
#define FLASH_CTRL_MP_REGION_CFG_ERASE_EN_FIELD_WIDTH 4
#define FLASH_CTRL_MP_REGION_CFG_SCRAMBLE_EN_FIELD_WIDTH 4
#define FLASH_CTRL_MP_REGION_CFG_ECC_EN_FIELD_WIDTH 4
#define FLASH_CTRL_MP_REGION_CFG_HE_EN_FIELD_WIDTH 4
#define FLASH_CTRL_MP_REGION_CFG_MULTIREG_COUNT 8
 
// Memory property configuration for data partition
#define FLASH_CTRL_MP_REGION_CFG_0_REG_OFFSET 0x50
#define FLASH_CTRL_MP_REGION_CFG_0_REG_RESVAL 0x9999999u
#define FLASH_CTRL_MP_REGION_CFG_0_EN_0_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_0_EN_0_OFFSET 0
#define FLASH_CTRL_MP_REGION_CFG_0_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_0_EN_0_MASK, .index = FLASH_CTRL_MP_REGION_CFG_0_EN_0_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_0_RD_EN_0_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_0_RD_EN_0_OFFSET 4
#define FLASH_CTRL_MP_REGION_CFG_0_RD_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_0_RD_EN_0_MASK, .index = FLASH_CTRL_MP_REGION_CFG_0_RD_EN_0_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_0_PROG_EN_0_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_0_PROG_EN_0_OFFSET 8
#define FLASH_CTRL_MP_REGION_CFG_0_PROG_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_0_PROG_EN_0_MASK, .index = FLASH_CTRL_MP_REGION_CFG_0_PROG_EN_0_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_0_ERASE_EN_0_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_0_ERASE_EN_0_OFFSET 12
#define FLASH_CTRL_MP_REGION_CFG_0_ERASE_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_0_ERASE_EN_0_MASK, .index = FLASH_CTRL_MP_REGION_CFG_0_ERASE_EN_0_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_OFFSET 16
#define FLASH_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_MASK, .index = FLASH_CTRL_MP_REGION_CFG_0_SCRAMBLE_EN_0_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_0_ECC_EN_0_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_0_ECC_EN_0_OFFSET 20
#define FLASH_CTRL_MP_REGION_CFG_0_ECC_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_0_ECC_EN_0_MASK, .index = FLASH_CTRL_MP_REGION_CFG_0_ECC_EN_0_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_0_HE_EN_0_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_0_HE_EN_0_OFFSET 24
#define FLASH_CTRL_MP_REGION_CFG_0_HE_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_0_HE_EN_0_MASK, .index = FLASH_CTRL_MP_REGION_CFG_0_HE_EN_0_OFFSET })
 
// Memory property configuration for data partition
#define FLASH_CTRL_MP_REGION_CFG_1_REG_OFFSET 0x54
#define FLASH_CTRL_MP_REGION_CFG_1_REG_RESVAL 0x9999999u
#define FLASH_CTRL_MP_REGION_CFG_1_EN_1_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_1_EN_1_OFFSET 0
#define FLASH_CTRL_MP_REGION_CFG_1_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_1_EN_1_MASK, .index = FLASH_CTRL_MP_REGION_CFG_1_EN_1_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_1_RD_EN_1_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_1_RD_EN_1_OFFSET 4
#define FLASH_CTRL_MP_REGION_CFG_1_RD_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_1_RD_EN_1_MASK, .index = FLASH_CTRL_MP_REGION_CFG_1_RD_EN_1_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_1_PROG_EN_1_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_1_PROG_EN_1_OFFSET 8
#define FLASH_CTRL_MP_REGION_CFG_1_PROG_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_1_PROG_EN_1_MASK, .index = FLASH_CTRL_MP_REGION_CFG_1_PROG_EN_1_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_1_ERASE_EN_1_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_1_ERASE_EN_1_OFFSET 12
#define FLASH_CTRL_MP_REGION_CFG_1_ERASE_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_1_ERASE_EN_1_MASK, .index = FLASH_CTRL_MP_REGION_CFG_1_ERASE_EN_1_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_1_SCRAMBLE_EN_1_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_1_SCRAMBLE_EN_1_OFFSET 16
#define FLASH_CTRL_MP_REGION_CFG_1_SCRAMBLE_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_1_SCRAMBLE_EN_1_MASK, .index = FLASH_CTRL_MP_REGION_CFG_1_SCRAMBLE_EN_1_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_1_ECC_EN_1_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_1_ECC_EN_1_OFFSET 20
#define FLASH_CTRL_MP_REGION_CFG_1_ECC_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_1_ECC_EN_1_MASK, .index = FLASH_CTRL_MP_REGION_CFG_1_ECC_EN_1_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_1_HE_EN_1_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_1_HE_EN_1_OFFSET 24
#define FLASH_CTRL_MP_REGION_CFG_1_HE_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_1_HE_EN_1_MASK, .index = FLASH_CTRL_MP_REGION_CFG_1_HE_EN_1_OFFSET })
 
// Memory property configuration for data partition
#define FLASH_CTRL_MP_REGION_CFG_2_REG_OFFSET 0x58
#define FLASH_CTRL_MP_REGION_CFG_2_REG_RESVAL 0x9999999u
#define FLASH_CTRL_MP_REGION_CFG_2_EN_2_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_2_EN_2_OFFSET 0
#define FLASH_CTRL_MP_REGION_CFG_2_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_2_EN_2_MASK, .index = FLASH_CTRL_MP_REGION_CFG_2_EN_2_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_2_RD_EN_2_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_2_RD_EN_2_OFFSET 4
#define FLASH_CTRL_MP_REGION_CFG_2_RD_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_2_RD_EN_2_MASK, .index = FLASH_CTRL_MP_REGION_CFG_2_RD_EN_2_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_2_PROG_EN_2_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_2_PROG_EN_2_OFFSET 8
#define FLASH_CTRL_MP_REGION_CFG_2_PROG_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_2_PROG_EN_2_MASK, .index = FLASH_CTRL_MP_REGION_CFG_2_PROG_EN_2_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_2_ERASE_EN_2_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_2_ERASE_EN_2_OFFSET 12
#define FLASH_CTRL_MP_REGION_CFG_2_ERASE_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_2_ERASE_EN_2_MASK, .index = FLASH_CTRL_MP_REGION_CFG_2_ERASE_EN_2_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_2_SCRAMBLE_EN_2_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_2_SCRAMBLE_EN_2_OFFSET 16
#define FLASH_CTRL_MP_REGION_CFG_2_SCRAMBLE_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_2_SCRAMBLE_EN_2_MASK, .index = FLASH_CTRL_MP_REGION_CFG_2_SCRAMBLE_EN_2_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_2_ECC_EN_2_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_2_ECC_EN_2_OFFSET 20
#define FLASH_CTRL_MP_REGION_CFG_2_ECC_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_2_ECC_EN_2_MASK, .index = FLASH_CTRL_MP_REGION_CFG_2_ECC_EN_2_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_2_HE_EN_2_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_2_HE_EN_2_OFFSET 24
#define FLASH_CTRL_MP_REGION_CFG_2_HE_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_2_HE_EN_2_MASK, .index = FLASH_CTRL_MP_REGION_CFG_2_HE_EN_2_OFFSET })
 
// Memory property configuration for data partition
#define FLASH_CTRL_MP_REGION_CFG_3_REG_OFFSET 0x5c
#define FLASH_CTRL_MP_REGION_CFG_3_REG_RESVAL 0x9999999u
#define FLASH_CTRL_MP_REGION_CFG_3_EN_3_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_3_EN_3_OFFSET 0
#define FLASH_CTRL_MP_REGION_CFG_3_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_3_EN_3_MASK, .index = FLASH_CTRL_MP_REGION_CFG_3_EN_3_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_3_RD_EN_3_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_3_RD_EN_3_OFFSET 4
#define FLASH_CTRL_MP_REGION_CFG_3_RD_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_3_RD_EN_3_MASK, .index = FLASH_CTRL_MP_REGION_CFG_3_RD_EN_3_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_3_PROG_EN_3_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_3_PROG_EN_3_OFFSET 8
#define FLASH_CTRL_MP_REGION_CFG_3_PROG_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_3_PROG_EN_3_MASK, .index = FLASH_CTRL_MP_REGION_CFG_3_PROG_EN_3_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_3_ERASE_EN_3_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_3_ERASE_EN_3_OFFSET 12
#define FLASH_CTRL_MP_REGION_CFG_3_ERASE_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_3_ERASE_EN_3_MASK, .index = FLASH_CTRL_MP_REGION_CFG_3_ERASE_EN_3_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_3_SCRAMBLE_EN_3_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_3_SCRAMBLE_EN_3_OFFSET 16
#define FLASH_CTRL_MP_REGION_CFG_3_SCRAMBLE_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_3_SCRAMBLE_EN_3_MASK, .index = FLASH_CTRL_MP_REGION_CFG_3_SCRAMBLE_EN_3_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_3_ECC_EN_3_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_3_ECC_EN_3_OFFSET 20
#define FLASH_CTRL_MP_REGION_CFG_3_ECC_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_3_ECC_EN_3_MASK, .index = FLASH_CTRL_MP_REGION_CFG_3_ECC_EN_3_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_3_HE_EN_3_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_3_HE_EN_3_OFFSET 24
#define FLASH_CTRL_MP_REGION_CFG_3_HE_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_3_HE_EN_3_MASK, .index = FLASH_CTRL_MP_REGION_CFG_3_HE_EN_3_OFFSET })
 
// Memory property configuration for data partition
#define FLASH_CTRL_MP_REGION_CFG_4_REG_OFFSET 0x60
#define FLASH_CTRL_MP_REGION_CFG_4_REG_RESVAL 0x9999999u
#define FLASH_CTRL_MP_REGION_CFG_4_EN_4_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_4_EN_4_OFFSET 0
#define FLASH_CTRL_MP_REGION_CFG_4_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_4_EN_4_MASK, .index = FLASH_CTRL_MP_REGION_CFG_4_EN_4_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_4_RD_EN_4_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_4_RD_EN_4_OFFSET 4
#define FLASH_CTRL_MP_REGION_CFG_4_RD_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_4_RD_EN_4_MASK, .index = FLASH_CTRL_MP_REGION_CFG_4_RD_EN_4_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_4_PROG_EN_4_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_4_PROG_EN_4_OFFSET 8
#define FLASH_CTRL_MP_REGION_CFG_4_PROG_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_4_PROG_EN_4_MASK, .index = FLASH_CTRL_MP_REGION_CFG_4_PROG_EN_4_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_4_ERASE_EN_4_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_4_ERASE_EN_4_OFFSET 12
#define FLASH_CTRL_MP_REGION_CFG_4_ERASE_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_4_ERASE_EN_4_MASK, .index = FLASH_CTRL_MP_REGION_CFG_4_ERASE_EN_4_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_4_SCRAMBLE_EN_4_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_4_SCRAMBLE_EN_4_OFFSET 16
#define FLASH_CTRL_MP_REGION_CFG_4_SCRAMBLE_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_4_SCRAMBLE_EN_4_MASK, .index = FLASH_CTRL_MP_REGION_CFG_4_SCRAMBLE_EN_4_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_4_ECC_EN_4_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_4_ECC_EN_4_OFFSET 20
#define FLASH_CTRL_MP_REGION_CFG_4_ECC_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_4_ECC_EN_4_MASK, .index = FLASH_CTRL_MP_REGION_CFG_4_ECC_EN_4_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_4_HE_EN_4_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_4_HE_EN_4_OFFSET 24
#define FLASH_CTRL_MP_REGION_CFG_4_HE_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_4_HE_EN_4_MASK, .index = FLASH_CTRL_MP_REGION_CFG_4_HE_EN_4_OFFSET })
 
// Memory property configuration for data partition
#define FLASH_CTRL_MP_REGION_CFG_5_REG_OFFSET 0x64
#define FLASH_CTRL_MP_REGION_CFG_5_REG_RESVAL 0x9999999u
#define FLASH_CTRL_MP_REGION_CFG_5_EN_5_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_5_EN_5_OFFSET 0
#define FLASH_CTRL_MP_REGION_CFG_5_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_5_EN_5_MASK, .index = FLASH_CTRL_MP_REGION_CFG_5_EN_5_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_5_RD_EN_5_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_5_RD_EN_5_OFFSET 4
#define FLASH_CTRL_MP_REGION_CFG_5_RD_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_5_RD_EN_5_MASK, .index = FLASH_CTRL_MP_REGION_CFG_5_RD_EN_5_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_5_PROG_EN_5_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_5_PROG_EN_5_OFFSET 8
#define FLASH_CTRL_MP_REGION_CFG_5_PROG_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_5_PROG_EN_5_MASK, .index = FLASH_CTRL_MP_REGION_CFG_5_PROG_EN_5_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_5_ERASE_EN_5_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_5_ERASE_EN_5_OFFSET 12
#define FLASH_CTRL_MP_REGION_CFG_5_ERASE_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_5_ERASE_EN_5_MASK, .index = FLASH_CTRL_MP_REGION_CFG_5_ERASE_EN_5_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_5_SCRAMBLE_EN_5_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_5_SCRAMBLE_EN_5_OFFSET 16
#define FLASH_CTRL_MP_REGION_CFG_5_SCRAMBLE_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_5_SCRAMBLE_EN_5_MASK, .index = FLASH_CTRL_MP_REGION_CFG_5_SCRAMBLE_EN_5_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_5_ECC_EN_5_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_5_ECC_EN_5_OFFSET 20
#define FLASH_CTRL_MP_REGION_CFG_5_ECC_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_5_ECC_EN_5_MASK, .index = FLASH_CTRL_MP_REGION_CFG_5_ECC_EN_5_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_5_HE_EN_5_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_5_HE_EN_5_OFFSET 24
#define FLASH_CTRL_MP_REGION_CFG_5_HE_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_5_HE_EN_5_MASK, .index = FLASH_CTRL_MP_REGION_CFG_5_HE_EN_5_OFFSET })
 
// Memory property configuration for data partition
#define FLASH_CTRL_MP_REGION_CFG_6_REG_OFFSET 0x68
#define FLASH_CTRL_MP_REGION_CFG_6_REG_RESVAL 0x9999999u
#define FLASH_CTRL_MP_REGION_CFG_6_EN_6_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_6_EN_6_OFFSET 0
#define FLASH_CTRL_MP_REGION_CFG_6_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_6_EN_6_MASK, .index = FLASH_CTRL_MP_REGION_CFG_6_EN_6_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_6_RD_EN_6_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_6_RD_EN_6_OFFSET 4
#define FLASH_CTRL_MP_REGION_CFG_6_RD_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_6_RD_EN_6_MASK, .index = FLASH_CTRL_MP_REGION_CFG_6_RD_EN_6_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_6_PROG_EN_6_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_6_PROG_EN_6_OFFSET 8
#define FLASH_CTRL_MP_REGION_CFG_6_PROG_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_6_PROG_EN_6_MASK, .index = FLASH_CTRL_MP_REGION_CFG_6_PROG_EN_6_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_6_ERASE_EN_6_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_6_ERASE_EN_6_OFFSET 12
#define FLASH_CTRL_MP_REGION_CFG_6_ERASE_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_6_ERASE_EN_6_MASK, .index = FLASH_CTRL_MP_REGION_CFG_6_ERASE_EN_6_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_6_SCRAMBLE_EN_6_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_6_SCRAMBLE_EN_6_OFFSET 16
#define FLASH_CTRL_MP_REGION_CFG_6_SCRAMBLE_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_6_SCRAMBLE_EN_6_MASK, .index = FLASH_CTRL_MP_REGION_CFG_6_SCRAMBLE_EN_6_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_6_ECC_EN_6_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_6_ECC_EN_6_OFFSET 20
#define FLASH_CTRL_MP_REGION_CFG_6_ECC_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_6_ECC_EN_6_MASK, .index = FLASH_CTRL_MP_REGION_CFG_6_ECC_EN_6_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_6_HE_EN_6_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_6_HE_EN_6_OFFSET 24
#define FLASH_CTRL_MP_REGION_CFG_6_HE_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_6_HE_EN_6_MASK, .index = FLASH_CTRL_MP_REGION_CFG_6_HE_EN_6_OFFSET })
 
// Memory property configuration for data partition
#define FLASH_CTRL_MP_REGION_CFG_7_REG_OFFSET 0x6c
#define FLASH_CTRL_MP_REGION_CFG_7_REG_RESVAL 0x9999999u
#define FLASH_CTRL_MP_REGION_CFG_7_EN_7_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_7_EN_7_OFFSET 0
#define FLASH_CTRL_MP_REGION_CFG_7_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_7_EN_7_MASK, .index = FLASH_CTRL_MP_REGION_CFG_7_EN_7_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_7_RD_EN_7_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_7_RD_EN_7_OFFSET 4
#define FLASH_CTRL_MP_REGION_CFG_7_RD_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_7_RD_EN_7_MASK, .index = FLASH_CTRL_MP_REGION_CFG_7_RD_EN_7_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_7_PROG_EN_7_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_7_PROG_EN_7_OFFSET 8
#define FLASH_CTRL_MP_REGION_CFG_7_PROG_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_7_PROG_EN_7_MASK, .index = FLASH_CTRL_MP_REGION_CFG_7_PROG_EN_7_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_7_ERASE_EN_7_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_7_ERASE_EN_7_OFFSET 12
#define FLASH_CTRL_MP_REGION_CFG_7_ERASE_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_7_ERASE_EN_7_MASK, .index = FLASH_CTRL_MP_REGION_CFG_7_ERASE_EN_7_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_7_SCRAMBLE_EN_7_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_7_SCRAMBLE_EN_7_OFFSET 16
#define FLASH_CTRL_MP_REGION_CFG_7_SCRAMBLE_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_7_SCRAMBLE_EN_7_MASK, .index = FLASH_CTRL_MP_REGION_CFG_7_SCRAMBLE_EN_7_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_7_ECC_EN_7_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_7_ECC_EN_7_OFFSET 20
#define FLASH_CTRL_MP_REGION_CFG_7_ECC_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_7_ECC_EN_7_MASK, .index = FLASH_CTRL_MP_REGION_CFG_7_ECC_EN_7_OFFSET })
#define FLASH_CTRL_MP_REGION_CFG_7_HE_EN_7_MASK 0xfu
#define FLASH_CTRL_MP_REGION_CFG_7_HE_EN_7_OFFSET 24
#define FLASH_CTRL_MP_REGION_CFG_7_HE_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_CFG_7_HE_EN_7_MASK, .index = FLASH_CTRL_MP_REGION_CFG_7_HE_EN_7_OFFSET })
 
// Memory base and size configuration for data partition (common parameters)
#define FLASH_CTRL_MP_REGION_BASE_FIELD_WIDTH 5
#define FLASH_CTRL_MP_REGION_SIZE_FIELD_WIDTH 6
#define FLASH_CTRL_MP_REGION_MULTIREG_COUNT 8
 
// Memory base and size configuration for data partition
#define FLASH_CTRL_MP_REGION_0_REG_OFFSET 0x70
#define FLASH_CTRL_MP_REGION_0_REG_RESVAL 0x0u
#define FLASH_CTRL_MP_REGION_0_BASE_0_MASK 0x1fu
#define FLASH_CTRL_MP_REGION_0_BASE_0_OFFSET 0
#define FLASH_CTRL_MP_REGION_0_BASE_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_0_BASE_0_MASK, .index = FLASH_CTRL_MP_REGION_0_BASE_0_OFFSET })
#define FLASH_CTRL_MP_REGION_0_SIZE_0_MASK 0x3fu
#define FLASH_CTRL_MP_REGION_0_SIZE_0_OFFSET 5
#define FLASH_CTRL_MP_REGION_0_SIZE_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_0_SIZE_0_MASK, .index = FLASH_CTRL_MP_REGION_0_SIZE_0_OFFSET })
 
// Memory base and size configuration for data partition
#define FLASH_CTRL_MP_REGION_1_REG_OFFSET 0x74
#define FLASH_CTRL_MP_REGION_1_REG_RESVAL 0x0u
#define FLASH_CTRL_MP_REGION_1_BASE_1_MASK 0x1fu
#define FLASH_CTRL_MP_REGION_1_BASE_1_OFFSET 0
#define FLASH_CTRL_MP_REGION_1_BASE_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_1_BASE_1_MASK, .index = FLASH_CTRL_MP_REGION_1_BASE_1_OFFSET })
#define FLASH_CTRL_MP_REGION_1_SIZE_1_MASK 0x3fu
#define FLASH_CTRL_MP_REGION_1_SIZE_1_OFFSET 5
#define FLASH_CTRL_MP_REGION_1_SIZE_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_1_SIZE_1_MASK, .index = FLASH_CTRL_MP_REGION_1_SIZE_1_OFFSET })
 
// Memory base and size configuration for data partition
#define FLASH_CTRL_MP_REGION_2_REG_OFFSET 0x78
#define FLASH_CTRL_MP_REGION_2_REG_RESVAL 0x0u
#define FLASH_CTRL_MP_REGION_2_BASE_2_MASK 0x1fu
#define FLASH_CTRL_MP_REGION_2_BASE_2_OFFSET 0
#define FLASH_CTRL_MP_REGION_2_BASE_2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_2_BASE_2_MASK, .index = FLASH_CTRL_MP_REGION_2_BASE_2_OFFSET })
#define FLASH_CTRL_MP_REGION_2_SIZE_2_MASK 0x3fu
#define FLASH_CTRL_MP_REGION_2_SIZE_2_OFFSET 5
#define FLASH_CTRL_MP_REGION_2_SIZE_2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_2_SIZE_2_MASK, .index = FLASH_CTRL_MP_REGION_2_SIZE_2_OFFSET })
 
// Memory base and size configuration for data partition
#define FLASH_CTRL_MP_REGION_3_REG_OFFSET 0x7c
#define FLASH_CTRL_MP_REGION_3_REG_RESVAL 0x0u
#define FLASH_CTRL_MP_REGION_3_BASE_3_MASK 0x1fu
#define FLASH_CTRL_MP_REGION_3_BASE_3_OFFSET 0
#define FLASH_CTRL_MP_REGION_3_BASE_3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_3_BASE_3_MASK, .index = FLASH_CTRL_MP_REGION_3_BASE_3_OFFSET })
#define FLASH_CTRL_MP_REGION_3_SIZE_3_MASK 0x3fu
#define FLASH_CTRL_MP_REGION_3_SIZE_3_OFFSET 5
#define FLASH_CTRL_MP_REGION_3_SIZE_3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_3_SIZE_3_MASK, .index = FLASH_CTRL_MP_REGION_3_SIZE_3_OFFSET })
 
// Memory base and size configuration for data partition
#define FLASH_CTRL_MP_REGION_4_REG_OFFSET 0x80
#define FLASH_CTRL_MP_REGION_4_REG_RESVAL 0x0u
#define FLASH_CTRL_MP_REGION_4_BASE_4_MASK 0x1fu
#define FLASH_CTRL_MP_REGION_4_BASE_4_OFFSET 0
#define FLASH_CTRL_MP_REGION_4_BASE_4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_4_BASE_4_MASK, .index = FLASH_CTRL_MP_REGION_4_BASE_4_OFFSET })
#define FLASH_CTRL_MP_REGION_4_SIZE_4_MASK 0x3fu
#define FLASH_CTRL_MP_REGION_4_SIZE_4_OFFSET 5
#define FLASH_CTRL_MP_REGION_4_SIZE_4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_4_SIZE_4_MASK, .index = FLASH_CTRL_MP_REGION_4_SIZE_4_OFFSET })
 
// Memory base and size configuration for data partition
#define FLASH_CTRL_MP_REGION_5_REG_OFFSET 0x84
#define FLASH_CTRL_MP_REGION_5_REG_RESVAL 0x0u
#define FLASH_CTRL_MP_REGION_5_BASE_5_MASK 0x1fu
#define FLASH_CTRL_MP_REGION_5_BASE_5_OFFSET 0
#define FLASH_CTRL_MP_REGION_5_BASE_5_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_5_BASE_5_MASK, .index = FLASH_CTRL_MP_REGION_5_BASE_5_OFFSET })
#define FLASH_CTRL_MP_REGION_5_SIZE_5_MASK 0x3fu
#define FLASH_CTRL_MP_REGION_5_SIZE_5_OFFSET 5
#define FLASH_CTRL_MP_REGION_5_SIZE_5_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_5_SIZE_5_MASK, .index = FLASH_CTRL_MP_REGION_5_SIZE_5_OFFSET })
 
// Memory base and size configuration for data partition
#define FLASH_CTRL_MP_REGION_6_REG_OFFSET 0x88
#define FLASH_CTRL_MP_REGION_6_REG_RESVAL 0x0u
#define FLASH_CTRL_MP_REGION_6_BASE_6_MASK 0x1fu
#define FLASH_CTRL_MP_REGION_6_BASE_6_OFFSET 0
#define FLASH_CTRL_MP_REGION_6_BASE_6_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_6_BASE_6_MASK, .index = FLASH_CTRL_MP_REGION_6_BASE_6_OFFSET })
#define FLASH_CTRL_MP_REGION_6_SIZE_6_MASK 0x3fu
#define FLASH_CTRL_MP_REGION_6_SIZE_6_OFFSET 5
#define FLASH_CTRL_MP_REGION_6_SIZE_6_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_6_SIZE_6_MASK, .index = FLASH_CTRL_MP_REGION_6_SIZE_6_OFFSET })
 
// Memory base and size configuration for data partition
#define FLASH_CTRL_MP_REGION_7_REG_OFFSET 0x8c
#define FLASH_CTRL_MP_REGION_7_REG_RESVAL 0x0u
#define FLASH_CTRL_MP_REGION_7_BASE_7_MASK 0x1fu
#define FLASH_CTRL_MP_REGION_7_BASE_7_OFFSET 0
#define FLASH_CTRL_MP_REGION_7_BASE_7_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_7_BASE_7_MASK, .index = FLASH_CTRL_MP_REGION_7_BASE_7_OFFSET })
#define FLASH_CTRL_MP_REGION_7_SIZE_7_MASK 0x3fu
#define FLASH_CTRL_MP_REGION_7_SIZE_7_OFFSET 5
#define FLASH_CTRL_MP_REGION_7_SIZE_7_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_MP_REGION_7_SIZE_7_MASK, .index = FLASH_CTRL_MP_REGION_7_SIZE_7_OFFSET })
 
// Default region properties
#define FLASH_CTRL_DEFAULT_REGION_REG_OFFSET 0x90
#define FLASH_CTRL_DEFAULT_REGION_REG_RESVAL 0x999999u
#define FLASH_CTRL_DEFAULT_REGION_RD_EN_MASK 0xfu
#define FLASH_CTRL_DEFAULT_REGION_RD_EN_OFFSET 0
#define FLASH_CTRL_DEFAULT_REGION_RD_EN_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_DEFAULT_REGION_RD_EN_MASK, .index = FLASH_CTRL_DEFAULT_REGION_RD_EN_OFFSET })
#define FLASH_CTRL_DEFAULT_REGION_PROG_EN_MASK 0xfu
#define FLASH_CTRL_DEFAULT_REGION_PROG_EN_OFFSET 4
#define FLASH_CTRL_DEFAULT_REGION_PROG_EN_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_DEFAULT_REGION_PROG_EN_MASK, .index = FLASH_CTRL_DEFAULT_REGION_PROG_EN_OFFSET })
#define FLASH_CTRL_DEFAULT_REGION_ERASE_EN_MASK 0xfu
#define FLASH_CTRL_DEFAULT_REGION_ERASE_EN_OFFSET 8
#define FLASH_CTRL_DEFAULT_REGION_ERASE_EN_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_DEFAULT_REGION_ERASE_EN_MASK, .index = FLASH_CTRL_DEFAULT_REGION_ERASE_EN_OFFSET })
#define FLASH_CTRL_DEFAULT_REGION_SCRAMBLE_EN_MASK 0xfu
#define FLASH_CTRL_DEFAULT_REGION_SCRAMBLE_EN_OFFSET 12
#define FLASH_CTRL_DEFAULT_REGION_SCRAMBLE_EN_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_DEFAULT_REGION_SCRAMBLE_EN_MASK, .index = FLASH_CTRL_DEFAULT_REGION_SCRAMBLE_EN_OFFSET })
#define FLASH_CTRL_DEFAULT_REGION_ECC_EN_MASK 0xfu
#define FLASH_CTRL_DEFAULT_REGION_ECC_EN_OFFSET 16
#define FLASH_CTRL_DEFAULT_REGION_ECC_EN_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_DEFAULT_REGION_ECC_EN_MASK, .index = FLASH_CTRL_DEFAULT_REGION_ECC_EN_OFFSET })
#define FLASH_CTRL_DEFAULT_REGION_HE_EN_MASK 0xfu
#define FLASH_CTRL_DEFAULT_REGION_HE_EN_OFFSET 20
#define FLASH_CTRL_DEFAULT_REGION_HE_EN_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_DEFAULT_REGION_HE_EN_MASK, .index = FLASH_CTRL_DEFAULT_REGION_HE_EN_OFFSET })
 
// Memory region registers configuration enable. (common parameters)
#define FLASH_CTRL_BANK0_INFO0_REGWEN_REGION_FIELD_WIDTH 1
#define FLASH_CTRL_BANK0_INFO0_REGWEN_MULTIREG_COUNT 10
 
// Memory region registers configuration enable.
#define FLASH_CTRL_BANK0_INFO0_REGWEN_0_REG_OFFSET 0x94
#define FLASH_CTRL_BANK0_INFO0_REGWEN_0_REG_RESVAL 0x1u
#define FLASH_CTRL_BANK0_INFO0_REGWEN_0_REGION_0_BIT 0
#define FLASH_CTRL_BANK0_INFO0_REGWEN_0_REGION_0_VALUE_PAGE_LOCKED 0x0
#define FLASH_CTRL_BANK0_INFO0_REGWEN_0_REGION_0_VALUE_PAGE_ENABLED 0x1
 
// Memory region registers configuration enable.
#define FLASH_CTRL_BANK0_INFO0_REGWEN_1_REG_OFFSET 0x98
#define FLASH_CTRL_BANK0_INFO0_REGWEN_1_REG_RESVAL 0x1u
#define FLASH_CTRL_BANK0_INFO0_REGWEN_1_REGION_1_BIT 0
 
// Memory region registers configuration enable.
#define FLASH_CTRL_BANK0_INFO0_REGWEN_2_REG_OFFSET 0x9c
#define FLASH_CTRL_BANK0_INFO0_REGWEN_2_REG_RESVAL 0x1u
#define FLASH_CTRL_BANK0_INFO0_REGWEN_2_REGION_2_BIT 0
 
// Memory region registers configuration enable.
#define FLASH_CTRL_BANK0_INFO0_REGWEN_3_REG_OFFSET 0xa0
#define FLASH_CTRL_BANK0_INFO0_REGWEN_3_REG_RESVAL 0x1u
#define FLASH_CTRL_BANK0_INFO0_REGWEN_3_REGION_3_BIT 0
 
// Memory region registers configuration enable.
#define FLASH_CTRL_BANK0_INFO0_REGWEN_4_REG_OFFSET 0xa4
#define FLASH_CTRL_BANK0_INFO0_REGWEN_4_REG_RESVAL 0x1u
#define FLASH_CTRL_BANK0_INFO0_REGWEN_4_REGION_4_BIT 0
 
// Memory region registers configuration enable.
#define FLASH_CTRL_BANK0_INFO0_REGWEN_5_REG_OFFSET 0xa8
#define FLASH_CTRL_BANK0_INFO0_REGWEN_5_REG_RESVAL 0x1u
#define FLASH_CTRL_BANK0_INFO0_REGWEN_5_REGION_5_BIT 0
 
// Memory region registers configuration enable.
#define FLASH_CTRL_BANK0_INFO0_REGWEN_6_REG_OFFSET 0xac
#define FLASH_CTRL_BANK0_INFO0_REGWEN_6_REG_RESVAL 0x1u
#define FLASH_CTRL_BANK0_INFO0_REGWEN_6_REGION_6_BIT 0
 
// Memory region registers configuration enable.
#define FLASH_CTRL_BANK0_INFO0_REGWEN_7_REG_OFFSET 0xb0
#define FLASH_CTRL_BANK0_INFO0_REGWEN_7_REG_RESVAL 0x1u
#define FLASH_CTRL_BANK0_INFO0_REGWEN_7_REGION_7_BIT 0
 
// Memory region registers configuration enable.
#define FLASH_CTRL_BANK0_INFO0_REGWEN_8_REG_OFFSET 0xb4
#define FLASH_CTRL_BANK0_INFO0_REGWEN_8_REG_RESVAL 0x1u
#define FLASH_CTRL_BANK0_INFO0_REGWEN_8_REGION_8_BIT 0
 
// Memory region registers configuration enable.
#define FLASH_CTRL_BANK0_INFO0_REGWEN_9_REG_OFFSET 0xb8
#define FLASH_CTRL_BANK0_INFO0_REGWEN_9_REG_RESVAL 0x1u
#define FLASH_CTRL_BANK0_INFO0_REGWEN_9_REGION_9_BIT 0
 
//   Memory property configuration for info partition in bank0,
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_RD_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_PROG_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_ERASE_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_SCRAMBLE_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_ECC_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_HE_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_MULTIREG_COUNT 10
 
//   Memory property configuration for info partition in bank0,
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_REG_OFFSET 0xbc
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_REG_RESVAL 0x9999999u
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_EN_0_OFFSET 0
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_EN_0_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_EN_0_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_RD_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_RD_EN_0_OFFSET 4
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_RD_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_RD_EN_0_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_RD_EN_0_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_PROG_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_PROG_EN_0_OFFSET 8
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_PROG_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_PROG_EN_0_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_PROG_EN_0_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_ERASE_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_ERASE_EN_0_OFFSET 12
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_ERASE_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_ERASE_EN_0_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_ERASE_EN_0_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_SCRAMBLE_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_SCRAMBLE_EN_0_OFFSET 16
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_SCRAMBLE_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_SCRAMBLE_EN_0_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_SCRAMBLE_EN_0_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_ECC_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_ECC_EN_0_OFFSET 20
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_ECC_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_ECC_EN_0_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_ECC_EN_0_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_HE_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_HE_EN_0_OFFSET 24
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_HE_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_HE_EN_0_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_0_HE_EN_0_OFFSET })
 
//   Memory property configuration for info partition in bank0,
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_REG_OFFSET 0xc0
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_REG_RESVAL 0x9999999u
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_EN_1_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_EN_1_OFFSET 0
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_EN_1_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_EN_1_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_RD_EN_1_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_RD_EN_1_OFFSET 4
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_RD_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_RD_EN_1_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_RD_EN_1_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_PROG_EN_1_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_PROG_EN_1_OFFSET 8
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_PROG_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_PROG_EN_1_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_PROG_EN_1_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_ERASE_EN_1_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_ERASE_EN_1_OFFSET 12
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_ERASE_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_ERASE_EN_1_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_ERASE_EN_1_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_SCRAMBLE_EN_1_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_SCRAMBLE_EN_1_OFFSET 16
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_SCRAMBLE_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_SCRAMBLE_EN_1_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_SCRAMBLE_EN_1_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_ECC_EN_1_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_ECC_EN_1_OFFSET 20
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_ECC_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_ECC_EN_1_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_ECC_EN_1_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_HE_EN_1_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_HE_EN_1_OFFSET 24
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_HE_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_HE_EN_1_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_1_HE_EN_1_OFFSET })
 
//   Memory property configuration for info partition in bank0,
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_REG_OFFSET 0xc4
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_REG_RESVAL 0x9999999u
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_EN_2_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_EN_2_OFFSET 0
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_EN_2_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_EN_2_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_RD_EN_2_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_RD_EN_2_OFFSET 4
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_RD_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_RD_EN_2_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_RD_EN_2_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_PROG_EN_2_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_PROG_EN_2_OFFSET 8
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_PROG_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_PROG_EN_2_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_PROG_EN_2_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_ERASE_EN_2_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_ERASE_EN_2_OFFSET 12
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_ERASE_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_ERASE_EN_2_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_ERASE_EN_2_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_SCRAMBLE_EN_2_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_SCRAMBLE_EN_2_OFFSET 16
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_SCRAMBLE_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_SCRAMBLE_EN_2_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_SCRAMBLE_EN_2_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_ECC_EN_2_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_ECC_EN_2_OFFSET 20
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_ECC_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_ECC_EN_2_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_ECC_EN_2_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_HE_EN_2_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_HE_EN_2_OFFSET 24
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_HE_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_HE_EN_2_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_2_HE_EN_2_OFFSET })
 
//   Memory property configuration for info partition in bank0,
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_REG_OFFSET 0xc8
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_REG_RESVAL 0x9999999u
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_EN_3_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_EN_3_OFFSET 0
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_EN_3_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_EN_3_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_RD_EN_3_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_RD_EN_3_OFFSET 4
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_RD_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_RD_EN_3_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_RD_EN_3_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_PROG_EN_3_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_PROG_EN_3_OFFSET 8
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_PROG_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_PROG_EN_3_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_PROG_EN_3_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_ERASE_EN_3_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_ERASE_EN_3_OFFSET 12
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_ERASE_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_ERASE_EN_3_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_ERASE_EN_3_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_SCRAMBLE_EN_3_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_SCRAMBLE_EN_3_OFFSET 16
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_SCRAMBLE_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_SCRAMBLE_EN_3_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_SCRAMBLE_EN_3_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_ECC_EN_3_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_ECC_EN_3_OFFSET 20
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_ECC_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_ECC_EN_3_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_ECC_EN_3_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_HE_EN_3_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_HE_EN_3_OFFSET 24
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_HE_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_HE_EN_3_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_3_HE_EN_3_OFFSET })
 
//   Memory property configuration for info partition in bank0,
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_REG_OFFSET 0xcc
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_REG_RESVAL 0x9999999u
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_EN_4_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_EN_4_OFFSET 0
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_EN_4_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_EN_4_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_RD_EN_4_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_RD_EN_4_OFFSET 4
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_RD_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_RD_EN_4_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_RD_EN_4_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_PROG_EN_4_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_PROG_EN_4_OFFSET 8
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_PROG_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_PROG_EN_4_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_PROG_EN_4_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_ERASE_EN_4_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_ERASE_EN_4_OFFSET 12
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_ERASE_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_ERASE_EN_4_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_ERASE_EN_4_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_SCRAMBLE_EN_4_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_SCRAMBLE_EN_4_OFFSET 16
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_SCRAMBLE_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_SCRAMBLE_EN_4_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_SCRAMBLE_EN_4_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_ECC_EN_4_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_ECC_EN_4_OFFSET 20
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_ECC_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_ECC_EN_4_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_ECC_EN_4_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_HE_EN_4_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_HE_EN_4_OFFSET 24
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_HE_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_HE_EN_4_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_4_HE_EN_4_OFFSET })
 
//   Memory property configuration for info partition in bank0,
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_REG_OFFSET 0xd0
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_REG_RESVAL 0x9999999u
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_EN_5_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_EN_5_OFFSET 0
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_EN_5_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_EN_5_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_RD_EN_5_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_RD_EN_5_OFFSET 4
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_RD_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_RD_EN_5_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_RD_EN_5_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_PROG_EN_5_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_PROG_EN_5_OFFSET 8
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_PROG_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_PROG_EN_5_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_PROG_EN_5_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_ERASE_EN_5_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_ERASE_EN_5_OFFSET 12
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_ERASE_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_ERASE_EN_5_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_ERASE_EN_5_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_SCRAMBLE_EN_5_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_SCRAMBLE_EN_5_OFFSET 16
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_SCRAMBLE_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_SCRAMBLE_EN_5_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_SCRAMBLE_EN_5_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_ECC_EN_5_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_ECC_EN_5_OFFSET 20
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_ECC_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_ECC_EN_5_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_ECC_EN_5_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_HE_EN_5_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_HE_EN_5_OFFSET 24
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_HE_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_HE_EN_5_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_5_HE_EN_5_OFFSET })
 
//   Memory property configuration for info partition in bank0,
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_REG_OFFSET 0xd4
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_REG_RESVAL 0x9999999u
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_EN_6_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_EN_6_OFFSET 0
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_EN_6_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_EN_6_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_RD_EN_6_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_RD_EN_6_OFFSET 4
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_RD_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_RD_EN_6_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_RD_EN_6_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_PROG_EN_6_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_PROG_EN_6_OFFSET 8
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_PROG_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_PROG_EN_6_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_PROG_EN_6_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_ERASE_EN_6_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_ERASE_EN_6_OFFSET 12
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_ERASE_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_ERASE_EN_6_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_ERASE_EN_6_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_SCRAMBLE_EN_6_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_SCRAMBLE_EN_6_OFFSET 16
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_SCRAMBLE_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_SCRAMBLE_EN_6_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_SCRAMBLE_EN_6_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_ECC_EN_6_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_ECC_EN_6_OFFSET 20
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_ECC_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_ECC_EN_6_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_ECC_EN_6_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_HE_EN_6_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_HE_EN_6_OFFSET 24
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_HE_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_HE_EN_6_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_6_HE_EN_6_OFFSET })
 
//   Memory property configuration for info partition in bank0,
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_REG_OFFSET 0xd8
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_REG_RESVAL 0x9999999u
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_EN_7_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_EN_7_OFFSET 0
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_EN_7_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_EN_7_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_RD_EN_7_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_RD_EN_7_OFFSET 4
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_RD_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_RD_EN_7_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_RD_EN_7_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_PROG_EN_7_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_PROG_EN_7_OFFSET 8
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_PROG_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_PROG_EN_7_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_PROG_EN_7_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_ERASE_EN_7_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_ERASE_EN_7_OFFSET 12
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_ERASE_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_ERASE_EN_7_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_ERASE_EN_7_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_SCRAMBLE_EN_7_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_SCRAMBLE_EN_7_OFFSET 16
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_SCRAMBLE_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_SCRAMBLE_EN_7_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_SCRAMBLE_EN_7_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_ECC_EN_7_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_ECC_EN_7_OFFSET 20
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_ECC_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_ECC_EN_7_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_ECC_EN_7_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_HE_EN_7_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_HE_EN_7_OFFSET 24
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_HE_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_HE_EN_7_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_7_HE_EN_7_OFFSET })
 
//   Memory property configuration for info partition in bank0,
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_REG_OFFSET 0xdc
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_REG_RESVAL 0x9999999u
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_EN_8_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_EN_8_OFFSET 0
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_EN_8_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_EN_8_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_EN_8_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_RD_EN_8_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_RD_EN_8_OFFSET 4
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_RD_EN_8_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_RD_EN_8_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_RD_EN_8_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_PROG_EN_8_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_PROG_EN_8_OFFSET 8
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_PROG_EN_8_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_PROG_EN_8_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_PROG_EN_8_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_ERASE_EN_8_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_ERASE_EN_8_OFFSET 12
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_ERASE_EN_8_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_ERASE_EN_8_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_ERASE_EN_8_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_SCRAMBLE_EN_8_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_SCRAMBLE_EN_8_OFFSET 16
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_SCRAMBLE_EN_8_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_SCRAMBLE_EN_8_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_SCRAMBLE_EN_8_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_ECC_EN_8_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_ECC_EN_8_OFFSET 20
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_ECC_EN_8_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_ECC_EN_8_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_ECC_EN_8_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_HE_EN_8_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_HE_EN_8_OFFSET 24
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_HE_EN_8_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_HE_EN_8_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_8_HE_EN_8_OFFSET })
 
//   Memory property configuration for info partition in bank0,
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_REG_OFFSET 0xe0
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_REG_RESVAL 0x9999999u
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_EN_9_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_EN_9_OFFSET 0
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_EN_9_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_EN_9_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_EN_9_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_RD_EN_9_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_RD_EN_9_OFFSET 4
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_RD_EN_9_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_RD_EN_9_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_RD_EN_9_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_PROG_EN_9_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_PROG_EN_9_OFFSET 8
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_PROG_EN_9_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_PROG_EN_9_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_PROG_EN_9_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_ERASE_EN_9_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_ERASE_EN_9_OFFSET 12
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_ERASE_EN_9_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_ERASE_EN_9_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_ERASE_EN_9_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_SCRAMBLE_EN_9_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_SCRAMBLE_EN_9_OFFSET 16
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_SCRAMBLE_EN_9_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_SCRAMBLE_EN_9_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_SCRAMBLE_EN_9_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_ECC_EN_9_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_ECC_EN_9_OFFSET 20
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_ECC_EN_9_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_ECC_EN_9_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_ECC_EN_9_OFFSET })
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_HE_EN_9_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_HE_EN_9_OFFSET 24
#define FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_HE_EN_9_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_HE_EN_9_MASK, .index = FLASH_CTRL_BANK0_INFO0_PAGE_CFG_9_HE_EN_9_OFFSET })
 
// Memory region registers configuration enable. (common parameters)
#define FLASH_CTRL_BANK0_INFO1_REGWEN_REGION_FIELD_WIDTH 1
#define FLASH_CTRL_BANK0_INFO1_REGWEN_MULTIREG_COUNT 1
 
// Memory region registers configuration enable.
#define FLASH_CTRL_BANK0_INFO1_REGWEN_REG_OFFSET 0xe4
#define FLASH_CTRL_BANK0_INFO1_REGWEN_REG_RESVAL 0x1u
#define FLASH_CTRL_BANK0_INFO1_REGWEN_REGION_0_BIT 0
#define FLASH_CTRL_BANK0_INFO1_REGWEN_REGION_0_VALUE_PAGE_LOCKED 0x0
#define FLASH_CTRL_BANK0_INFO1_REGWEN_REGION_0_VALUE_PAGE_ENABLED 0x1
 
//   Memory property configuration for info partition in bank0,
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_RD_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_PROG_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_ERASE_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SCRAMBLE_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_ECC_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_HE_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_MULTIREG_COUNT 1
 
//   Memory property configuration for info partition in bank0,
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_REG_OFFSET 0xe8
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_REG_RESVAL 0x9999999u
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_EN_0_OFFSET 0
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO1_PAGE_CFG_EN_0_MASK, .index = FLASH_CTRL_BANK0_INFO1_PAGE_CFG_EN_0_OFFSET })
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_RD_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_RD_EN_0_OFFSET 4
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_RD_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO1_PAGE_CFG_RD_EN_0_MASK, .index = FLASH_CTRL_BANK0_INFO1_PAGE_CFG_RD_EN_0_OFFSET })
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_PROG_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_PROG_EN_0_OFFSET 8
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_PROG_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO1_PAGE_CFG_PROG_EN_0_MASK, .index = FLASH_CTRL_BANK0_INFO1_PAGE_CFG_PROG_EN_0_OFFSET })
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_ERASE_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_ERASE_EN_0_OFFSET 12
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_ERASE_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO1_PAGE_CFG_ERASE_EN_0_MASK, .index = FLASH_CTRL_BANK0_INFO1_PAGE_CFG_ERASE_EN_0_OFFSET })
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SCRAMBLE_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SCRAMBLE_EN_0_OFFSET 16
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SCRAMBLE_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SCRAMBLE_EN_0_MASK, .index = FLASH_CTRL_BANK0_INFO1_PAGE_CFG_SCRAMBLE_EN_0_OFFSET })
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_ECC_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_ECC_EN_0_OFFSET 20
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_ECC_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO1_PAGE_CFG_ECC_EN_0_MASK, .index = FLASH_CTRL_BANK0_INFO1_PAGE_CFG_ECC_EN_0_OFFSET })
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_HE_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_HE_EN_0_OFFSET 24
#define FLASH_CTRL_BANK0_INFO1_PAGE_CFG_HE_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO1_PAGE_CFG_HE_EN_0_MASK, .index = FLASH_CTRL_BANK0_INFO1_PAGE_CFG_HE_EN_0_OFFSET })
 
// Memory region registers configuration enable. (common parameters)
#define FLASH_CTRL_BANK0_INFO2_REGWEN_REGION_FIELD_WIDTH 1
#define FLASH_CTRL_BANK0_INFO2_REGWEN_MULTIREG_COUNT 2
 
// Memory region registers configuration enable.
#define FLASH_CTRL_BANK0_INFO2_REGWEN_0_REG_OFFSET 0xec
#define FLASH_CTRL_BANK0_INFO2_REGWEN_0_REG_RESVAL 0x1u
#define FLASH_CTRL_BANK0_INFO2_REGWEN_0_REGION_0_BIT 0
#define FLASH_CTRL_BANK0_INFO2_REGWEN_0_REGION_0_VALUE_PAGE_LOCKED 0x0
#define FLASH_CTRL_BANK0_INFO2_REGWEN_0_REGION_0_VALUE_PAGE_ENABLED 0x1
 
// Memory region registers configuration enable.
#define FLASH_CTRL_BANK0_INFO2_REGWEN_1_REG_OFFSET 0xf0
#define FLASH_CTRL_BANK0_INFO2_REGWEN_1_REG_RESVAL 0x1u
#define FLASH_CTRL_BANK0_INFO2_REGWEN_1_REGION_1_BIT 0
 
//   Memory property configuration for info partition in bank0,
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_RD_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_PROG_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_ERASE_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_SCRAMBLE_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_ECC_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_HE_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_MULTIREG_COUNT 2
 
//   Memory property configuration for info partition in bank0,
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_REG_OFFSET 0xf4
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_REG_RESVAL 0x9999999u
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_EN_0_OFFSET 0
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_EN_0_MASK, .index = FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_EN_0_OFFSET })
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_RD_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_RD_EN_0_OFFSET 4
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_RD_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_RD_EN_0_MASK, .index = FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_RD_EN_0_OFFSET })
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_PROG_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_PROG_EN_0_OFFSET 8
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_PROG_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_PROG_EN_0_MASK, .index = FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_PROG_EN_0_OFFSET })
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_ERASE_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_ERASE_EN_0_OFFSET 12
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_ERASE_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_ERASE_EN_0_MASK, .index = FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_ERASE_EN_0_OFFSET })
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_SCRAMBLE_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_SCRAMBLE_EN_0_OFFSET 16
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_SCRAMBLE_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_SCRAMBLE_EN_0_MASK, .index = FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_SCRAMBLE_EN_0_OFFSET })
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_ECC_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_ECC_EN_0_OFFSET 20
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_ECC_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_ECC_EN_0_MASK, .index = FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_ECC_EN_0_OFFSET })
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_HE_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_HE_EN_0_OFFSET 24
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_HE_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_HE_EN_0_MASK, .index = FLASH_CTRL_BANK0_INFO2_PAGE_CFG_0_HE_EN_0_OFFSET })
 
//   Memory property configuration for info partition in bank0,
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_REG_OFFSET 0xf8
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_REG_RESVAL 0x9999999u
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_EN_1_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_EN_1_OFFSET 0
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_EN_1_MASK, .index = FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_EN_1_OFFSET })
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_RD_EN_1_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_RD_EN_1_OFFSET 4
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_RD_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_RD_EN_1_MASK, .index = FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_RD_EN_1_OFFSET })
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_PROG_EN_1_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_PROG_EN_1_OFFSET 8
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_PROG_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_PROG_EN_1_MASK, .index = FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_PROG_EN_1_OFFSET })
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_ERASE_EN_1_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_ERASE_EN_1_OFFSET 12
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_ERASE_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_ERASE_EN_1_MASK, .index = FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_ERASE_EN_1_OFFSET })
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_SCRAMBLE_EN_1_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_SCRAMBLE_EN_1_OFFSET 16
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_SCRAMBLE_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_SCRAMBLE_EN_1_MASK, .index = FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_SCRAMBLE_EN_1_OFFSET })
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_ECC_EN_1_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_ECC_EN_1_OFFSET 20
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_ECC_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_ECC_EN_1_MASK, .index = FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_ECC_EN_1_OFFSET })
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_HE_EN_1_MASK 0xfu
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_HE_EN_1_OFFSET 24
#define FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_HE_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_HE_EN_1_MASK, .index = FLASH_CTRL_BANK0_INFO2_PAGE_CFG_1_HE_EN_1_OFFSET })
 
// Memory region registers configuration enable. (common parameters)
#define FLASH_CTRL_BANK1_INFO0_REGWEN_REGION_FIELD_WIDTH 1
#define FLASH_CTRL_BANK1_INFO0_REGWEN_MULTIREG_COUNT 10
 
// Memory region registers configuration enable.
#define FLASH_CTRL_BANK1_INFO0_REGWEN_0_REG_OFFSET 0xfc
#define FLASH_CTRL_BANK1_INFO0_REGWEN_0_REG_RESVAL 0x1u
#define FLASH_CTRL_BANK1_INFO0_REGWEN_0_REGION_0_BIT 0
#define FLASH_CTRL_BANK1_INFO0_REGWEN_0_REGION_0_VALUE_PAGE_LOCKED 0x0
#define FLASH_CTRL_BANK1_INFO0_REGWEN_0_REGION_0_VALUE_PAGE_ENABLED 0x1
 
// Memory region registers configuration enable.
#define FLASH_CTRL_BANK1_INFO0_REGWEN_1_REG_OFFSET 0x100
#define FLASH_CTRL_BANK1_INFO0_REGWEN_1_REG_RESVAL 0x1u
#define FLASH_CTRL_BANK1_INFO0_REGWEN_1_REGION_1_BIT 0
 
// Memory region registers configuration enable.
#define FLASH_CTRL_BANK1_INFO0_REGWEN_2_REG_OFFSET 0x104
#define FLASH_CTRL_BANK1_INFO0_REGWEN_2_REG_RESVAL 0x1u
#define FLASH_CTRL_BANK1_INFO0_REGWEN_2_REGION_2_BIT 0
 
// Memory region registers configuration enable.
#define FLASH_CTRL_BANK1_INFO0_REGWEN_3_REG_OFFSET 0x108
#define FLASH_CTRL_BANK1_INFO0_REGWEN_3_REG_RESVAL 0x1u
#define FLASH_CTRL_BANK1_INFO0_REGWEN_3_REGION_3_BIT 0
 
// Memory region registers configuration enable.
#define FLASH_CTRL_BANK1_INFO0_REGWEN_4_REG_OFFSET 0x10c
#define FLASH_CTRL_BANK1_INFO0_REGWEN_4_REG_RESVAL 0x1u
#define FLASH_CTRL_BANK1_INFO0_REGWEN_4_REGION_4_BIT 0
 
// Memory region registers configuration enable.
#define FLASH_CTRL_BANK1_INFO0_REGWEN_5_REG_OFFSET 0x110
#define FLASH_CTRL_BANK1_INFO0_REGWEN_5_REG_RESVAL 0x1u
#define FLASH_CTRL_BANK1_INFO0_REGWEN_5_REGION_5_BIT 0
 
// Memory region registers configuration enable.
#define FLASH_CTRL_BANK1_INFO0_REGWEN_6_REG_OFFSET 0x114
#define FLASH_CTRL_BANK1_INFO0_REGWEN_6_REG_RESVAL 0x1u
#define FLASH_CTRL_BANK1_INFO0_REGWEN_6_REGION_6_BIT 0
 
// Memory region registers configuration enable.
#define FLASH_CTRL_BANK1_INFO0_REGWEN_7_REG_OFFSET 0x118
#define FLASH_CTRL_BANK1_INFO0_REGWEN_7_REG_RESVAL 0x1u
#define FLASH_CTRL_BANK1_INFO0_REGWEN_7_REGION_7_BIT 0
 
// Memory region registers configuration enable.
#define FLASH_CTRL_BANK1_INFO0_REGWEN_8_REG_OFFSET 0x11c
#define FLASH_CTRL_BANK1_INFO0_REGWEN_8_REG_RESVAL 0x1u
#define FLASH_CTRL_BANK1_INFO0_REGWEN_8_REGION_8_BIT 0
 
// Memory region registers configuration enable.
#define FLASH_CTRL_BANK1_INFO0_REGWEN_9_REG_OFFSET 0x120
#define FLASH_CTRL_BANK1_INFO0_REGWEN_9_REG_RESVAL 0x1u
#define FLASH_CTRL_BANK1_INFO0_REGWEN_9_REGION_9_BIT 0
 
//   Memory property configuration for info partition in bank1,
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_RD_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_PROG_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_ERASE_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_SCRAMBLE_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_ECC_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_HE_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_MULTIREG_COUNT 10
 
//   Memory property configuration for info partition in bank1,
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_REG_OFFSET 0x124
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_REG_RESVAL 0x9999999u
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_EN_0_OFFSET 0
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_EN_0_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_EN_0_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_RD_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_RD_EN_0_OFFSET 4
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_RD_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_RD_EN_0_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_RD_EN_0_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_PROG_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_PROG_EN_0_OFFSET 8
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_PROG_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_PROG_EN_0_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_PROG_EN_0_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_ERASE_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_ERASE_EN_0_OFFSET 12
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_ERASE_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_ERASE_EN_0_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_ERASE_EN_0_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_SCRAMBLE_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_SCRAMBLE_EN_0_OFFSET 16
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_SCRAMBLE_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_SCRAMBLE_EN_0_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_SCRAMBLE_EN_0_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_ECC_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_ECC_EN_0_OFFSET 20
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_ECC_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_ECC_EN_0_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_ECC_EN_0_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_HE_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_HE_EN_0_OFFSET 24
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_HE_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_HE_EN_0_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_0_HE_EN_0_OFFSET })
 
//   Memory property configuration for info partition in bank1,
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_REG_OFFSET 0x128
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_REG_RESVAL 0x9999999u
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_EN_1_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_EN_1_OFFSET 0
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_EN_1_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_EN_1_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_RD_EN_1_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_RD_EN_1_OFFSET 4
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_RD_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_RD_EN_1_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_RD_EN_1_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_PROG_EN_1_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_PROG_EN_1_OFFSET 8
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_PROG_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_PROG_EN_1_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_PROG_EN_1_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_ERASE_EN_1_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_ERASE_EN_1_OFFSET 12
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_ERASE_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_ERASE_EN_1_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_ERASE_EN_1_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_SCRAMBLE_EN_1_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_SCRAMBLE_EN_1_OFFSET 16
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_SCRAMBLE_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_SCRAMBLE_EN_1_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_SCRAMBLE_EN_1_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_ECC_EN_1_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_ECC_EN_1_OFFSET 20
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_ECC_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_ECC_EN_1_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_ECC_EN_1_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_HE_EN_1_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_HE_EN_1_OFFSET 24
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_HE_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_HE_EN_1_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_1_HE_EN_1_OFFSET })
 
//   Memory property configuration for info partition in bank1,
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_REG_OFFSET 0x12c
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_REG_RESVAL 0x9999999u
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_EN_2_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_EN_2_OFFSET 0
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_EN_2_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_EN_2_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_RD_EN_2_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_RD_EN_2_OFFSET 4
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_RD_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_RD_EN_2_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_RD_EN_2_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_PROG_EN_2_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_PROG_EN_2_OFFSET 8
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_PROG_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_PROG_EN_2_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_PROG_EN_2_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_ERASE_EN_2_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_ERASE_EN_2_OFFSET 12
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_ERASE_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_ERASE_EN_2_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_ERASE_EN_2_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_SCRAMBLE_EN_2_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_SCRAMBLE_EN_2_OFFSET 16
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_SCRAMBLE_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_SCRAMBLE_EN_2_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_SCRAMBLE_EN_2_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_ECC_EN_2_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_ECC_EN_2_OFFSET 20
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_ECC_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_ECC_EN_2_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_ECC_EN_2_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_HE_EN_2_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_HE_EN_2_OFFSET 24
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_HE_EN_2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_HE_EN_2_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_2_HE_EN_2_OFFSET })
 
//   Memory property configuration for info partition in bank1,
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_REG_OFFSET 0x130
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_REG_RESVAL 0x9999999u
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_EN_3_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_EN_3_OFFSET 0
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_EN_3_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_EN_3_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_RD_EN_3_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_RD_EN_3_OFFSET 4
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_RD_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_RD_EN_3_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_RD_EN_3_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_PROG_EN_3_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_PROG_EN_3_OFFSET 8
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_PROG_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_PROG_EN_3_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_PROG_EN_3_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_ERASE_EN_3_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_ERASE_EN_3_OFFSET 12
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_ERASE_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_ERASE_EN_3_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_ERASE_EN_3_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_SCRAMBLE_EN_3_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_SCRAMBLE_EN_3_OFFSET 16
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_SCRAMBLE_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_SCRAMBLE_EN_3_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_SCRAMBLE_EN_3_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_ECC_EN_3_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_ECC_EN_3_OFFSET 20
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_ECC_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_ECC_EN_3_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_ECC_EN_3_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_HE_EN_3_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_HE_EN_3_OFFSET 24
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_HE_EN_3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_HE_EN_3_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_3_HE_EN_3_OFFSET })
 
//   Memory property configuration for info partition in bank1,
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_REG_OFFSET 0x134
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_REG_RESVAL 0x9999999u
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_EN_4_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_EN_4_OFFSET 0
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_EN_4_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_EN_4_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_RD_EN_4_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_RD_EN_4_OFFSET 4
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_RD_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_RD_EN_4_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_RD_EN_4_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_PROG_EN_4_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_PROG_EN_4_OFFSET 8
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_PROG_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_PROG_EN_4_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_PROG_EN_4_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_ERASE_EN_4_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_ERASE_EN_4_OFFSET 12
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_ERASE_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_ERASE_EN_4_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_ERASE_EN_4_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_SCRAMBLE_EN_4_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_SCRAMBLE_EN_4_OFFSET 16
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_SCRAMBLE_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_SCRAMBLE_EN_4_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_SCRAMBLE_EN_4_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_ECC_EN_4_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_ECC_EN_4_OFFSET 20
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_ECC_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_ECC_EN_4_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_ECC_EN_4_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_HE_EN_4_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_HE_EN_4_OFFSET 24
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_HE_EN_4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_HE_EN_4_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_4_HE_EN_4_OFFSET })
 
//   Memory property configuration for info partition in bank1,
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_REG_OFFSET 0x138
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_REG_RESVAL 0x9999999u
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_EN_5_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_EN_5_OFFSET 0
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_EN_5_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_EN_5_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_RD_EN_5_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_RD_EN_5_OFFSET 4
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_RD_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_RD_EN_5_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_RD_EN_5_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_PROG_EN_5_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_PROG_EN_5_OFFSET 8
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_PROG_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_PROG_EN_5_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_PROG_EN_5_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_ERASE_EN_5_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_ERASE_EN_5_OFFSET 12
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_ERASE_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_ERASE_EN_5_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_ERASE_EN_5_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_SCRAMBLE_EN_5_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_SCRAMBLE_EN_5_OFFSET 16
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_SCRAMBLE_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_SCRAMBLE_EN_5_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_SCRAMBLE_EN_5_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_ECC_EN_5_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_ECC_EN_5_OFFSET 20
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_ECC_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_ECC_EN_5_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_ECC_EN_5_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_HE_EN_5_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_HE_EN_5_OFFSET 24
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_HE_EN_5_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_HE_EN_5_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_5_HE_EN_5_OFFSET })
 
//   Memory property configuration for info partition in bank1,
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_REG_OFFSET 0x13c
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_REG_RESVAL 0x9999999u
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_EN_6_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_EN_6_OFFSET 0
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_EN_6_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_EN_6_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_RD_EN_6_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_RD_EN_6_OFFSET 4
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_RD_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_RD_EN_6_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_RD_EN_6_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_PROG_EN_6_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_PROG_EN_6_OFFSET 8
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_PROG_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_PROG_EN_6_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_PROG_EN_6_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_ERASE_EN_6_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_ERASE_EN_6_OFFSET 12
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_ERASE_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_ERASE_EN_6_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_ERASE_EN_6_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_SCRAMBLE_EN_6_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_SCRAMBLE_EN_6_OFFSET 16
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_SCRAMBLE_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_SCRAMBLE_EN_6_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_SCRAMBLE_EN_6_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_ECC_EN_6_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_ECC_EN_6_OFFSET 20
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_ECC_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_ECC_EN_6_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_ECC_EN_6_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_HE_EN_6_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_HE_EN_6_OFFSET 24
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_HE_EN_6_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_HE_EN_6_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_6_HE_EN_6_OFFSET })
 
//   Memory property configuration for info partition in bank1,
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_REG_OFFSET 0x140
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_REG_RESVAL 0x9999999u
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_EN_7_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_EN_7_OFFSET 0
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_EN_7_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_EN_7_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_RD_EN_7_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_RD_EN_7_OFFSET 4
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_RD_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_RD_EN_7_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_RD_EN_7_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_PROG_EN_7_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_PROG_EN_7_OFFSET 8
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_PROG_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_PROG_EN_7_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_PROG_EN_7_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_ERASE_EN_7_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_ERASE_EN_7_OFFSET 12
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_ERASE_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_ERASE_EN_7_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_ERASE_EN_7_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_SCRAMBLE_EN_7_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_SCRAMBLE_EN_7_OFFSET 16
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_SCRAMBLE_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_SCRAMBLE_EN_7_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_SCRAMBLE_EN_7_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_ECC_EN_7_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_ECC_EN_7_OFFSET 20
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_ECC_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_ECC_EN_7_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_ECC_EN_7_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_HE_EN_7_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_HE_EN_7_OFFSET 24
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_HE_EN_7_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_HE_EN_7_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_7_HE_EN_7_OFFSET })
 
//   Memory property configuration for info partition in bank1,
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_REG_OFFSET 0x144
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_REG_RESVAL 0x9999999u
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_EN_8_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_EN_8_OFFSET 0
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_EN_8_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_EN_8_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_EN_8_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_RD_EN_8_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_RD_EN_8_OFFSET 4
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_RD_EN_8_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_RD_EN_8_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_RD_EN_8_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_PROG_EN_8_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_PROG_EN_8_OFFSET 8
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_PROG_EN_8_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_PROG_EN_8_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_PROG_EN_8_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_ERASE_EN_8_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_ERASE_EN_8_OFFSET 12
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_ERASE_EN_8_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_ERASE_EN_8_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_ERASE_EN_8_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_SCRAMBLE_EN_8_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_SCRAMBLE_EN_8_OFFSET 16
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_SCRAMBLE_EN_8_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_SCRAMBLE_EN_8_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_SCRAMBLE_EN_8_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_ECC_EN_8_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_ECC_EN_8_OFFSET 20
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_ECC_EN_8_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_ECC_EN_8_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_ECC_EN_8_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_HE_EN_8_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_HE_EN_8_OFFSET 24
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_HE_EN_8_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_HE_EN_8_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_8_HE_EN_8_OFFSET })
 
//   Memory property configuration for info partition in bank1,
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_REG_OFFSET 0x148
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_REG_RESVAL 0x9999999u
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_EN_9_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_EN_9_OFFSET 0
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_EN_9_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_EN_9_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_EN_9_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_RD_EN_9_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_RD_EN_9_OFFSET 4
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_RD_EN_9_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_RD_EN_9_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_RD_EN_9_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_PROG_EN_9_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_PROG_EN_9_OFFSET 8
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_PROG_EN_9_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_PROG_EN_9_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_PROG_EN_9_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_ERASE_EN_9_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_ERASE_EN_9_OFFSET 12
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_ERASE_EN_9_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_ERASE_EN_9_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_ERASE_EN_9_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_SCRAMBLE_EN_9_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_SCRAMBLE_EN_9_OFFSET 16
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_SCRAMBLE_EN_9_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_SCRAMBLE_EN_9_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_SCRAMBLE_EN_9_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_ECC_EN_9_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_ECC_EN_9_OFFSET 20
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_ECC_EN_9_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_ECC_EN_9_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_ECC_EN_9_OFFSET })
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_HE_EN_9_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_HE_EN_9_OFFSET 24
#define FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_HE_EN_9_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_HE_EN_9_MASK, .index = FLASH_CTRL_BANK1_INFO0_PAGE_CFG_9_HE_EN_9_OFFSET })
 
// Memory region registers configuration enable. (common parameters)
#define FLASH_CTRL_BANK1_INFO1_REGWEN_REGION_FIELD_WIDTH 1
#define FLASH_CTRL_BANK1_INFO1_REGWEN_MULTIREG_COUNT 1
 
// Memory region registers configuration enable.
#define FLASH_CTRL_BANK1_INFO1_REGWEN_REG_OFFSET 0x14c
#define FLASH_CTRL_BANK1_INFO1_REGWEN_REG_RESVAL 0x1u
#define FLASH_CTRL_BANK1_INFO1_REGWEN_REGION_0_BIT 0
#define FLASH_CTRL_BANK1_INFO1_REGWEN_REGION_0_VALUE_PAGE_LOCKED 0x0
#define FLASH_CTRL_BANK1_INFO1_REGWEN_REGION_0_VALUE_PAGE_ENABLED 0x1
 
//   Memory property configuration for info partition in bank1,
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_RD_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_PROG_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_ERASE_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SCRAMBLE_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_ECC_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_HE_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_MULTIREG_COUNT 1
 
//   Memory property configuration for info partition in bank1,
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_REG_OFFSET 0x150
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_REG_RESVAL 0x9999999u
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_EN_0_OFFSET 0
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO1_PAGE_CFG_EN_0_MASK, .index = FLASH_CTRL_BANK1_INFO1_PAGE_CFG_EN_0_OFFSET })
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_RD_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_RD_EN_0_OFFSET 4
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_RD_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO1_PAGE_CFG_RD_EN_0_MASK, .index = FLASH_CTRL_BANK1_INFO1_PAGE_CFG_RD_EN_0_OFFSET })
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_PROG_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_PROG_EN_0_OFFSET 8
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_PROG_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO1_PAGE_CFG_PROG_EN_0_MASK, .index = FLASH_CTRL_BANK1_INFO1_PAGE_CFG_PROG_EN_0_OFFSET })
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_ERASE_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_ERASE_EN_0_OFFSET 12
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_ERASE_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO1_PAGE_CFG_ERASE_EN_0_MASK, .index = FLASH_CTRL_BANK1_INFO1_PAGE_CFG_ERASE_EN_0_OFFSET })
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SCRAMBLE_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SCRAMBLE_EN_0_OFFSET 16
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SCRAMBLE_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SCRAMBLE_EN_0_MASK, .index = FLASH_CTRL_BANK1_INFO1_PAGE_CFG_SCRAMBLE_EN_0_OFFSET })
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_ECC_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_ECC_EN_0_OFFSET 20
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_ECC_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO1_PAGE_CFG_ECC_EN_0_MASK, .index = FLASH_CTRL_BANK1_INFO1_PAGE_CFG_ECC_EN_0_OFFSET })
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_HE_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_HE_EN_0_OFFSET 24
#define FLASH_CTRL_BANK1_INFO1_PAGE_CFG_HE_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO1_PAGE_CFG_HE_EN_0_MASK, .index = FLASH_CTRL_BANK1_INFO1_PAGE_CFG_HE_EN_0_OFFSET })
 
// Memory region registers configuration enable. (common parameters)
#define FLASH_CTRL_BANK1_INFO2_REGWEN_REGION_FIELD_WIDTH 1
#define FLASH_CTRL_BANK1_INFO2_REGWEN_MULTIREG_COUNT 2
 
// Memory region registers configuration enable.
#define FLASH_CTRL_BANK1_INFO2_REGWEN_0_REG_OFFSET 0x154
#define FLASH_CTRL_BANK1_INFO2_REGWEN_0_REG_RESVAL 0x1u
#define FLASH_CTRL_BANK1_INFO2_REGWEN_0_REGION_0_BIT 0
#define FLASH_CTRL_BANK1_INFO2_REGWEN_0_REGION_0_VALUE_PAGE_LOCKED 0x0
#define FLASH_CTRL_BANK1_INFO2_REGWEN_0_REGION_0_VALUE_PAGE_ENABLED 0x1
 
// Memory region registers configuration enable.
#define FLASH_CTRL_BANK1_INFO2_REGWEN_1_REG_OFFSET 0x158
#define FLASH_CTRL_BANK1_INFO2_REGWEN_1_REG_RESVAL 0x1u
#define FLASH_CTRL_BANK1_INFO2_REGWEN_1_REGION_1_BIT 0
 
//   Memory property configuration for info partition in bank1,
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_RD_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_PROG_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_ERASE_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_SCRAMBLE_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_ECC_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_HE_EN_FIELD_WIDTH 4
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_MULTIREG_COUNT 2
 
//   Memory property configuration for info partition in bank1,
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_REG_OFFSET 0x15c
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_REG_RESVAL 0x9999999u
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_EN_0_OFFSET 0
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_EN_0_MASK, .index = FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_EN_0_OFFSET })
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_RD_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_RD_EN_0_OFFSET 4
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_RD_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_RD_EN_0_MASK, .index = FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_RD_EN_0_OFFSET })
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_PROG_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_PROG_EN_0_OFFSET 8
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_PROG_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_PROG_EN_0_MASK, .index = FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_PROG_EN_0_OFFSET })
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_ERASE_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_ERASE_EN_0_OFFSET 12
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_ERASE_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_ERASE_EN_0_MASK, .index = FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_ERASE_EN_0_OFFSET })
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_SCRAMBLE_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_SCRAMBLE_EN_0_OFFSET 16
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_SCRAMBLE_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_SCRAMBLE_EN_0_MASK, .index = FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_SCRAMBLE_EN_0_OFFSET })
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_ECC_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_ECC_EN_0_OFFSET 20
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_ECC_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_ECC_EN_0_MASK, .index = FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_ECC_EN_0_OFFSET })
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_HE_EN_0_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_HE_EN_0_OFFSET 24
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_HE_EN_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_HE_EN_0_MASK, .index = FLASH_CTRL_BANK1_INFO2_PAGE_CFG_0_HE_EN_0_OFFSET })
 
//   Memory property configuration for info partition in bank1,
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_REG_OFFSET 0x160
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_REG_RESVAL 0x9999999u
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_EN_1_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_EN_1_OFFSET 0
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_EN_1_MASK, .index = FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_EN_1_OFFSET })
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_RD_EN_1_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_RD_EN_1_OFFSET 4
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_RD_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_RD_EN_1_MASK, .index = FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_RD_EN_1_OFFSET })
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_PROG_EN_1_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_PROG_EN_1_OFFSET 8
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_PROG_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_PROG_EN_1_MASK, .index = FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_PROG_EN_1_OFFSET })
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_ERASE_EN_1_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_ERASE_EN_1_OFFSET 12
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_ERASE_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_ERASE_EN_1_MASK, .index = FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_ERASE_EN_1_OFFSET })
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_SCRAMBLE_EN_1_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_SCRAMBLE_EN_1_OFFSET 16
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_SCRAMBLE_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_SCRAMBLE_EN_1_MASK, .index = FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_SCRAMBLE_EN_1_OFFSET })
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_ECC_EN_1_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_ECC_EN_1_OFFSET 20
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_ECC_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_ECC_EN_1_MASK, .index = FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_ECC_EN_1_OFFSET })
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_HE_EN_1_MASK 0xfu
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_HE_EN_1_OFFSET 24
#define FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_HE_EN_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_HE_EN_1_MASK, .index = FLASH_CTRL_BANK1_INFO2_PAGE_CFG_1_HE_EN_1_OFFSET })
 
// HW interface info configuration rule overrides
#define FLASH_CTRL_HW_INFO_CFG_OVERRIDE_REG_OFFSET 0x164
#define FLASH_CTRL_HW_INFO_CFG_OVERRIDE_REG_RESVAL 0x99u
#define FLASH_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_MASK 0xfu
#define FLASH_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_OFFSET 0
#define FLASH_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_MASK, .index = FLASH_CTRL_HW_INFO_CFG_OVERRIDE_SCRAMBLE_DIS_OFFSET })
#define FLASH_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_MASK 0xfu
#define FLASH_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_OFFSET 4
#define FLASH_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_MASK, .index = FLASH_CTRL_HW_INFO_CFG_OVERRIDE_ECC_DIS_OFFSET })
 
// Bank configuration registers configuration enable.
#define FLASH_CTRL_BANK_CFG_REGWEN_REG_OFFSET 0x168
#define FLASH_CTRL_BANK_CFG_REGWEN_REG_RESVAL 0x1u
#define FLASH_CTRL_BANK_CFG_REGWEN_BANK_BIT 0
#define FLASH_CTRL_BANK_CFG_REGWEN_BANK_VALUE_BANK_LOCKED 0x0
#define FLASH_CTRL_BANK_CFG_REGWEN_BANK_VALUE_BANK_ENABLED 0x1
 
// Memory properties bank configuration (common parameters)
#define FLASH_CTRL_MP_BANK_CFG_SHADOWED_ERASE_EN_FIELD_WIDTH 1
#define FLASH_CTRL_MP_BANK_CFG_SHADOWED_MULTIREG_COUNT 1
 
// Memory properties bank configuration
#define FLASH_CTRL_MP_BANK_CFG_SHADOWED_REG_OFFSET 0x16c
#define FLASH_CTRL_MP_BANK_CFG_SHADOWED_REG_RESVAL 0x0u
#define FLASH_CTRL_MP_BANK_CFG_SHADOWED_ERASE_EN_0_BIT 0
#define FLASH_CTRL_MP_BANK_CFG_SHADOWED_ERASE_EN_1_BIT 1
 
// Flash Operation Status
#define FLASH_CTRL_OP_STATUS_REG_OFFSET 0x170
#define FLASH_CTRL_OP_STATUS_REG_RESVAL 0x0u
#define FLASH_CTRL_OP_STATUS_DONE_BIT 0
#define FLASH_CTRL_OP_STATUS_ERR_BIT 1
 
// Flash Controller Status
#define FLASH_CTRL_STATUS_REG_OFFSET 0x174
#define FLASH_CTRL_STATUS_REG_RESVAL 0xau
#define FLASH_CTRL_STATUS_RD_FULL_BIT 0
#define FLASH_CTRL_STATUS_RD_EMPTY_BIT 1
#define FLASH_CTRL_STATUS_PROG_FULL_BIT 2
#define FLASH_CTRL_STATUS_PROG_EMPTY_BIT 3
#define FLASH_CTRL_STATUS_INIT_WIP_BIT 4
#define FLASH_CTRL_STATUS_INITIALIZED_BIT 5
 
// Current flash fsm state
#define FLASH_CTRL_DEBUG_STATE_REG_OFFSET 0x178
#define FLASH_CTRL_DEBUG_STATE_REG_RESVAL 0x0u
#define FLASH_CTRL_DEBUG_STATE_LCMGR_STATE_MASK 0x7ffu
#define FLASH_CTRL_DEBUG_STATE_LCMGR_STATE_OFFSET 0
#define FLASH_CTRL_DEBUG_STATE_LCMGR_STATE_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_DEBUG_STATE_LCMGR_STATE_MASK, .index = FLASH_CTRL_DEBUG_STATE_LCMGR_STATE_OFFSET })
 
// Flash error code register.
#define FLASH_CTRL_ERR_CODE_REG_OFFSET 0x17c
#define FLASH_CTRL_ERR_CODE_REG_RESVAL 0x0u
#define FLASH_CTRL_ERR_CODE_OP_ERR_BIT 0
#define FLASH_CTRL_ERR_CODE_MP_ERR_BIT 1
#define FLASH_CTRL_ERR_CODE_RD_ERR_BIT 2
#define FLASH_CTRL_ERR_CODE_PROG_ERR_BIT 3
#define FLASH_CTRL_ERR_CODE_PROG_WIN_ERR_BIT 4
#define FLASH_CTRL_ERR_CODE_PROG_TYPE_ERR_BIT 5
#define FLASH_CTRL_ERR_CODE_UPDATE_ERR_BIT 6
#define FLASH_CTRL_ERR_CODE_MACRO_ERR_BIT 7
 
// This register tabulates standard fault status of the flash.
#define FLASH_CTRL_STD_FAULT_STATUS_REG_OFFSET 0x180
#define FLASH_CTRL_STD_FAULT_STATUS_REG_RESVAL 0x0u
#define FLASH_CTRL_STD_FAULT_STATUS_REG_INTG_ERR_BIT 0
#define FLASH_CTRL_STD_FAULT_STATUS_PROG_INTG_ERR_BIT 1
#define FLASH_CTRL_STD_FAULT_STATUS_LCMGR_ERR_BIT 2
#define FLASH_CTRL_STD_FAULT_STATUS_LCMGR_INTG_ERR_BIT 3
#define FLASH_CTRL_STD_FAULT_STATUS_ARB_FSM_ERR_BIT 4
#define FLASH_CTRL_STD_FAULT_STATUS_STORAGE_ERR_BIT 5
#define FLASH_CTRL_STD_FAULT_STATUS_PHY_FSM_ERR_BIT 6
#define FLASH_CTRL_STD_FAULT_STATUS_CTRL_CNT_ERR_BIT 7
#define FLASH_CTRL_STD_FAULT_STATUS_FIFO_ERR_BIT 8
 
// This register tabulates customized fault status of the flash.
#define FLASH_CTRL_FAULT_STATUS_REG_OFFSET 0x184
#define FLASH_CTRL_FAULT_STATUS_REG_RESVAL 0x0u
#define FLASH_CTRL_FAULT_STATUS_OP_ERR_BIT 0
#define FLASH_CTRL_FAULT_STATUS_MP_ERR_BIT 1
#define FLASH_CTRL_FAULT_STATUS_RD_ERR_BIT 2
#define FLASH_CTRL_FAULT_STATUS_PROG_ERR_BIT 3
#define FLASH_CTRL_FAULT_STATUS_PROG_WIN_ERR_BIT 4
#define FLASH_CTRL_FAULT_STATUS_PROG_TYPE_ERR_BIT 5
#define FLASH_CTRL_FAULT_STATUS_SEED_ERR_BIT 6
#define FLASH_CTRL_FAULT_STATUS_PHY_RELBL_ERR_BIT 7
#define FLASH_CTRL_FAULT_STATUS_PHY_STORAGE_ERR_BIT 8
#define FLASH_CTRL_FAULT_STATUS_SPURIOUS_ACK_BIT 9
#define FLASH_CTRL_FAULT_STATUS_ARB_ERR_BIT 10
#define FLASH_CTRL_FAULT_STATUS_HOST_GNT_ERR_BIT 11
 
// Synchronous error address
#define FLASH_CTRL_ERR_ADDR_REG_OFFSET 0x188
#define FLASH_CTRL_ERR_ADDR_REG_RESVAL 0x0u
#define FLASH_CTRL_ERR_ADDR_ERR_ADDR_MASK 0xffffu
#define FLASH_CTRL_ERR_ADDR_ERR_ADDR_OFFSET 0
#define FLASH_CTRL_ERR_ADDR_ERR_ADDR_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_ERR_ADDR_ERR_ADDR_MASK, .index = FLASH_CTRL_ERR_ADDR_ERR_ADDR_OFFSET })
 
// Count of single bit ECC errors (common parameters)
#define FLASH_CTRL_ECC_SINGLE_ERR_CNT_ECC_SINGLE_ERR_CNT_FIELD_WIDTH 8
#define FLASH_CTRL_ECC_SINGLE_ERR_CNT_MULTIREG_COUNT 1
 
// Count of single bit ECC errors
#define FLASH_CTRL_ECC_SINGLE_ERR_CNT_REG_OFFSET 0x18c
#define FLASH_CTRL_ECC_SINGLE_ERR_CNT_REG_RESVAL 0x0u
#define FLASH_CTRL_ECC_SINGLE_ERR_CNT_ECC_SINGLE_ERR_CNT_0_MASK 0xffu
#define FLASH_CTRL_ECC_SINGLE_ERR_CNT_ECC_SINGLE_ERR_CNT_0_OFFSET 0
#define FLASH_CTRL_ECC_SINGLE_ERR_CNT_ECC_SINGLE_ERR_CNT_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_ECC_SINGLE_ERR_CNT_ECC_SINGLE_ERR_CNT_0_MASK, .index = FLASH_CTRL_ECC_SINGLE_ERR_CNT_ECC_SINGLE_ERR_CNT_0_OFFSET })
#define FLASH_CTRL_ECC_SINGLE_ERR_CNT_ECC_SINGLE_ERR_CNT_1_MASK 0xffu
#define FLASH_CTRL_ECC_SINGLE_ERR_CNT_ECC_SINGLE_ERR_CNT_1_OFFSET 8
#define FLASH_CTRL_ECC_SINGLE_ERR_CNT_ECC_SINGLE_ERR_CNT_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_ECC_SINGLE_ERR_CNT_ECC_SINGLE_ERR_CNT_1_MASK, .index = FLASH_CTRL_ECC_SINGLE_ERR_CNT_ECC_SINGLE_ERR_CNT_1_OFFSET })
 
// Latest address of ECC single err (common parameters)
#define FLASH_CTRL_ECC_SINGLE_ERR_ADDR_ECC_SINGLE_ERR_ADDR_FIELD_WIDTH 16
#define FLASH_CTRL_ECC_SINGLE_ERR_ADDR_MULTIREG_COUNT 2
 
// Latest address of ECC single err
#define FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_REG_OFFSET 0x190
#define FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_REG_RESVAL 0x0u
#define FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_ECC_SINGLE_ERR_ADDR_0_MASK 0xffffu
#define FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_ECC_SINGLE_ERR_ADDR_0_OFFSET 0
#define FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_ECC_SINGLE_ERR_ADDR_0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_ECC_SINGLE_ERR_ADDR_0_MASK, .index = FLASH_CTRL_ECC_SINGLE_ERR_ADDR_0_ECC_SINGLE_ERR_ADDR_0_OFFSET })
 
// Latest address of ECC single err
#define FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_REG_OFFSET 0x194
#define FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_REG_RESVAL 0x0u
#define FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_ECC_SINGLE_ERR_ADDR_1_MASK 0xffffu
#define FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_ECC_SINGLE_ERR_ADDR_1_OFFSET 0
#define FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_ECC_SINGLE_ERR_ADDR_1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_ECC_SINGLE_ERR_ADDR_1_MASK, .index = FLASH_CTRL_ECC_SINGLE_ERR_ADDR_1_ECC_SINGLE_ERR_ADDR_1_OFFSET })
 
// Phy alert configuration
#define FLASH_CTRL_PHY_ALERT_CFG_REG_OFFSET 0x198
#define FLASH_CTRL_PHY_ALERT_CFG_REG_RESVAL 0x0u
#define FLASH_CTRL_PHY_ALERT_CFG_ALERT_ACK_BIT 0
#define FLASH_CTRL_PHY_ALERT_CFG_ALERT_TRIG_BIT 1
 
// Flash Phy Status
#define FLASH_CTRL_PHY_STATUS_REG_OFFSET 0x19c
#define FLASH_CTRL_PHY_STATUS_REG_RESVAL 0x6u
#define FLASH_CTRL_PHY_STATUS_INIT_WIP_BIT 0
#define FLASH_CTRL_PHY_STATUS_PROG_NORMAL_AVAIL_BIT 1
#define FLASH_CTRL_PHY_STATUS_PROG_REPAIR_AVAIL_BIT 2
 
// Flash Controller Scratch
#define FLASH_CTRL_SCRATCH_REG_OFFSET 0x1a0
#define FLASH_CTRL_SCRATCH_REG_RESVAL 0x0u
 
// Programmable depth where FIFOs should generate interrupts
#define FLASH_CTRL_FIFO_LVL_REG_OFFSET 0x1a4
#define FLASH_CTRL_FIFO_LVL_REG_RESVAL 0xf0fu
#define FLASH_CTRL_FIFO_LVL_PROG_MASK 0x1fu
#define FLASH_CTRL_FIFO_LVL_PROG_OFFSET 0
#define FLASH_CTRL_FIFO_LVL_PROG_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_FIFO_LVL_PROG_MASK, .index = FLASH_CTRL_FIFO_LVL_PROG_OFFSET })
#define FLASH_CTRL_FIFO_LVL_RD_MASK 0x1fu
#define FLASH_CTRL_FIFO_LVL_RD_OFFSET 8
#define FLASH_CTRL_FIFO_LVL_RD_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_FIFO_LVL_RD_MASK, .index = FLASH_CTRL_FIFO_LVL_RD_OFFSET })
 
// Reset for flash controller FIFOs
#define FLASH_CTRL_FIFO_RST_REG_OFFSET 0x1a8
#define FLASH_CTRL_FIFO_RST_REG_RESVAL 0x0u
#define FLASH_CTRL_FIFO_RST_EN_BIT 0
 
// Current program and read fifo depth
#define FLASH_CTRL_CURR_FIFO_LVL_REG_OFFSET 0x1ac
#define FLASH_CTRL_CURR_FIFO_LVL_REG_RESVAL 0x0u
#define FLASH_CTRL_CURR_FIFO_LVL_PROG_MASK 0x1fu
#define FLASH_CTRL_CURR_FIFO_LVL_PROG_OFFSET 0
#define FLASH_CTRL_CURR_FIFO_LVL_PROG_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CURR_FIFO_LVL_PROG_MASK, .index = FLASH_CTRL_CURR_FIFO_LVL_PROG_OFFSET })
#define FLASH_CTRL_CURR_FIFO_LVL_RD_MASK 0x1fu
#define FLASH_CTRL_CURR_FIFO_LVL_RD_OFFSET 8
#define FLASH_CTRL_CURR_FIFO_LVL_RD_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CURR_FIFO_LVL_RD_MASK, .index = FLASH_CTRL_CURR_FIFO_LVL_RD_OFFSET })
 
// Memory area: Flash program FIFO.
#define FLASH_CTRL_PROG_FIFO_REG_OFFSET 0x1b0
#define FLASH_CTRL_PROG_FIFO_SIZE_WORDS 1
#define FLASH_CTRL_PROG_FIFO_SIZE_BYTES 4
// Memory area: Flash read FIFO.
#define FLASH_CTRL_RD_FIFO_REG_OFFSET 0x1b4
#define FLASH_CTRL_RD_FIFO_SIZE_WORDS 1
#define FLASH_CTRL_RD_FIFO_SIZE_BYTES 4
 
#define FLASH_CTRL_CSR0_REGWEN_REG_OFFSET 0x0
#define FLASH_CTRL_CSR0_REGWEN_REG_RESVAL 0x1u
#define FLASH_CTRL_CSR0_REGWEN_FIELD0_BIT 0
 
 
#define FLASH_CTRL_CSR1_REG_OFFSET 0x4
#define FLASH_CTRL_CSR1_REG_RESVAL 0x0u
#define FLASH_CTRL_CSR1_FIELD0_MASK 0xffu
#define FLASH_CTRL_CSR1_FIELD0_OFFSET 0
#define FLASH_CTRL_CSR1_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR1_FIELD0_MASK, .index = FLASH_CTRL_CSR1_FIELD0_OFFSET })
#define FLASH_CTRL_CSR1_FIELD1_MASK 0x1fu
#define FLASH_CTRL_CSR1_FIELD1_OFFSET 8
#define FLASH_CTRL_CSR1_FIELD1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR1_FIELD1_MASK, .index = FLASH_CTRL_CSR1_FIELD1_OFFSET })
 
 
#define FLASH_CTRL_CSR2_REG_OFFSET 0x8
#define FLASH_CTRL_CSR2_REG_RESVAL 0x0u
#define FLASH_CTRL_CSR2_FIELD0_BIT 0
#define FLASH_CTRL_CSR2_FIELD1_BIT 1
#define FLASH_CTRL_CSR2_FIELD2_BIT 2
#define FLASH_CTRL_CSR2_FIELD3_BIT 3
#define FLASH_CTRL_CSR2_FIELD4_BIT 4
#define FLASH_CTRL_CSR2_FIELD5_BIT 5
#define FLASH_CTRL_CSR2_FIELD6_BIT 6
#define FLASH_CTRL_CSR2_FIELD7_BIT 7
 
 
#define FLASH_CTRL_CSR3_REG_OFFSET 0xc
#define FLASH_CTRL_CSR3_REG_RESVAL 0x0u
#define FLASH_CTRL_CSR3_FIELD0_MASK 0xfu
#define FLASH_CTRL_CSR3_FIELD0_OFFSET 0
#define FLASH_CTRL_CSR3_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR3_FIELD0_MASK, .index = FLASH_CTRL_CSR3_FIELD0_OFFSET })
#define FLASH_CTRL_CSR3_FIELD1_MASK 0xfu
#define FLASH_CTRL_CSR3_FIELD1_OFFSET 4
#define FLASH_CTRL_CSR3_FIELD1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR3_FIELD1_MASK, .index = FLASH_CTRL_CSR3_FIELD1_OFFSET })
#define FLASH_CTRL_CSR3_FIELD2_MASK 0x7u
#define FLASH_CTRL_CSR3_FIELD2_OFFSET 8
#define FLASH_CTRL_CSR3_FIELD2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR3_FIELD2_MASK, .index = FLASH_CTRL_CSR3_FIELD2_OFFSET })
#define FLASH_CTRL_CSR3_FIELD3_MASK 0x7u
#define FLASH_CTRL_CSR3_FIELD3_OFFSET 11
#define FLASH_CTRL_CSR3_FIELD3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR3_FIELD3_MASK, .index = FLASH_CTRL_CSR3_FIELD3_OFFSET })
#define FLASH_CTRL_CSR3_FIELD4_MASK 0x7u
#define FLASH_CTRL_CSR3_FIELD4_OFFSET 14
#define FLASH_CTRL_CSR3_FIELD4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR3_FIELD4_MASK, .index = FLASH_CTRL_CSR3_FIELD4_OFFSET })
#define FLASH_CTRL_CSR3_FIELD5_MASK 0x7u
#define FLASH_CTRL_CSR3_FIELD5_OFFSET 17
#define FLASH_CTRL_CSR3_FIELD5_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR3_FIELD5_MASK, .index = FLASH_CTRL_CSR3_FIELD5_OFFSET })
#define FLASH_CTRL_CSR3_FIELD6_BIT 20
#define FLASH_CTRL_CSR3_FIELD7_MASK 0x7u
#define FLASH_CTRL_CSR3_FIELD7_OFFSET 21
#define FLASH_CTRL_CSR3_FIELD7_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR3_FIELD7_MASK, .index = FLASH_CTRL_CSR3_FIELD7_OFFSET })
#define FLASH_CTRL_CSR3_FIELD8_MASK 0x3u
#define FLASH_CTRL_CSR3_FIELD8_OFFSET 24
#define FLASH_CTRL_CSR3_FIELD8_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR3_FIELD8_MASK, .index = FLASH_CTRL_CSR3_FIELD8_OFFSET })
#define FLASH_CTRL_CSR3_FIELD9_MASK 0x3u
#define FLASH_CTRL_CSR3_FIELD9_OFFSET 26
#define FLASH_CTRL_CSR3_FIELD9_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR3_FIELD9_MASK, .index = FLASH_CTRL_CSR3_FIELD9_OFFSET })
 
 
#define FLASH_CTRL_CSR4_REG_OFFSET 0x10
#define FLASH_CTRL_CSR4_REG_RESVAL 0x0u
#define FLASH_CTRL_CSR4_FIELD0_MASK 0x7u
#define FLASH_CTRL_CSR4_FIELD0_OFFSET 0
#define FLASH_CTRL_CSR4_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR4_FIELD0_MASK, .index = FLASH_CTRL_CSR4_FIELD0_OFFSET })
#define FLASH_CTRL_CSR4_FIELD1_MASK 0x7u
#define FLASH_CTRL_CSR4_FIELD1_OFFSET 3
#define FLASH_CTRL_CSR4_FIELD1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR4_FIELD1_MASK, .index = FLASH_CTRL_CSR4_FIELD1_OFFSET })
#define FLASH_CTRL_CSR4_FIELD2_MASK 0x7u
#define FLASH_CTRL_CSR4_FIELD2_OFFSET 6
#define FLASH_CTRL_CSR4_FIELD2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR4_FIELD2_MASK, .index = FLASH_CTRL_CSR4_FIELD2_OFFSET })
#define FLASH_CTRL_CSR4_FIELD3_MASK 0x7u
#define FLASH_CTRL_CSR4_FIELD3_OFFSET 9
#define FLASH_CTRL_CSR4_FIELD3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR4_FIELD3_MASK, .index = FLASH_CTRL_CSR4_FIELD3_OFFSET })
 
 
#define FLASH_CTRL_CSR5_REG_OFFSET 0x14
#define FLASH_CTRL_CSR5_REG_RESVAL 0x0u
#define FLASH_CTRL_CSR5_FIELD0_MASK 0x7u
#define FLASH_CTRL_CSR5_FIELD0_OFFSET 0
#define FLASH_CTRL_CSR5_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR5_FIELD0_MASK, .index = FLASH_CTRL_CSR5_FIELD0_OFFSET })
#define FLASH_CTRL_CSR5_FIELD1_MASK 0x3u
#define FLASH_CTRL_CSR5_FIELD1_OFFSET 3
#define FLASH_CTRL_CSR5_FIELD1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR5_FIELD1_MASK, .index = FLASH_CTRL_CSR5_FIELD1_OFFSET })
#define FLASH_CTRL_CSR5_FIELD2_MASK 0x1ffu
#define FLASH_CTRL_CSR5_FIELD2_OFFSET 5
#define FLASH_CTRL_CSR5_FIELD2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR5_FIELD2_MASK, .index = FLASH_CTRL_CSR5_FIELD2_OFFSET })
#define FLASH_CTRL_CSR5_FIELD3_MASK 0x1fu
#define FLASH_CTRL_CSR5_FIELD3_OFFSET 14
#define FLASH_CTRL_CSR5_FIELD3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR5_FIELD3_MASK, .index = FLASH_CTRL_CSR5_FIELD3_OFFSET })
#define FLASH_CTRL_CSR5_FIELD4_MASK 0xfu
#define FLASH_CTRL_CSR5_FIELD4_OFFSET 19
#define FLASH_CTRL_CSR5_FIELD4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR5_FIELD4_MASK, .index = FLASH_CTRL_CSR5_FIELD4_OFFSET })
 
 
#define FLASH_CTRL_CSR6_REG_OFFSET 0x18
#define FLASH_CTRL_CSR6_REG_RESVAL 0x0u
#define FLASH_CTRL_CSR6_FIELD0_MASK 0x7u
#define FLASH_CTRL_CSR6_FIELD0_OFFSET 0
#define FLASH_CTRL_CSR6_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR6_FIELD0_MASK, .index = FLASH_CTRL_CSR6_FIELD0_OFFSET })
#define FLASH_CTRL_CSR6_FIELD1_MASK 0x7u
#define FLASH_CTRL_CSR6_FIELD1_OFFSET 3
#define FLASH_CTRL_CSR6_FIELD1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR6_FIELD1_MASK, .index = FLASH_CTRL_CSR6_FIELD1_OFFSET })
#define FLASH_CTRL_CSR6_FIELD2_MASK 0xffu
#define FLASH_CTRL_CSR6_FIELD2_OFFSET 6
#define FLASH_CTRL_CSR6_FIELD2_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR6_FIELD2_MASK, .index = FLASH_CTRL_CSR6_FIELD2_OFFSET })
#define FLASH_CTRL_CSR6_FIELD3_MASK 0x7u
#define FLASH_CTRL_CSR6_FIELD3_OFFSET 14
#define FLASH_CTRL_CSR6_FIELD3_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR6_FIELD3_MASK, .index = FLASH_CTRL_CSR6_FIELD3_OFFSET })
#define FLASH_CTRL_CSR6_FIELD4_MASK 0x3u
#define FLASH_CTRL_CSR6_FIELD4_OFFSET 17
#define FLASH_CTRL_CSR6_FIELD4_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR6_FIELD4_MASK, .index = FLASH_CTRL_CSR6_FIELD4_OFFSET })
#define FLASH_CTRL_CSR6_FIELD5_MASK 0x3u
#define FLASH_CTRL_CSR6_FIELD5_OFFSET 19
#define FLASH_CTRL_CSR6_FIELD5_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR6_FIELD5_MASK, .index = FLASH_CTRL_CSR6_FIELD5_OFFSET })
#define FLASH_CTRL_CSR6_FIELD6_MASK 0x3u
#define FLASH_CTRL_CSR6_FIELD6_OFFSET 21
#define FLASH_CTRL_CSR6_FIELD6_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR6_FIELD6_MASK, .index = FLASH_CTRL_CSR6_FIELD6_OFFSET })
#define FLASH_CTRL_CSR6_FIELD7_BIT 23
#define FLASH_CTRL_CSR6_FIELD8_BIT 24
 
 
#define FLASH_CTRL_CSR7_REG_OFFSET 0x1c
#define FLASH_CTRL_CSR7_REG_RESVAL 0x0u
#define FLASH_CTRL_CSR7_FIELD0_MASK 0xffu
#define FLASH_CTRL_CSR7_FIELD0_OFFSET 0
#define FLASH_CTRL_CSR7_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR7_FIELD0_MASK, .index = FLASH_CTRL_CSR7_FIELD0_OFFSET })
#define FLASH_CTRL_CSR7_FIELD1_MASK 0x1ffu
#define FLASH_CTRL_CSR7_FIELD1_OFFSET 8
#define FLASH_CTRL_CSR7_FIELD1_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR7_FIELD1_MASK, .index = FLASH_CTRL_CSR7_FIELD1_OFFSET })
 
 
#define FLASH_CTRL_CSR8_REG_OFFSET 0x20
#define FLASH_CTRL_CSR8_REG_RESVAL 0x0u
 
 
#define FLASH_CTRL_CSR9_REG_OFFSET 0x24
#define FLASH_CTRL_CSR9_REG_RESVAL 0x0u
 
 
#define FLASH_CTRL_CSR10_REG_OFFSET 0x28
#define FLASH_CTRL_CSR10_REG_RESVAL 0x0u
 
 
#define FLASH_CTRL_CSR11_REG_OFFSET 0x2c
#define FLASH_CTRL_CSR11_REG_RESVAL 0x0u
 
 
#define FLASH_CTRL_CSR12_REG_OFFSET 0x30
#define FLASH_CTRL_CSR12_REG_RESVAL 0x0u
#define FLASH_CTRL_CSR12_FIELD0_MASK 0x3ffu
#define FLASH_CTRL_CSR12_FIELD0_OFFSET 0
#define FLASH_CTRL_CSR12_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR12_FIELD0_MASK, .index = FLASH_CTRL_CSR12_FIELD0_OFFSET })
 
 
#define FLASH_CTRL_CSR13_REG_OFFSET 0x34
#define FLASH_CTRL_CSR13_REG_RESVAL 0x0u
#define FLASH_CTRL_CSR13_FIELD0_MASK 0xfffffu
#define FLASH_CTRL_CSR13_FIELD0_OFFSET 0
#define FLASH_CTRL_CSR13_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR13_FIELD0_MASK, .index = FLASH_CTRL_CSR13_FIELD0_OFFSET })
#define FLASH_CTRL_CSR13_FIELD1_BIT 20
 
 
#define FLASH_CTRL_CSR14_REG_OFFSET 0x38
#define FLASH_CTRL_CSR14_REG_RESVAL 0x0u
#define FLASH_CTRL_CSR14_FIELD0_MASK 0xffu
#define FLASH_CTRL_CSR14_FIELD0_OFFSET 0
#define FLASH_CTRL_CSR14_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR14_FIELD0_MASK, .index = FLASH_CTRL_CSR14_FIELD0_OFFSET })
#define FLASH_CTRL_CSR14_FIELD1_BIT 8
 
 
#define FLASH_CTRL_CSR15_REG_OFFSET 0x3c
#define FLASH_CTRL_CSR15_REG_RESVAL 0x0u
#define FLASH_CTRL_CSR15_FIELD0_MASK 0xffu
#define FLASH_CTRL_CSR15_FIELD0_OFFSET 0
#define FLASH_CTRL_CSR15_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR15_FIELD0_MASK, .index = FLASH_CTRL_CSR15_FIELD0_OFFSET })
#define FLASH_CTRL_CSR15_FIELD1_BIT 8
 
 
#define FLASH_CTRL_CSR16_REG_OFFSET 0x40
#define FLASH_CTRL_CSR16_REG_RESVAL 0x0u
#define FLASH_CTRL_CSR16_FIELD0_MASK 0xffu
#define FLASH_CTRL_CSR16_FIELD0_OFFSET 0
#define FLASH_CTRL_CSR16_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR16_FIELD0_MASK, .index = FLASH_CTRL_CSR16_FIELD0_OFFSET })
#define FLASH_CTRL_CSR16_FIELD1_BIT 8
 
 
#define FLASH_CTRL_CSR17_REG_OFFSET 0x44
#define FLASH_CTRL_CSR17_REG_RESVAL 0x0u
#define FLASH_CTRL_CSR17_FIELD0_MASK 0xffu
#define FLASH_CTRL_CSR17_FIELD0_OFFSET 0
#define FLASH_CTRL_CSR17_FIELD0_FIELD \
  ((bitfield_field32_t) { .mask = FLASH_CTRL_CSR17_FIELD0_MASK, .index = FLASH_CTRL_CSR17_FIELD0_OFFSET })
#define FLASH_CTRL_CSR17_FIELD1_BIT 8
 
 
#define FLASH_CTRL_CSR18_REG_OFFSET 0x48
#define FLASH_CTRL_CSR18_REG_RESVAL 0x0u
#define FLASH_CTRL_CSR18_FIELD0_BIT 0
 
 
#define FLASH_CTRL_CSR19_REG_OFFSET 0x4c
#define FLASH_CTRL_CSR19_REG_RESVAL 0x0u
#define FLASH_CTRL_CSR19_FIELD0_BIT 0
 
 
#define FLASH_CTRL_CSR20_REG_OFFSET 0x50
#define FLASH_CTRL_CSR20_REG_RESVAL 0x0u
#define FLASH_CTRL_CSR20_FIELD0_BIT 0
#define FLASH_CTRL_CSR20_FIELD1_BIT 1
#define FLASH_CTRL_CSR20_FIELD2_BIT 2
 
#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _FLASH_CTRL_REG_DEFS_
// End generated register defines for flash_ctrl