Software APIs
epmp_defs.h
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 #ifndef OPENTITAN_SW_DEVICE_SILICON_CREATOR_LIB_EPMP_DEFS_H_
6 #define OPENTITAN_SW_DEVICE_SILICON_CREATOR_LIB_EPMP_DEFS_H_
7 
8 /**
9  * Constants for use when interacting with the enhanced Physical Memory
10  * Protection control registers.
11  *
12  * See the Ibex Physical Memory Protection documentation for more
13  * details:
14  *
15  * https://ibex-core.readthedocs.io/en/latest/03_reference/pmp.html
16  *
17  * Note: this file must be usable from assembly, C and C++ files and
18  * should therefore only contain constant definitions.
19  */
20 
21 /**
22  * Address of the Machine Security Configuration control register.
23  *
24  * For use with CSR operations such as read, write, set and clear.
25  */
26 #define EPMP_MSECCFG 0x747
27 
28 /**
29  * Machine Security Configuration bits.
30  *
31  * MML = Machine Mode Lockdown
32  * MMWP = Machine Mode Whitelist Policy
33  * RLB = Rule Locking Bypass
34  */
35 #define EPMP_MSECCFG_MML (1 << 0)
36 #define EPMP_MSECCFG_MMWP (1 << 1)
37 #define EPMP_MSECCFG_RLB (1 << 2)
38 
39 /**
40  * PMP configuration (`pmpNcfg`) register fields.
41  *
42  * 8 7 5 3 2 1 0
43  * +---+-------+-------+---+---+---+
44  * | L | 0 | A | X | W | R |
45  * +---+-------+-------+---+---+---+
46  *
47  * Key:
48  *
49  * L - lock
50  * A - addressing mode (OFF=0, TOR=1, NA4=2, NAPOT=3)
51  * X - execute
52  * W - write
53  * R - read
54  *
55  * Note that there are four 8-bit configuration fields (`pmpNcfg`)
56  * packed into each hardware configuration register (`pmpcfgN`).
57  */
58 #define EPMP_CFG_L (1 << 7)
59 #define EPMP_CFG_A_MASK (3 << 3)
60 #define EPMP_CFG_A_OFF (0 << 3)
61 #define EPMP_CFG_A_TOR (1 << 3)
62 #define EPMP_CFG_A_NA4 (2 << 3)
63 #define EPMP_CFG_A_NAPOT (3 << 3)
64 #define EPMP_CFG_X (1 << 2)
65 #define EPMP_CFG_W (1 << 1)
66 #define EPMP_CFG_R (1 << 0)
67 
68 /**
69  * Common PMP configuration (`pmpNcfg`) permission combinations.
70  */
71 #define EPMP_CFG_LR (EPMP_CFG_L | EPMP_CFG_R)
72 #define EPMP_CFG_LRX (EPMP_CFG_L | EPMP_CFG_R | EPMP_CFG_X)
73 #define EPMP_CFG_LRW (EPMP_CFG_L | EPMP_CFG_R | EPMP_CFG_W)
74 #define EPMP_CFG_LRWX (EPMP_CFG_L | EPMP_CFG_R | EPMP_CFG_W | EPMP_CFG_X)
75 
76 #endif // OPENTITAN_SW_DEVICE_SILICON_CREATOR_LIB_EPMP_DEFS_H_
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