Software APIs
dt_sysrst_ctrl.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7#ifndef OPENTITAN_DT_SYSRST_CTRL_H_
8#define OPENTITAN_DT_SYSRST_CTRL_H_
9
10#ifdef __cplusplus
11extern "C" {
12#endif // __cplusplus
13
14/**
15 * @file
16 * @brief Device Tables (DT) for IP sysrst_ctrl and top earlgrey.
17 *
18 * This file contains the type definitions and global functions of the sysrst_ctrl.
19 */
20
21#include "hw/top/dt/dt_api.h"
22#include <stdint.h>
23
24
25
26/**
27 * List of instances.
28 */
29typedef enum dt_sysrst_ctrl {
30 kDtSysrstCtrlAon = 0, /**< sysrst_ctrl_aon */
31 kDtSysrstCtrlFirst = 0, /**< \internal First instance */
32 kDtSysrstCtrlCount = 1, /**< \internal Number of instances */
34
35/**
36 * List of register blocks.
37 *
38 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
39 */
41 kDtSysrstCtrlRegBlockCore = 0, /**< */
42 kDtSysrstCtrlRegBlockCount = 1, /**< \internal Number of register blocks */
44
45/** Primary register block (associated with the "primary" set of registers that control the IP). */
46static const dt_sysrst_ctrl_reg_block_t kDtSysrstCtrlRegBlockPrimary = kDtSysrstCtrlRegBlockCore;
47
48/**
49 * List of memories.
50 *
51 * Memories are guaranteed to start at 0 and to be consecutively numbered.
52 */
54 kDtSysrstCtrlMemoryCount = 0, /**< \internal Number of memories */
56
57/**
58 * List of IRQs.
59 *
60 * IRQs are guaranteed to be numbered consecutively from 0.
61 */
62typedef enum dt_sysrst_ctrl_irq {
63 kDtSysrstCtrlIrqEventDetected = 0, /**< Common interrupt triggered by combo or keyboard events. */
64 kDtSysrstCtrlIrqCount = 1, /**< \internal Number of IRQs */
66
67/**
68 * List of Alerts.
69 *
70 * Alerts are guaranteed to be numbered consecutively from 0.
71 */
73 kDtSysrstCtrlAlertFatalFault = 0, /**< This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. */
74 kDtSysrstCtrlAlertCount = 1, /**< \internal Number of Alerts */
76
77/**
78 * List of clock ports.
79 *
80 * Clock ports are guaranteed to be numbered consecutively from 0.
81 */
83 kDtSysrstCtrlClockClk = 0, /**< Clock port clk_i */
84 kDtSysrstCtrlClockAon = 1, /**< Clock port clk_aon_i */
85 kDtSysrstCtrlClockCount = 2, /**< \internal Number of clock ports */
87
88/**
89 * List of reset requests.
90 *
91 * Reset requests are guaranteed to be numbered consecutively from 0.
92 */
94 kDtSysrstCtrlResetReqRstReq = 0, /**< OpenTitan reset request to `rstmgr` (running on AON clock). */
95 kDtSysrstCtrlResetReqCount = 1, /**< \internal Number of reset requests */
97
98/**
99 * List of reset ports.
100 *
101 * Reset ports are guaranteed to be numbered consecutively from 0.
102 */
104 kDtSysrstCtrlResetRst = 0, /**< Reset port rst_ni */
105 kDtSysrstCtrlResetAon = 1, /**< Reset port rst_aon_ni */
106 kDtSysrstCtrlResetCount = 2, /**< \internal Number of reset ports */
108
109/**
110 * List of peripheral I/O.
111 *
112 * Peripheral I/O are guaranteed to be numbered consecutively from 0.
113 */
115 kDtSysrstCtrlPeriphIoAcPresent = 0, /**< */
116 kDtSysrstCtrlPeriphIoKey0In = 1, /**< */
117 kDtSysrstCtrlPeriphIoKey1In = 2, /**< */
118 kDtSysrstCtrlPeriphIoKey2In = 3, /**< */
119 kDtSysrstCtrlPeriphIoPwrbIn = 4, /**< */
120 kDtSysrstCtrlPeriphIoLidOpen = 5, /**< */
121 kDtSysrstCtrlPeriphIoBatDisable = 6, /**< */
122 kDtSysrstCtrlPeriphIoKey0Out = 7, /**< */
123 kDtSysrstCtrlPeriphIoKey1Out = 8, /**< */
124 kDtSysrstCtrlPeriphIoKey2Out = 9, /**< */
125 kDtSysrstCtrlPeriphIoPwrbOut = 10, /**< */
126 kDtSysrstCtrlPeriphIoZ3Wakeup = 11, /**< */
127 kDtSysrstCtrlPeriphIoEcRstL = 12, /**< */
128 kDtSysrstCtrlPeriphIoFlashWpL = 13, /**< */
129 kDtSysrstCtrlPeriphIoCount = 14, /**< \internal Number of peripheral I/O */
131
132/**
133 * List of wakeups.
134 *
135 * Wakeups are guaranteed to be numbered consecutively from 0.
136 */
138 kDtSysrstCtrlWakeupWkupReq = 0, /**< OpenTitan wake request signal to `pwrmgr` (running on AON clock). */
139 kDtSysrstCtrlWakeupCount = 1, /**< \internal Number of wakeups */
141
142/**
143 * List of supported hardware features.
144 */
145#define OPENTITAN_SYSRST_CTRL_HAS_COMBO_DETECT 1
146#define OPENTITAN_SYSRST_CTRL_HAS_AUTO_BLOCK_KEY_OUTPUT 1
147#define OPENTITAN_SYSRST_CTRL_HAS_INPUT_TRIGGERED_INTERRUPT 1
148#define OPENTITAN_SYSRST_CTRL_HAS_ULTRA_LOW_POWER_WAKEUP 1
149#define OPENTITAN_SYSRST_CTRL_HAS_PINOUT_KEY_INVERSION_CONTROL 1
150#define OPENTITAN_SYSRST_CTRL_HAS_HARDWARE_RESET_STRETCH 1
151#define OPENTITAN_SYSRST_CTRL_HAS_FLASH_WRITE_PROTECT 1
152#define OPENTITAN_SYSRST_CTRL_HAS_PIN_INPUT_VALUE_ACCESS 1
153
154
155
156/**
157 * Get the sysrst_ctrl instance from an instance ID
158 *
159 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
160 *
161 * @param inst_id Instance ID.
162 * @return A sysrst_ctrl instance.
163 *
164 * **Note:** This function only makes sense if the instance ID has device type sysrst_ctrl,
165 * otherwise the returned value is unspecified.
166 */
168
169/**
170 * Get the instance ID of an instance.
171 *
172 * @param dt Instance of sysrst_ctrl.
173 * @return The instance ID of that instance.
174 */
176
177/**
178 * Get the register base address of an instance.
179 *
180 * @param dt Instance of sysrst_ctrl.
181 * @param reg_block The register block requested.
182 * @return The register base address of the requested block.
183 */
187
188/**
189 * Get the primary register base address of an instance.
190 *
191 * This is just a convenience function, equivalent to
192 * `dt_sysrst_ctrl_reg_block(dt, kDtSysrstCtrlRegBlockCore)`
193 *
194 * @param dt Instance of sysrst_ctrl.
195 * @return The register base address of the primary register block.
196 */
197static inline uint32_t dt_sysrst_ctrl_primary_reg_block(
198 dt_sysrst_ctrl_t dt) {
199 return dt_sysrst_ctrl_reg_block(dt, kDtSysrstCtrlRegBlockCore);
200}
201
202/**
203 * Get the base address of a memory.
204 *
205 * @param dt Instance of sysrst_ctrl.
206 * @param mem The memory requested.
207 * @return The base address of the requested memory.
208 */
212
213/**
214 * Get the size of a memory.
215 *
216 * @param dt Instance of sysrst_ctrl.
217 * @param mem The memory requested.
218 * @return The size of the requested memory.
219 */
223
224/**
225 * Get the PLIC ID of a sysrst_ctrl IRQ for a given instance.
226 *
227 * If the instance is not connected to the PLIC, this function
228 * will return `kDtPlicIrqIdNone`.
229 *
230 * @param dt Instance of sysrst_ctrl.
231 * @param irq A sysrst_ctrl IRQ.
232 * @return The PLIC ID of the IRQ of this instance.
233 */
237
238/**
239 * Convert a global IRQ ID to a local sysrst_ctrl IRQ type.
240 *
241 * @param dt Instance of sysrst_ctrl.
242 * @param irq A PLIC ID that belongs to this instance.
243 * @return The sysrst_ctrl IRQ, or `kDtSysrstCtrlIrqCount`.
244 *
245 * **Note:** This function assumes that the PLIC ID belongs to the instance
246 * of sysrst_ctrl passed in parameter. In other words, it must be the case that
247 * `dt_sysrst_ctrl_instance_id(dt) == dt_plic_id_to_instance_id(irq)`. Otherwise, this function
248 * will return `kDtSysrstCtrlIrqCount`.
249 */
252 dt_plic_irq_id_t irq);
253
254
255/**
256 * Get the alert ID of a sysrst_ctrl alert for a given instance.
257 *
258 * **Note:** This function only makes sense if the instance is connected to the Alert Handler. For any
259 * instances where the instance is not connected, the return value is unspecified.
260 *
261 * @param dt Instance of sysrst_ctrl.
262 * @param alert A sysrst_ctrl alert.
263 * @return The Alert Handler alert ID of the alert of this instance.
264 */
268
269/**
270 * Convert a global alert ID to a local sysrst_ctrl alert type.
271 *
272 * @param dt Instance of sysrst_ctrl.
273 * @param alert A global alert ID that belongs to this instance.
274 * @return The sysrst_ctrl alert, or `kDtSysrstCtrlAlertCount`.
275 *
276 * **Note:** This function assumes that the global alert ID belongs to the
277 * instance of sysrst_ctrl passed in parameter. In other words, it must be the case
278 * that `dt_sysrst_ctrl_instance_id(dt) == dt_alert_id_to_instance_id(alert)`. Otherwise,
279 * this function will return `kDtSysrstCtrlAlertCount`.
280 */
283 dt_alert_id_t alert);
284
285
286/**
287 * Get the peripheral I/O description of an instance.
288 *
289 * @param dt Instance of sysrst_ctrl.
290 * @param sig Requested peripheral I/O.
291 * @return Description of the requested peripheral I/O for this instance.
292 */
296
297/**
298 * Get the clock signal connected to a clock port of an instance.
299 *
300 * @param dt Instance of sysrst_ctrl.
301 * @param clk Clock port.
302 * @return Clock signal.
303 */
307
308/**
309 * Get the reset signal connected to a reset port of an instance.
310 *
311 * @param dt Instance of sysrst_ctrl.
312 * @param rst Reset port.
313 * @return Reset signal.
314 */
318
319
320
321#ifdef __cplusplus
322} // extern "C"
323#endif // __cplusplus
324
325#endif // OPENTITAN_DT_SYSRST_CTRL_H_