dt_sysrst_ctrl.h

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// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Device table API auto-generated by `dtgen`
 
#ifndef OPENTITAN_DT_SYSRST_CTRL_H_
#define OPENTITAN_DT_SYSRST_CTRL_H_
 
#ifdef __cplusplus
extern "C" {
#endif  // __cplusplus
 
/**
 * @file
 * @brief Device Tables (DT) for IP sysrst_ctrl and top earlgrey.
 *
 * This file contains the type definitions and global functions of the sysrst_ctrl.
 */
 
#include "hw/top/dt/dt_api.h"
#include <stdint.h>
 
 
 
/**
 * List of instances.
 */
typedef enum dt_sysrst_ctrl {
  kDtSysrstCtrlAon = 0, /**< sysrst_ctrl_aon */
  kDtSysrstCtrlFirst = 0, /**< \internal First instance */
  kDtSysrstCtrlCount = 1, /**< \internal Number of instances */
} dt_sysrst_ctrl_t;
 
/**
 * List of register blocks.
 *
 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
 */
typedef enum dt_sysrst_ctrl_reg_block {
  kDtSysrstCtrlRegBlockCore = 0, /**<  */
  kDtSysrstCtrlRegBlockCount = 1, /**< \internal Number of register blocks */
} dt_sysrst_ctrl_reg_block_t;
 
/** Primary register block (associated with the "primary" set of registers that control the IP). */
static const dt_sysrst_ctrl_reg_block_t kDtSysrstCtrlRegBlockPrimary = kDtSysrstCtrlRegBlockCore;
 
/**
 * List of memories.
 *
 * Memories are guaranteed to start at 0 and to be consecutively numbered.
 */
typedef enum dt_sysrst_ctrl_memory {
  kDtSysrstCtrlMemoryCount = 0, /**< \internal Number of memories */
} dt_sysrst_ctrl_memory_t;
 
/**
 * List of IRQs.
 *
 * IRQs are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_sysrst_ctrl_irq {
  kDtSysrstCtrlIrqEventDetected = 0, /**< Common interrupt triggered by combo or keyboard events. */
  kDtSysrstCtrlIrqCount = 1, /**< \internal Number of IRQs */
} dt_sysrst_ctrl_irq_t;
 
/**
 * List of Alerts.
 *
 * Alerts are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_sysrst_ctrl_alert {
  kDtSysrstCtrlAlertFatalFault = 0, /**< This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. */
  kDtSysrstCtrlAlertCount = 1, /**< \internal Number of Alerts */
} dt_sysrst_ctrl_alert_t;
 
/**
 * List of clock ports.
 *
 * Clock ports are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_sysrst_ctrl_clock {
  kDtSysrstCtrlClockClk = 0, /**< Clock port clk_i */
  kDtSysrstCtrlClockAon = 1, /**< Clock port clk_aon_i */
  kDtSysrstCtrlClockCount = 2, /**< \internal Number of clock ports */
} dt_sysrst_ctrl_clock_t;
 
/**
 * List of reset requests.
 *
 * Reset requests are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_sysrst_ctrl_reset_req {
  kDtSysrstCtrlResetReqRstReq = 0, /**< OpenTitan reset request to `rstmgr` (running on AON clock). */
  kDtSysrstCtrlResetReqCount = 1, /**< \internal Number of reset requests */
} dt_sysrst_ctrl_reset_req_t;
 
/**
 * List of reset ports.
 *
 * Reset ports are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_sysrst_ctrl_reset {
  kDtSysrstCtrlResetRst = 0, /**< Reset port rst_ni */
  kDtSysrstCtrlResetAon = 1, /**< Reset port rst_aon_ni */
  kDtSysrstCtrlResetCount = 2, /**< \internal Number of reset ports */
} dt_sysrst_ctrl_reset_t;
 
/**
 * List of peripheral I/O.
 *
 * Peripheral I/O are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_sysrst_ctrl_periph_io {
  kDtSysrstCtrlPeriphIoAcPresent = 0, /**<  */
  kDtSysrstCtrlPeriphIoKey0In = 1, /**<  */
  kDtSysrstCtrlPeriphIoKey1In = 2, /**<  */
  kDtSysrstCtrlPeriphIoKey2In = 3, /**<  */
  kDtSysrstCtrlPeriphIoPwrbIn = 4, /**<  */
  kDtSysrstCtrlPeriphIoLidOpen = 5, /**<  */
  kDtSysrstCtrlPeriphIoBatDisable = 6, /**<  */
  kDtSysrstCtrlPeriphIoKey0Out = 7, /**<  */
  kDtSysrstCtrlPeriphIoKey1Out = 8, /**<  */
  kDtSysrstCtrlPeriphIoKey2Out = 9, /**<  */
  kDtSysrstCtrlPeriphIoPwrbOut = 10, /**<  */
  kDtSysrstCtrlPeriphIoZ3Wakeup = 11, /**<  */
  kDtSysrstCtrlPeriphIoEcRstL = 12, /**<  */
  kDtSysrstCtrlPeriphIoFlashWpL = 13, /**<  */
  kDtSysrstCtrlPeriphIoCount = 14, /**< \internal Number of peripheral I/O */
} dt_sysrst_ctrl_periph_io_t;
 
/**
 * List of wakeups.
 *
 * Wakeups are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_sysrst_ctrl_wakeup {
  kDtSysrstCtrlWakeupWkupReq = 0, /**< OpenTitan wake request signal to `pwrmgr` (running on AON clock). */
  kDtSysrstCtrlWakeupCount = 1, /**< \internal Number of wakeups */
} dt_sysrst_ctrl_wakeup_t;
 
/**
 * List of supported hardware features.
 */
#define OPENTITAN_SYSRST_CTRL_HAS_COMBO_DETECT 1
#define OPENTITAN_SYSRST_CTRL_HAS_AUTO_BLOCK_KEY_OUTPUT 1
#define OPENTITAN_SYSRST_CTRL_HAS_INPUT_TRIGGERED_INTERRUPT 1
#define OPENTITAN_SYSRST_CTRL_HAS_ULTRA_LOW_POWER_WAKEUP 1
#define OPENTITAN_SYSRST_CTRL_HAS_PINOUT_KEY_INVERSION_CONTROL 1
#define OPENTITAN_SYSRST_CTRL_HAS_HARDWARE_RESET_STRETCH 1
#define OPENTITAN_SYSRST_CTRL_HAS_FLASH_WRITE_PROTECT 1
#define OPENTITAN_SYSRST_CTRL_HAS_PIN_INPUT_VALUE_ACCESS 1
 
 
 
/**
 * Get the sysrst_ctrl instance from an instance ID
 *
 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
 *
 * @param inst_id Instance ID.
 * @return A sysrst_ctrl instance.
 *
 * **Note:** This function only makes sense if the instance ID has device type sysrst_ctrl,
 * otherwise the returned value is unspecified.
 */
dt_sysrst_ctrl_t dt_sysrst_ctrl_from_instance_id(dt_instance_id_t inst_id);
 
/**
 * Get the instance ID of an instance.
 *
 * @param dt Instance of sysrst_ctrl.
 * @return The instance ID of that instance.
 */
dt_instance_id_t dt_sysrst_ctrl_instance_id(dt_sysrst_ctrl_t dt);
 
/**
 * Get the register base address of an instance.
 *
 * @param dt Instance of sysrst_ctrl.
 * @param reg_block The register block requested.
 * @return The register base address of the requested block.
 */
uint32_t dt_sysrst_ctrl_reg_block(
    dt_sysrst_ctrl_t dt,
    dt_sysrst_ctrl_reg_block_t reg_block);
 
/**
 * Get the primary register base address of an instance.
 *
 * This is just a convenience function, equivalent to
 * `dt_sysrst_ctrl_reg_block(dt, kDtSysrstCtrlRegBlockCore)`
 *
 * @param dt Instance of sysrst_ctrl.
 * @return The register base address of the primary register block.
 */
static inline uint32_t dt_sysrst_ctrl_primary_reg_block(
    dt_sysrst_ctrl_t dt) {
  return dt_sysrst_ctrl_reg_block(dt, kDtSysrstCtrlRegBlockCore);
}
 
/**
 * Get the base address of a memory.
 *
 * @param dt Instance of sysrst_ctrl.
 * @param mem The memory requested.
 * @return The base address of the requested memory.
 */
uint32_t dt_sysrst_ctrl_memory_base(
    dt_sysrst_ctrl_t dt,
    dt_sysrst_ctrl_memory_t mem);
 
/**
 * Get the size of a memory.
 *
 * @param dt Instance of sysrst_ctrl.
 * @param mem The memory requested.
 * @return The size of the requested memory.
 */
uint32_t dt_sysrst_ctrl_memory_size(
    dt_sysrst_ctrl_t dt,
    dt_sysrst_ctrl_memory_t mem);
 
/**
 * Get the PLIC ID of a sysrst_ctrl IRQ for a given instance.
 *
 * If the instance is not connected to the PLIC, this function
 * will return `kDtPlicIrqIdNone`.
 *
 * @param dt Instance of sysrst_ctrl.
 * @param irq A sysrst_ctrl IRQ.
 * @return The PLIC ID of the IRQ of this instance.
 */
dt_plic_irq_id_t dt_sysrst_ctrl_irq_to_plic_id(
    dt_sysrst_ctrl_t dt,
    dt_sysrst_ctrl_irq_t irq);
 
/**
 * Convert a global IRQ ID to a local sysrst_ctrl IRQ type.
 *
 * @param dt Instance of sysrst_ctrl.
 * @param irq A PLIC ID that belongs to this instance.
 * @return The sysrst_ctrl IRQ, or `kDtSysrstCtrlIrqCount`.
 *
 * **Note:** This function assumes that the PLIC ID belongs to the instance
 * of sysrst_ctrl passed in parameter. In other words, it must be the case that
 * `dt_sysrst_ctrl_instance_id(dt) == dt_plic_id_to_instance_id(irq)`. Otherwise, this function
 * will return `kDtSysrstCtrlIrqCount`.
 */
dt_sysrst_ctrl_irq_t dt_sysrst_ctrl_irq_from_plic_id(
    dt_sysrst_ctrl_t dt,
    dt_plic_irq_id_t irq);
 
 
/**
 * Get the alert ID of a sysrst_ctrl alert for a given instance.
 *
 * **Note:** This function only makes sense if the instance is connected to the Alert Handler. For any
 * instances where the instance is not connected, the return value is unspecified.
 *
 * @param dt Instance of sysrst_ctrl.
 * @param alert A sysrst_ctrl alert.
 * @return The Alert Handler alert ID of the alert of this instance.
 */
dt_alert_id_t dt_sysrst_ctrl_alert_to_alert_id(
    dt_sysrst_ctrl_t dt,
    dt_sysrst_ctrl_alert_t alert);
 
/**
 * Convert a global alert ID to a local sysrst_ctrl alert type.
 *
 * @param dt Instance of sysrst_ctrl.
 * @param alert A global alert ID that belongs to this instance.
 * @return The sysrst_ctrl alert, or `kDtSysrstCtrlAlertCount`.
 *
 * **Note:** This function assumes that the global alert ID belongs to the
 * instance of sysrst_ctrl passed in parameter. In other words, it must be the case
 * that `dt_sysrst_ctrl_instance_id(dt) == dt_alert_id_to_instance_id(alert)`. Otherwise,
 * this function will return `kDtSysrstCtrlAlertCount`.
 */
dt_sysrst_ctrl_alert_t dt_sysrst_ctrl_alert_from_alert_id(
    dt_sysrst_ctrl_t dt,
    dt_alert_id_t alert);
 
 
/**
 * Get the peripheral I/O description of an instance.
 *
 * @param dt Instance of sysrst_ctrl.
 * @param sig Requested peripheral I/O.
 * @return Description of the requested peripheral I/O for this instance.
 */
dt_periph_io_t dt_sysrst_ctrl_periph_io(
    dt_sysrst_ctrl_t dt,
    dt_sysrst_ctrl_periph_io_t sig);
 
/**
 * Get the clock signal connected to a clock port of an instance.
 *
 * @param dt Instance of sysrst_ctrl.
 * @param clk Clock port.
 * @return Clock signal.
 */
dt_clock_t dt_sysrst_ctrl_clock(
    dt_sysrst_ctrl_t dt,
    dt_sysrst_ctrl_clock_t clk);
 
/**
 * Get the reset signal connected to a reset port of an instance.
 *
 * @param dt Instance of sysrst_ctrl.
 * @param rst Reset port.
 * @return Reset signal.
 */
dt_reset_t dt_sysrst_ctrl_reset(
    dt_sysrst_ctrl_t dt,
    dt_sysrst_ctrl_reset_t rst);
 
 
 
#ifdef __cplusplus
}  // extern "C"
#endif  // __cplusplus
 
#endif  // OPENTITAN_DT_SYSRST_CTRL_H_