Software APIs
dt_sysrst_ctrl.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7#ifndef OPENTITAN_DT_SYSRST_CTRL_H_
8#define OPENTITAN_DT_SYSRST_CTRL_H_
9
10#ifdef __cplusplus
11extern "C" {
12#endif // __cplusplus
13
14/**
15 * @file
16 * @brief Device Tables (DT) for IP sysrst_ctrl and top earlgrey.
17 *
18 * This file contains the type definitions and global functions of the sysrst_ctrl.
19 */
20
21#include "dt_api.h"
22#include <stdint.h>
23
24
25
26/**
27 * List of instances.
28 */
29typedef enum dt_sysrst_ctrl {
30 kDtSysrstCtrlAon = 0, /**< sysrst_ctrl_aon */
31 kDtSysrstCtrlFirst = 0, /**< \internal First instance */
32 kDtSysrstCtrlCount = 1, /**< \internal Number of instances */
34
35/**
36 * List of register blocks.
37 *
38 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
39 */
41 kDtSysrstCtrlRegBlockCore = 0, /**< */
42 kDtSysrstCtrlRegBlockCount = 1, /**< \internal Number of register blocks */
44
45/** Primary register block (associated with the "primary" set of registers that control the IP). */
46static const dt_sysrst_ctrl_reg_block_t kDtSysrstCtrlRegBlockPrimary = kDtSysrstCtrlRegBlockCore;
47
48/**
49 * List of IRQs.
50 *
51 * IRQs are guaranteed to be numbered consecutively from 0.
52 */
53typedef enum dt_sysrst_ctrl_irq {
54 kDtSysrstCtrlIrqEventDetected = 0, /**< Common interrupt triggered by combo or keyboard events. */
55 kDtSysrstCtrlIrqCount = 1, /**< \internal Number of IRQs */
57
58/**
59 * List of Alerts.
60 *
61 * Alerts are guaranteed to be numbered consecutively from 0.
62 */
64 kDtSysrstCtrlAlertFatalFault = 0, /**< This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. */
65 kDtSysrstCtrlAlertCount = 1, /**< \internal Number of Alerts */
67
68/**
69 * List of clock ports.
70 *
71 * Clock ports are guaranteed to be numbered consecutively from 0.
72 */
74 kDtSysrstCtrlClockClk = 0, /**< Clock port clk_i */
75 kDtSysrstCtrlClockAon = 1, /**< Clock port clk_aon_i */
76 kDtSysrstCtrlClockCount = 2, /**< \internal Number of clock ports */
78
79/**
80 * List of reset requests.
81 *
82 * Reset requests are guaranteed to be numbered consecutively from 0.
83 */
85 kDtSysrstCtrlResetReqRstReq = 0, /**< OpenTitan reset request to `rstmgr` (running on AON clock). */
86 kDtSysrstCtrlResetReqCount = 1, /**< \internal Number of reset requests */
88
89/**
90 * List of reset ports.
91 *
92 * Reset ports are guaranteed to be numbered consecutively from 0.
93 */
95 kDtSysrstCtrlResetRst = 0, /**< Reset port rst_ni */
96 kDtSysrstCtrlResetAon = 1, /**< Reset port rst_aon_ni */
97 kDtSysrstCtrlResetCount = 2, /**< \internal Number of reset ports */
99
100/**
101 * List of peripheral I/O.
102 *
103 * Peripheral I/O are guaranteed to be numbered consecutively from 0.
104 */
106 kDtSysrstCtrlPeriphIoAcPresent = 0, /**< */
107 kDtSysrstCtrlPeriphIoKey0In = 1, /**< */
108 kDtSysrstCtrlPeriphIoKey1In = 2, /**< */
109 kDtSysrstCtrlPeriphIoKey2In = 3, /**< */
110 kDtSysrstCtrlPeriphIoPwrbIn = 4, /**< */
111 kDtSysrstCtrlPeriphIoLidOpen = 5, /**< */
112 kDtSysrstCtrlPeriphIoBatDisable = 6, /**< */
113 kDtSysrstCtrlPeriphIoKey0Out = 7, /**< */
114 kDtSysrstCtrlPeriphIoKey1Out = 8, /**< */
115 kDtSysrstCtrlPeriphIoKey2Out = 9, /**< */
116 kDtSysrstCtrlPeriphIoPwrbOut = 10, /**< */
117 kDtSysrstCtrlPeriphIoZ3Wakeup = 11, /**< */
118 kDtSysrstCtrlPeriphIoEcRstL = 12, /**< */
119 kDtSysrstCtrlPeriphIoFlashWpL = 13, /**< */
120 kDtSysrstCtrlPeriphIoCount = 14, /**< \internal Number of peripheral I/O */
122
123/**
124 * List of wakeups.
125 *
126 * Wakeups are guaranteed to be numbered consecutively from 0.
127 */
129 kDtSysrstCtrlWakeupWkupReq = 0, /**< OpenTitan wake request signal to `pwrmgr` (running on AON clock). */
130 kDtSysrstCtrlWakeupCount = 1, /**< \internal Number of wakeups */
132
133/**
134 * List of supported hardware features.
135 */
136#define OPENTITAN_SYSRST_CTRL_HAS_COMBO_DETECT 1
137#define OPENTITAN_SYSRST_CTRL_HAS_AUTO_BLOCK_KEY_OUTPUT 1
138#define OPENTITAN_SYSRST_CTRL_HAS_INPUT_TRIGGERED_INTERRUPT 1
139#define OPENTITAN_SYSRST_CTRL_HAS_ULTRA_LOW_POWER_WAKEUP 1
140#define OPENTITAN_SYSRST_CTRL_HAS_PINOUT_KEY_INVERSION_CONTROL 1
141#define OPENTITAN_SYSRST_CTRL_HAS_HARDWARE_RESET_STRETCH 1
142#define OPENTITAN_SYSRST_CTRL_HAS_FLASH_WRITE_PROTECT 1
143#define OPENTITAN_SYSRST_CTRL_HAS_PIN_INPUT_VALUE_ACCESS 1
144
145
146
147/**
148 * Get the sysrst_ctrl instance from an instance ID
149 *
150 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
151 *
152 * @param inst_id Instance ID.
153 * @return A sysrst_ctrl instance.
154 *
155 * **Note:** This function only makes sense if the instance ID has device type sysrst_ctrl,
156 * otherwise the returned value is unspecified.
157 */
159
160/**
161 * Get the instance ID of an instance.
162 *
163 * @param dt Instance of sysrst_ctrl.
164 * @return The instance ID of that instance.
165 */
167
168/**
169 * Get the register base address of an instance.
170 *
171 * @param dt Instance of sysrst_ctrl.
172 * @param reg_block The register block requested.
173 * @return The register base address of the requested block.
174 */
178
179/**
180 * Get the primary register base address of an instance.
181 *
182 * This is just a convenience function, equivalent to
183 * `dt_sysrst_ctrl_reg_block(dt, kDtSysrstCtrlRegBlockCore)`
184 *
185 * @param dt Instance of sysrst_ctrl.
186 * @return The register base address of the primary register block.
187 */
188static inline uint32_t dt_sysrst_ctrl_primary_reg_block(
189 dt_sysrst_ctrl_t dt) {
190 return dt_sysrst_ctrl_reg_block(dt, kDtSysrstCtrlRegBlockCore);
191}
192
193/**
194 * Get the PLIC ID of a sysrst_ctrl IRQ for a given instance.
195 *
196 * If the instance is not connected to the PLIC, this function
197 * will return `kDtPlicIrqIdNone`.
198 *
199 * @param dt Instance of sysrst_ctrl.
200 * @param irq A sysrst_ctrl IRQ.
201 * @return The PLIC ID of the IRQ of this instance.
202 */
206
207/**
208 * Convert a global IRQ ID to a local sysrst_ctrl IRQ type.
209 *
210 * @param dt Instance of sysrst_ctrl.
211 * @param irq A PLIC ID that belongs to this instance.
212 * @return The sysrst_ctrl IRQ, or `kDtSysrstCtrlIrqCount`.
213 *
214 * **Note:** This function assumes that the PLIC ID belongs to the instance
215 * of sysrst_ctrl passed in parameter. In other words, it must be the case that
216 * `dt_sysrst_ctrl_instance_id(dt) == dt_plic_id_to_instance_id(irq)`. Otherwise, this function
217 * will return `kDtSysrstCtrlIrqCount`.
218 */
221 dt_plic_irq_id_t irq);
222
223
224/**
225 * Get the alert ID of a sysrst_ctrl alert for a given instance.
226 *
227 * **Note:** This function only makes sense if the instance is connected to the Alert Handler. For any
228 * instances where the instance is not connected, the return value is unspecified.
229 *
230 * @param dt Instance of sysrst_ctrl.
231 * @param alert A sysrst_ctrl alert.
232 * @return The Alert Handler alert ID of the alert of this instance.
233 */
237
238/**
239 * Convert a global alert ID to a local sysrst_ctrl alert type.
240 *
241 * @param dt Instance of sysrst_ctrl.
242 * @param alert A global alert ID that belongs to this instance.
243 * @return The sysrst_ctrl alert, or `kDtSysrstCtrlAlertCount`.
244 *
245 * **Note:** This function assumes that the global alert ID belongs to the
246 * instance of sysrst_ctrl passed in parameter. In other words, it must be the case
247 * that `dt_sysrst_ctrl_instance_id(dt) == dt_alert_id_to_instance_id(alert)`. Otherwise,
248 * this function will return `kDtSysrstCtrlAlertCount`.
249 */
252 dt_alert_id_t alert);
253
254
255/**
256 * Get the peripheral I/O description of an instance.
257 *
258 * @param dt Instance of sysrst_ctrl.
259 * @param sig Requested peripheral I/O.
260 * @return Description of the requested peripheral I/O for this instance.
261 */
265
266/**
267 * Get the clock signal connected to a clock port of an instance.
268 *
269 * @param dt Instance of sysrst_ctrl.
270 * @param clk Clock port.
271 * @return Clock signal.
272 */
276
277/**
278 * Get the reset signal connected to a reset port of an instance.
279 *
280 * @param dt Instance of sysrst_ctrl.
281 * @param rst Reset port.
282 * @return Reset signal.
283 */
287
288
289
290#ifdef __cplusplus
291} // extern "C"
292#endif // __cplusplus
293
294#endif // OPENTITAN_DT_SYSRST_CTRL_H_