Software APIs
dt_sysrst_ctrl.h
Go to the documentation of this file.
1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4//
5// Device table API auto-generated by `dtgen`
6
7#ifndef OPENTITAN_DT_SYSRST_CTRL_H_
8#define OPENTITAN_DT_SYSRST_CTRL_H_
9
10/**
11 * @file
12 * @brief Device Tables (DT) for IP sysrst_ctrl and top earlgrey.
13 *
14 * This file contains the type definitions and global functions of the sysrst_ctrl.
15 */
16
17#include "dt_api.h"
18#include <stdint.h>
19
20
21
22/**
23 * List of instances.
24 */
25typedef enum dt_sysrst_ctrl {
26 kDtSysrstCtrlAon = 0, /**< sysrst_ctrl_aon */
27 kDtSysrstCtrlFirst = 0, /**< \internal First instance */
28 kDtSysrstCtrlCount = 1, /**< \internal Number of instances */
30
31/**
32 * List of register blocks.
33 *
34 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
35 */
37 kDtSysrstCtrlRegBlockCore = 0, /**< */
38 kDtSysrstCtrlRegBlockCount = 1, /**< \internal Number of register blocks */
40
41/** Primary register block (associated with the "primary" set of registers that control the IP). */
42static const dt_sysrst_ctrl_reg_block_t kDtSysrstCtrlRegBlockPrimary = kDtSysrstCtrlRegBlockCore;
43
44/**
45 * List of IRQs.
46 *
47 * IRQs are guaranteed to be numbered consecutively from 0.
48 */
49typedef enum dt_sysrst_ctrl_irq {
50 kDtSysrstCtrlIrqEventDetected = 0, /**< Common interrupt triggered by combo or keyboard events. */
51 kDtSysrstCtrlIrqCount = 1, /**< \internal Number of IRQs */
53
54/**
55 * List of Alerts.
56 *
57 * Alerts are guaranteed to be numbered consecutively from 0.
58 */
60 kDtSysrstCtrlAlertFatalFault = 0, /**< This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. */
61 kDtSysrstCtrlAlertCount = 1, /**< \internal Number of Alerts */
63
64/**
65 * List of clock ports.
66 *
67 * Clock ports are guaranteed to be numbered consecutively from 0.
68 */
70 kDtSysrstCtrlClockClk = 0, /**< Clock port clk_i */
71 kDtSysrstCtrlClockAon = 1, /**< Clock port clk_aon_i */
72 kDtSysrstCtrlClockCount = 2, /**< \internal Number of clock ports */
74
75/**
76 * List of reset requests.
77 *
78 * Reset requests are guaranteed to be numbered consecutively from 0.
79 */
81 kDtSysrstCtrlResetReqRstReq = 0, /**< OpenTitan reset request to `rstmgr` (running on AON clock). */
82 kDtSysrstCtrlResetReqCount = 1, /**< \internal Number of reset requests */
84
85/**
86 * List of reset ports.
87 *
88 * Reset ports are guaranteed to be numbered consecutively from 0.
89 */
91 kDtSysrstCtrlResetRst = 0, /**< Reset port rst_ni */
92 kDtSysrstCtrlResetAon = 1, /**< Reset port rst_aon_ni */
93 kDtSysrstCtrlResetCount = 2, /**< \internal Number of reset ports */
95
96/**
97 * List of peripheral I/O.
98 *
99 * Peripheral I/O are guaranteed to be numbered consecutively from 0.
100 */
102 kDtSysrstCtrlPeriphIoAcPresent = 0, /**< */
103 kDtSysrstCtrlPeriphIoKey0In = 1, /**< */
104 kDtSysrstCtrlPeriphIoKey1In = 2, /**< */
105 kDtSysrstCtrlPeriphIoKey2In = 3, /**< */
106 kDtSysrstCtrlPeriphIoPwrbIn = 4, /**< */
107 kDtSysrstCtrlPeriphIoLidOpen = 5, /**< */
108 kDtSysrstCtrlPeriphIoBatDisable = 6, /**< */
109 kDtSysrstCtrlPeriphIoKey0Out = 7, /**< */
110 kDtSysrstCtrlPeriphIoKey1Out = 8, /**< */
111 kDtSysrstCtrlPeriphIoKey2Out = 9, /**< */
112 kDtSysrstCtrlPeriphIoPwrbOut = 10, /**< */
113 kDtSysrstCtrlPeriphIoZ3Wakeup = 11, /**< */
114 kDtSysrstCtrlPeriphIoEcRstL = 12, /**< */
115 kDtSysrstCtrlPeriphIoFlashWpL = 13, /**< */
116 kDtSysrstCtrlPeriphIoCount = 14, /**< \internal Number of peripheral I/O */
118
119/**
120 * List of wakeups.
121 *
122 * Wakeups are guaranteed to be numbered consecutively from 0.
123 */
125 kDtSysrstCtrlWakeupWkupReq = 0, /**< OpenTitan wake request signal to `pwrmgr` (running on AON clock). */
126 kDtSysrstCtrlWakeupCount = 1, /**< \internal Number of wakeups */
128
129/**
130 * List of supported hardware features.
131 */
132#define OPENTITAN_SYSRST_CTRL_HAS_COMBO_DETECT 1
133#define OPENTITAN_SYSRST_CTRL_HAS_AUTO_BLOCK_KEY_OUTPUT 1
134#define OPENTITAN_SYSRST_CTRL_HAS_INPUT_TRIGGERED_INTERRUPT 1
135#define OPENTITAN_SYSRST_CTRL_HAS_ULTRA_LOW_POWER_WAKEUP 1
136#define OPENTITAN_SYSRST_CTRL_HAS_PINOUT_KEY_INVERSION_CONTROL 1
137#define OPENTITAN_SYSRST_CTRL_HAS_HARDWARE_RESET_STRETCH 1
138#define OPENTITAN_SYSRST_CTRL_HAS_FLASH_WRITE_PROTECT 1
139#define OPENTITAN_SYSRST_CTRL_HAS_PIN_INPUT_VALUE_ACCESS 1
140
141
142
143/**
144 * Get the sysrst_ctrl instance from an instance ID
145 *
146 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
147 *
148 * @param inst_id Instance ID.
149 * @return A sysrst_ctrl instance.
150 *
151 * **Note:** This function only makes sense if the instance ID has device type sysrst_ctrl,
152 * otherwise the returned value is unspecified.
153 */
155
156/**
157 * Get the instance ID of an instance.
158 *
159 * @param dt Instance of sysrst_ctrl.
160 * @return The instance ID of that instance.
161 */
163
164/**
165 * Get the register base address of an instance.
166 *
167 * @param dt Instance of sysrst_ctrl.
168 * @param reg_block The register block requested.
169 * @return The register base address of the requested block.
170 */
174
175/**
176 * Get the primary register base address of an instance.
177 *
178 * This is just a convenience function, equivalent to
179 * `dt_sysrst_ctrl_reg_block(dt, kDtSysrstCtrlRegBlockCore)`
180 *
181 * @param dt Instance of sysrst_ctrl.
182 * @return The register base address of the primary register block.
183 */
184static inline uint32_t dt_sysrst_ctrl_primary_reg_block(
185 dt_sysrst_ctrl_t dt) {
186 return dt_sysrst_ctrl_reg_block(dt, kDtSysrstCtrlRegBlockCore);
187}
188
189/**
190 * Get the PLIC ID of a sysrst_ctrl IRQ for a given instance.
191 *
192 * If the instance is not connected to the PLIC, this function
193 * will return `kDtPlicIrqIdNone`.
194 *
195 * @param dt Instance of sysrst_ctrl.
196 * @param irq A sysrst_ctrl IRQ.
197 * @return The PLIC ID of the IRQ of this instance.
198 */
202
203/**
204 * Convert a global IRQ ID to a local sysrst_ctrl IRQ type.
205 *
206 * @param dt Instance of sysrst_ctrl.
207 * @param irq A PLIC ID that belongs to this instance.
208 * @return The sysrst_ctrl IRQ, or `kDtSysrstCtrlIrqCount`.
209 *
210 * **Note:** This function assumes that the PLIC ID belongs to the instance
211 * of sysrst_ctrl passed in parameter. In other words, it must be the case that
212 * `dt_sysrst_ctrl_instance_id(dt) == dt_plic_id_to_instance_id(irq)`. Otherwise, this function
213 * will return `kDtSysrstCtrlIrqCount`.
214 */
217 dt_plic_irq_id_t irq);
218
219
220/**
221 * Get the alert ID of a sysrst_ctrl alert for a given instance.
222 *
223 * **Note:** This function only makes sense if the instance is connected to the Alert Handler. For any
224 * instances where the instance is not connected, the return value is unspecified.
225 *
226 * @param dt Instance of sysrst_ctrl.
227 * @param alert A sysrst_ctrl alert.
228 * @return The Alert Handler alert ID of the alert of this instance.
229 */
233
234/**
235 * Convert a global alert ID to a local sysrst_ctrl alert type.
236 *
237 * @param dt Instance of sysrst_ctrl.
238 * @param alert A global alert ID that belongs to this instance.
239 * @return The sysrst_ctrl alert, or `kDtSysrstCtrlAlertCount`.
240 *
241 * **Note:** This function assumes that the global alert ID belongs to the
242 * instance of sysrst_ctrl passed in parameter. In other words, it must be the case
243 * that `dt_sysrst_ctrl_instance_id(dt) == dt_alert_id_to_instance_id(alert)`. Otherwise,
244 * this function will return `kDtSysrstCtrlAlertCount`.
245 */
248 dt_alert_id_t alert);
249
250
251/**
252 * Get the peripheral I/O description of an instance.
253 *
254 * @param dt Instance of sysrst_ctrl.
255 * @param sig Requested peripheral I/O.
256 * @return Description of the requested peripheral I/O for this instance.
257 */
261
262/**
263 * Get the clock signal connected to a clock port of an instance.
264 *
265 * @param dt Instance of sysrst_ctrl.
266 * @param clk Clock port.
267 * @return Clock signal.
268 */
272
273/**
274 * Get the reset signal connected to a reset port of an instance.
275 *
276 * @param dt Instance of sysrst_ctrl.
277 * @param rst Reset port.
278 * @return Reset signal.
279 */
283
284
285
286#endif // OPENTITAN_DT_SYSRST_CTRL_H_