dt_soc_dbg_ctrl.h

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// Copyright lowRISC contributors (OpenTitan project).
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Device table API auto-generated by `dtgen`
 
#ifndef OPENTITAN_DT_SOC_DBG_CTRL_H_
#define OPENTITAN_DT_SOC_DBG_CTRL_H_
 
#ifdef __cplusplus
extern "C" {
#endif  // __cplusplus
 
/**
 * @file
 * @brief Device Tables (DT) for IP soc_dbg_ctrl and top darjeeling.
 *
 * This file contains the type definitions and global functions of the soc_dbg_ctrl.
 */
 
#include "hw/top/dt/dt_api.h"
#include <stdint.h>
 
 
 
/**
 * List of instances.
 */
typedef enum dt_soc_dbg_ctrl {
  kDtSocDbgCtrl = 0, /**< soc_dbg_ctrl */
  kDtSocDbgCtrlFirst = 0, /**< \internal First instance */
  kDtSocDbgCtrlCount = 1, /**< \internal Number of instances */
} dt_soc_dbg_ctrl_t;
 
/**
 * List of register blocks.
 *
 * Register blocks are guaranteed to start at 0 and to be consecutively numbered.
 */
typedef enum dt_soc_dbg_ctrl_reg_block {
  kDtSocDbgCtrlRegBlockCore = 0, /**<  */
  kDtSocDbgCtrlRegBlockJtag = 1, /**<  */
  kDtSocDbgCtrlRegBlockCount = 2, /**< \internal Number of register blocks */
} dt_soc_dbg_ctrl_reg_block_t;
 
/**
 * List of memories.
 *
 * Memories are guaranteed to start at 0 and to be consecutively numbered.
 */
typedef enum dt_soc_dbg_ctrl_memory {
  kDtSocDbgCtrlMemoryCount = 0, /**< \internal Number of memories */
} dt_soc_dbg_ctrl_memory_t;
 
/** Primary register block (associated with the "primary" set of registers that control the IP). */
static const dt_soc_dbg_ctrl_reg_block_t kDtSocDbgCtrlRegBlockPrimary = kDtSocDbgCtrlRegBlockCore;
 
/**
 * List of Alerts.
 *
 * Alerts are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_soc_dbg_ctrl_alert {
  kDtSocDbgCtrlAlertFatalFault = 0, /**< This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. */
  kDtSocDbgCtrlAlertRecovCtrlUpdateErr = 1, /**< This recoverable alert is triggered upon detecting an update error in the shadowed Control Register. */
  kDtSocDbgCtrlAlertCount = 2, /**< \internal Number of Alerts */
} dt_soc_dbg_ctrl_alert_t;
 
/**
 * List of clock ports.
 *
 * Clock ports are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_soc_dbg_ctrl_clock {
  kDtSocDbgCtrlClockClk = 0, /**< Clock port clk_i */
  kDtSocDbgCtrlClockCount = 1, /**< \internal Number of clock ports */
} dt_soc_dbg_ctrl_clock_t;
 
/**
 * List of reset ports.
 *
 * Reset ports are guaranteed to be numbered consecutively from 0.
 */
typedef enum dt_soc_dbg_ctrl_reset {
  kDtSocDbgCtrlResetRst = 0, /**< Reset port rst_ni */
  kDtSocDbgCtrlResetCount = 1, /**< \internal Number of reset ports */
} dt_soc_dbg_ctrl_reset_t;
 
 
/**
 * Get the soc_dbg_ctrl instance from an instance ID
 *
 * For example, `dt_uart_from_instance_id(kDtInstanceIdUart3) == kDtUart3`.
 *
 * @param inst_id Instance ID.
 * @return A soc_dbg_ctrl instance.
 *
 * **Note:** This function only makes sense if the instance ID has device type soc_dbg_ctrl,
 * otherwise the returned value is unspecified.
 */
dt_soc_dbg_ctrl_t dt_soc_dbg_ctrl_from_instance_id(dt_instance_id_t inst_id);
 
/**
 * Get the instance ID of an instance.
 *
 * @param dt Instance of soc_dbg_ctrl.
 * @return The instance ID of that instance.
 */
dt_instance_id_t dt_soc_dbg_ctrl_instance_id(dt_soc_dbg_ctrl_t dt);
 
/**
 * Get the register base address of an instance.
 *
 * @param dt Instance of soc_dbg_ctrl.
 * @param reg_block The register block requested.
 * @return The register base address of the requested block.
 */
uint32_t dt_soc_dbg_ctrl_reg_block(
    dt_soc_dbg_ctrl_t dt,
    dt_soc_dbg_ctrl_reg_block_t reg_block);
 
/**
 * Get the primary register base address of an instance.
 *
 * This is just a convenience function, equivalent to
 * `dt_soc_dbg_ctrl_reg_block(dt, kDtSocDbgCtrlRegBlockCore)`
 *
 * @param dt Instance of soc_dbg_ctrl.
 * @return The register base address of the primary register block.
 */
static inline uint32_t dt_soc_dbg_ctrl_primary_reg_block(
    dt_soc_dbg_ctrl_t dt) {
  return dt_soc_dbg_ctrl_reg_block(dt, kDtSocDbgCtrlRegBlockCore);
}
 
/**
 * Get the base address of a memory.
 *
 * @param dt Instance of soc_dbg_ctrl.
 * @param mem The memory requested.
 * @return The base address of the requested memory.
 */
uint32_t dt_soc_dbg_ctrl_memory_base(
    dt_soc_dbg_ctrl_t dt,
    dt_soc_dbg_ctrl_memory_t mem);
 
/**
 * Get the size of a memory.
 *
 * @param dt Instance of soc_dbg_ctrl.
 * @param mem The memory requested.
 * @return The size of the requested memory.
 */
uint32_t dt_soc_dbg_ctrl_memory_size(
    dt_soc_dbg_ctrl_t dt,
    dt_soc_dbg_ctrl_memory_t mem);
 
 
/**
 * Get the alert ID of a soc_dbg_ctrl alert for a given instance.
 *
 * **Note:** This function only makes sense if the instance is connected to the Alert Handler. For any
 * instances where the instance is not connected, the return value is unspecified.
 *
 * @param dt Instance of soc_dbg_ctrl.
 * @param alert A soc_dbg_ctrl alert.
 * @return The Alert Handler alert ID of the alert of this instance.
 */
dt_alert_id_t dt_soc_dbg_ctrl_alert_to_alert_id(
    dt_soc_dbg_ctrl_t dt,
    dt_soc_dbg_ctrl_alert_t alert);
 
/**
 * Convert a global alert ID to a local soc_dbg_ctrl alert type.
 *
 * @param dt Instance of soc_dbg_ctrl.
 * @param alert A global alert ID that belongs to this instance.
 * @return The soc_dbg_ctrl alert, or `kDtSocDbgCtrlAlertCount`.
 *
 * **Note:** This function assumes that the global alert ID belongs to the
 * instance of soc_dbg_ctrl passed in parameter. In other words, it must be the case
 * that `dt_soc_dbg_ctrl_instance_id(dt) == dt_alert_id_to_instance_id(alert)`. Otherwise,
 * this function will return `kDtSocDbgCtrlAlertCount`.
 */
dt_soc_dbg_ctrl_alert_t dt_soc_dbg_ctrl_alert_from_alert_id(
    dt_soc_dbg_ctrl_t dt,
    dt_alert_id_t alert);
 
 
 
/**
 * Get the clock signal connected to a clock port of an instance.
 *
 * @param dt Instance of soc_dbg_ctrl.
 * @param clk Clock port.
 * @return Clock signal.
 */
dt_clock_t dt_soc_dbg_ctrl_clock(
    dt_soc_dbg_ctrl_t dt,
    dt_soc_dbg_ctrl_clock_t clk);
 
/**
 * Get the reset signal connected to a reset port of an instance.
 *
 * @param dt Instance of soc_dbg_ctrl.
 * @param rst Reset port.
 * @return Reset signal.
 */
dt_reset_t dt_soc_dbg_ctrl_reset(
    dt_soc_dbg_ctrl_t dt,
    dt_soc_dbg_ctrl_reset_t rst);
 
 
 
#ifdef __cplusplus
}  // extern "C"
#endif  // __cplusplus
 
#endif  // OPENTITAN_DT_SOC_DBG_CTRL_H_