Software APIs
dif_usbdev_unittest.cc
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 #include "sw/device/lib/dif/dif_usbdev.h"
6 
7 #include "gtest/gtest.h"
8 #include "sw/device/lib/base/mmio.h"
9 #include "sw/device/lib/base/mock_mmio.h"
10 #include "sw/device/lib/base/multibits.h"
11 #include "sw/device/lib/dif/dif_base.h"
12 #include "sw/device/lib/dif/dif_test_base.h"
13 
14 #include "usbdev_regs.h" // Generated.
15 
16 namespace dif_usbdev_unittest {
17 namespace {
18 using mock_mmio::MmioTest;
19 using mock_mmio::MockDevice;
20 using testing::Test;
21 
22 class UsbdevTest : public Test, public MmioTest {
23  protected:
24  dif_usbdev_t usbdev_ = {
25  .base_addr = dev().region(),
26  };
27 };
28 
29 TEST_F(UsbdevTest, NullArgsTest) {
30  dif_usbdev_config_t config;
31  dif_usbdev_buffer_pool_t buffer_pool;
32  bool bool_arg, bool_arg2;
33  dif_usbdev_rx_packet_info_t packet_info;
34  dif_usbdev_buffer_t buffer;
35  uint8_t uint8_arg, uint8_arg2;
36  size_t size_arg;
37  dif_usbdev_endpoint_id_t endpoint_id;
38  dif_usbdev_tx_status_t tx_status;
39  uint16_t uint16_arg;
40  dif_usbdev_link_state_t link_state;
41  dif_usbdev_wake_status_t wake_status;
42  dif_usbdev_phy_pins_sense_t phy_pins_status;
43  dif_usbdev_phy_pins_drive_t phy_pins_drive;
44 
45  EXPECT_DIF_BADARG(dif_usbdev_configure(nullptr, &buffer_pool, config));
46  EXPECT_DIF_BADARG(dif_usbdev_configure(&usbdev_, nullptr, config));
47  EXPECT_DIF_BADARG(dif_usbdev_fill_available_fifos(nullptr, &buffer_pool));
48  EXPECT_DIF_BADARG(dif_usbdev_fill_available_fifos(&usbdev_, nullptr));
49  EXPECT_DIF_BADARG(dif_usbdev_endpoint_setup_enable(nullptr, /*endpoint=*/0,
50  kDifToggleEnabled));
51  EXPECT_DIF_BADARG(dif_usbdev_endpoint_out_enable(nullptr, /*endpoint=*/0,
52  kDifToggleEnabled));
53  EXPECT_DIF_BADARG(dif_usbdev_endpoint_set_nak_out_enable(
54  nullptr, /*endpoint=*/0, kDifToggleEnabled));
55  EXPECT_DIF_BADARG(dif_usbdev_endpoint_stall_enable(nullptr, endpoint_id,
56  kDifToggleEnabled));
57  EXPECT_DIF_BADARG(
58  dif_usbdev_endpoint_stall_get(nullptr, endpoint_id, &bool_arg));
59  EXPECT_DIF_BADARG(
60  dif_usbdev_endpoint_stall_get(&usbdev_, endpoint_id, nullptr));
61  EXPECT_DIF_BADARG(
62  dif_usbdev_endpoint_iso_enable(nullptr, endpoint_id, kDifToggleEnabled));
63  EXPECT_DIF_BADARG(
64  dif_usbdev_endpoint_enable(nullptr, endpoint_id, kDifToggleEnabled));
65  EXPECT_DIF_BADARG(dif_usbdev_interface_enable(nullptr, kDifToggleEnabled));
66  EXPECT_DIF_BADARG(dif_usbdev_recv(nullptr, &packet_info, &buffer));
67  EXPECT_DIF_BADARG(dif_usbdev_recv(&usbdev_, nullptr, &buffer));
68  EXPECT_DIF_BADARG(dif_usbdev_recv(&usbdev_, &packet_info, nullptr));
69  EXPECT_DIF_BADARG(dif_usbdev_buffer_read(
70  nullptr, &buffer_pool, &buffer, &uint8_arg, /*dst_len=*/1, &size_arg));
71  EXPECT_DIF_BADARG(dif_usbdev_buffer_read(
72  &usbdev_, nullptr, &buffer, &uint8_arg, /*dst_len=*/1, &size_arg));
73  EXPECT_DIF_BADARG(dif_usbdev_buffer_read(
74  &usbdev_, &buffer_pool, nullptr, &uint8_arg, /*dst_len=*/1, &size_arg));
75  EXPECT_DIF_BADARG(dif_usbdev_buffer_read(&usbdev_, &buffer_pool, &buffer,
76  nullptr, /*dst_len=*/1, &size_arg));
77  EXPECT_DIF_BADARG(dif_usbdev_buffer_read(&usbdev_, &buffer_pool, &buffer,
78  &uint8_arg, /*dst_len=*/1, nullptr));
79  EXPECT_DIF_BADARG(dif_usbdev_buffer_return(nullptr, &buffer_pool, &buffer));
80  EXPECT_DIF_BADARG(dif_usbdev_buffer_return(&usbdev_, nullptr, &buffer));
81  EXPECT_DIF_BADARG(dif_usbdev_buffer_return(&usbdev_, &buffer_pool, nullptr));
82  EXPECT_DIF_BADARG(dif_usbdev_buffer_request(nullptr, &buffer_pool, &buffer));
83  EXPECT_DIF_BADARG(dif_usbdev_buffer_request(&usbdev_, nullptr, &buffer));
84  EXPECT_DIF_BADARG(dif_usbdev_buffer_request(&usbdev_, &buffer_pool, nullptr));
85  EXPECT_DIF_BADARG(dif_usbdev_buffer_write(nullptr, &buffer, &uint8_arg,
86  /*src_len=*/1, &size_arg));
87  EXPECT_DIF_BADARG(dif_usbdev_buffer_write(&usbdev_, nullptr, &uint8_arg,
88  /*src_len=*/1, &size_arg));
89  EXPECT_DIF_BADARG(dif_usbdev_buffer_write(&usbdev_, &buffer, nullptr,
90  /*src_len=*/1, &size_arg));
91  EXPECT_DIF_BADARG(dif_usbdev_buffer_write(&usbdev_, &buffer, &uint8_arg,
92  /*src_len=*/1, nullptr));
93  EXPECT_DIF_BADARG(dif_usbdev_send(nullptr, /*endpoint=*/0, &buffer));
94  EXPECT_DIF_BADARG(dif_usbdev_send(&usbdev_, /*endpoint=*/0, nullptr));
95  EXPECT_DIF_BADARG(dif_usbdev_get_tx_sent(nullptr, &uint16_arg));
96  EXPECT_DIF_BADARG(dif_usbdev_get_tx_sent(&usbdev_, nullptr));
97  EXPECT_DIF_BADARG(
98  dif_usbdev_clear_tx_status(nullptr, &buffer_pool, /*endpoint=*/0));
99  EXPECT_DIF_BADARG(
100  dif_usbdev_clear_tx_status(&usbdev_, nullptr, /*endpoint=*/0));
101  EXPECT_DIF_BADARG(
102  dif_usbdev_get_tx_status(nullptr, /*endpoint=*/0, &tx_status));
103  EXPECT_DIF_BADARG(
104  dif_usbdev_get_tx_status(&usbdev_, /*endpoint=*/0, nullptr));
105  EXPECT_DIF_BADARG(dif_usbdev_address_set(nullptr, /*addr=*/1));
106  EXPECT_DIF_BADARG(dif_usbdev_address_get(nullptr, &uint8_arg));
107  EXPECT_DIF_BADARG(dif_usbdev_address_get(&usbdev_, nullptr));
108  EXPECT_DIF_BADARG(dif_usbdev_clear_data_toggle(nullptr, /*endpoint=*/1));
109  EXPECT_DIF_BADARG(dif_usbdev_status_get_frame(nullptr, &uint16_arg));
110  EXPECT_DIF_BADARG(dif_usbdev_status_get_frame(&usbdev_, nullptr));
111  EXPECT_DIF_BADARG(dif_usbdev_status_get_host_lost(nullptr, &bool_arg));
112  EXPECT_DIF_BADARG(dif_usbdev_status_get_host_lost(&usbdev_, nullptr));
113  EXPECT_DIF_BADARG(dif_usbdev_status_get_link_state(nullptr, &link_state));
114  EXPECT_DIF_BADARG(dif_usbdev_status_get_link_state(&usbdev_, nullptr));
115  EXPECT_DIF_BADARG(dif_usbdev_status_get_sense(nullptr, &bool_arg));
116  EXPECT_DIF_BADARG(dif_usbdev_status_get_sense(&usbdev_, nullptr));
117  EXPECT_DIF_BADARG(dif_usbdev_status_get_available_fifo_depths(
118  nullptr, &uint8_arg, &uint8_arg2));
119  EXPECT_DIF_BADARG(dif_usbdev_status_get_available_fifo_depths(
120  &usbdev_, nullptr, &uint8_arg));
121  EXPECT_DIF_BADARG(dif_usbdev_status_get_available_fifo_depths(
122  &usbdev_, &uint8_arg, nullptr));
123  EXPECT_DIF_BADARG(dif_usbdev_status_get_available_fifo_full(
124  nullptr, &bool_arg, &bool_arg2));
125  EXPECT_DIF_BADARG(
126  dif_usbdev_status_get_available_fifo_full(&usbdev_, nullptr, &bool_arg));
127  EXPECT_DIF_BADARG(
128  dif_usbdev_status_get_available_fifo_full(&usbdev_, &bool_arg, nullptr));
129  EXPECT_DIF_BADARG(dif_usbdev_status_get_rx_fifo_depth(nullptr, &uint8_arg));
130  EXPECT_DIF_BADARG(dif_usbdev_status_get_rx_fifo_depth(&usbdev_, nullptr));
131  EXPECT_DIF_BADARG(dif_usbdev_status_get_rx_fifo_empty(nullptr, &bool_arg));
132  EXPECT_DIF_BADARG(dif_usbdev_status_get_rx_fifo_empty(&usbdev_, nullptr));
133  EXPECT_DIF_BADARG(dif_usbdev_set_osc_test_mode(nullptr, kDifToggleEnabled));
134  EXPECT_DIF_BADARG(dif_usbdev_set_wake_enable(nullptr, kDifToggleEnabled));
135  EXPECT_DIF_BADARG(dif_usbdev_get_wake_status(nullptr, &wake_status));
136  EXPECT_DIF_BADARG(dif_usbdev_get_wake_status(&usbdev_, nullptr));
137  EXPECT_DIF_BADARG(dif_usbdev_resume_link_to_active(nullptr));
138  EXPECT_DIF_BADARG(dif_usbdev_get_phy_pins_status(nullptr, &phy_pins_status));
139  EXPECT_DIF_BADARG(dif_usbdev_get_phy_pins_status(&usbdev_, nullptr));
140  EXPECT_DIF_BADARG(dif_usbdev_set_phy_pins_state(nullptr, kDifToggleEnabled,
141  phy_pins_drive));
142 }
143 
144 TEST_F(UsbdevTest, PhyConfig) {
145  dif_usbdev_buffer_pool_t buffer_pool;
146  dif_usbdev_config_t phy_config = {
147  .have_differential_receiver = kDifToggleEnabled,
148  .use_tx_d_se0 = kDifToggleDisabled,
149  .single_bit_eop = kDifToggleDisabled,
150  .pin_flip = kDifToggleEnabled,
151  .clock_sync_signals = kDifToggleEnabled,
152  };
153  EXPECT_WRITE32(USBDEV_PHY_CONFIG_REG_OFFSET,
154  {
155  {USBDEV_PHY_CONFIG_USE_DIFF_RCVR_BIT, 1},
156  {USBDEV_PHY_CONFIG_TX_USE_D_SE0_BIT, 0},
157  {USBDEV_PHY_CONFIG_EOP_SINGLE_BIT_BIT, 0},
158  {USBDEV_PHY_CONFIG_PINFLIP_BIT, 1},
159  {USBDEV_PHY_CONFIG_USB_REF_DISABLE_BIT, 0},
160  });
161  EXPECT_DIF_OK(dif_usbdev_configure(&usbdev_, &buffer_pool, phy_config));
162 
163  dif_usbdev_phy_pins_sense_t phy_pins_status;
164  EXPECT_READ32(USBDEV_PHY_PINS_SENSE_REG_OFFSET,
165  {
166  {USBDEV_PHY_PINS_SENSE_RX_DP_I_BIT, 1},
167  {USBDEV_PHY_PINS_SENSE_RX_DN_I_BIT, 0},
168  {USBDEV_PHY_PINS_SENSE_RX_D_I_BIT, 1},
169  {USBDEV_PHY_PINS_SENSE_TX_DP_O_BIT, 0},
170  {USBDEV_PHY_PINS_SENSE_TX_DN_O_BIT, 1},
171  {USBDEV_PHY_PINS_SENSE_TX_D_O_BIT, 0},
172  {USBDEV_PHY_PINS_SENSE_TX_SE0_O_BIT, 0},
173  {USBDEV_PHY_PINS_SENSE_TX_OE_O_BIT, 1},
174  {USBDEV_PHY_PINS_SENSE_PWR_SENSE_BIT, 1},
175  });
176  EXPECT_DIF_OK(dif_usbdev_get_phy_pins_status(&usbdev_, &phy_pins_status));
177  EXPECT_TRUE(phy_pins_status.rx_dp);
178  EXPECT_FALSE(phy_pins_status.rx_dn);
179  EXPECT_TRUE(phy_pins_status.rx_d);
180  EXPECT_FALSE(phy_pins_status.tx_dp);
181  EXPECT_TRUE(phy_pins_status.tx_dn);
182  EXPECT_FALSE(phy_pins_status.tx_d);
183  EXPECT_FALSE(phy_pins_status.tx_se0);
184  EXPECT_TRUE(phy_pins_status.output_enable);
185  EXPECT_TRUE(phy_pins_status.vbus_sense);
186 
187  dif_usbdev_phy_pins_drive_t overrides = {
188  .dp = 0,
189  .dn = 1,
190  .data = 0,
191  .se0 = 1,
192  .output_enable = 1,
193  .diff_receiver_enable = 0,
194  .dp_pullup_en = 1,
195  .dn_pullup_en = 0,
196  };
197  EXPECT_WRITE32(
198  USBDEV_PHY_PINS_DRIVE_REG_OFFSET,
199  {
200  {USBDEV_PHY_PINS_DRIVE_DP_O_BIT, overrides.dp},
201  {USBDEV_PHY_PINS_DRIVE_DN_O_BIT, overrides.dn},
202  {USBDEV_PHY_PINS_DRIVE_D_O_BIT, overrides.data},
203  {USBDEV_PHY_PINS_DRIVE_SE0_O_BIT, overrides.se0},
204  {USBDEV_PHY_PINS_DRIVE_OE_O_BIT, overrides.output_enable},
205  {USBDEV_PHY_PINS_DRIVE_RX_ENABLE_O_BIT,
206  overrides.diff_receiver_enable},
207  {USBDEV_PHY_PINS_DRIVE_DP_PULLUP_EN_O_BIT, overrides.dp_pullup_en},
208  {USBDEV_PHY_PINS_DRIVE_DN_PULLUP_EN_O_BIT, overrides.dn_pullup_en},
209  {USBDEV_PHY_PINS_DRIVE_EN_BIT, 1},
210  });
211  EXPECT_DIF_OK(
212  dif_usbdev_set_phy_pins_state(&usbdev_, kDifToggleEnabled, overrides));
213 
214  EXPECT_WRITE32(USBDEV_PHY_PINS_DRIVE_REG_OFFSET, 0);
215  EXPECT_DIF_OK(
216  dif_usbdev_set_phy_pins_state(&usbdev_, kDifToggleDisabled, overrides));
217 
218  EXPECT_READ32(USBDEV_PHY_CONFIG_REG_OFFSET,
219  {
220  {USBDEV_PHY_CONFIG_USE_DIFF_RCVR_BIT, 1},
221  {USBDEV_PHY_CONFIG_TX_USE_D_SE0_BIT, 0},
222  {USBDEV_PHY_CONFIG_EOP_SINGLE_BIT_BIT, 0},
223  {USBDEV_PHY_CONFIG_PINFLIP_BIT, 1},
224  {USBDEV_PHY_CONFIG_USB_REF_DISABLE_BIT, 0},
225  {USBDEV_PHY_CONFIG_TX_OSC_TEST_MODE_BIT, 0},
226  });
227  EXPECT_WRITE32(USBDEV_PHY_CONFIG_REG_OFFSET,
228  {
229  {USBDEV_PHY_CONFIG_USE_DIFF_RCVR_BIT, 1},
230  {USBDEV_PHY_CONFIG_TX_USE_D_SE0_BIT, 0},
231  {USBDEV_PHY_CONFIG_EOP_SINGLE_BIT_BIT, 0},
232  {USBDEV_PHY_CONFIG_PINFLIP_BIT, 1},
233  {USBDEV_PHY_CONFIG_USB_REF_DISABLE_BIT, 0},
234  {USBDEV_PHY_CONFIG_TX_OSC_TEST_MODE_BIT, 1},
235  });
236  EXPECT_DIF_OK(dif_usbdev_set_osc_test_mode(&usbdev_, kDifToggleEnabled));
237 
238  EXPECT_READ32(USBDEV_PHY_CONFIG_REG_OFFSET,
239  {
240  {USBDEV_PHY_CONFIG_USE_DIFF_RCVR_BIT, 1},
241  {USBDEV_PHY_CONFIG_TX_USE_D_SE0_BIT, 0},
242  {USBDEV_PHY_CONFIG_EOP_SINGLE_BIT_BIT, 0},
243  {USBDEV_PHY_CONFIG_PINFLIP_BIT, 1},
244  {USBDEV_PHY_CONFIG_USB_REF_DISABLE_BIT, 0},
245  {USBDEV_PHY_CONFIG_TX_OSC_TEST_MODE_BIT, 1},
246  });
247  EXPECT_WRITE32(USBDEV_PHY_CONFIG_REG_OFFSET,
248  {
249  {USBDEV_PHY_CONFIG_USE_DIFF_RCVR_BIT, 1},
250  {USBDEV_PHY_CONFIG_TX_USE_D_SE0_BIT, 0},
251  {USBDEV_PHY_CONFIG_EOP_SINGLE_BIT_BIT, 0},
252  {USBDEV_PHY_CONFIG_PINFLIP_BIT, 1},
253  {USBDEV_PHY_CONFIG_USB_REF_DISABLE_BIT, 0},
254  {USBDEV_PHY_CONFIG_TX_OSC_TEST_MODE_BIT, 0},
255  });
256  EXPECT_DIF_OK(dif_usbdev_set_osc_test_mode(&usbdev_, kDifToggleDisabled));
257 }
258 
259 TEST_F(UsbdevTest, ConnectAndConfig) {
260  // Connect the interface.
261  EXPECT_READ32(USBDEV_USBCTRL_REG_OFFSET, 0);
262  EXPECT_WRITE32(USBDEV_USBCTRL_REG_OFFSET, {{USBDEV_USBCTRL_ENABLE_BIT, 1}});
263  EXPECT_DIF_OK(dif_usbdev_interface_enable(&usbdev_, kDifToggleEnabled));
264 
265  // Disconnect the interface.
266  EXPECT_READ32(USBDEV_USBCTRL_REG_OFFSET,
267  {
268  {USBDEV_USBCTRL_ENABLE_BIT, 1},
269  {USBDEV_USBCTRL_DEVICE_ADDRESS_OFFSET, 127},
270  });
271  EXPECT_WRITE32(USBDEV_USBCTRL_REG_OFFSET,
272  {
273  {USBDEV_USBCTRL_ENABLE_BIT, 0},
274  {USBDEV_USBCTRL_DEVICE_ADDRESS_OFFSET, 127},
275  });
276  EXPECT_DIF_OK(dif_usbdev_interface_enable(&usbdev_, kDifToggleDisabled));
277 
278  dif_usbdev_endpoint_id_t endpoint = {
279  .number = 2,
280  .direction = 1,
281  };
282  EXPECT_READ32(USBDEV_EP_IN_ENABLE_REG_OFFSET,
283  {
284  {USBDEV_EP_IN_ENABLE_ENABLE_0_BIT, 1},
285  });
286  EXPECT_WRITE32(USBDEV_EP_IN_ENABLE_REG_OFFSET,
287  {
288  {USBDEV_EP_IN_ENABLE_ENABLE_0_BIT, 1},
289  {USBDEV_EP_IN_ENABLE_ENABLE_2_BIT, 1},
290  });
291  EXPECT_DIF_OK(
292  dif_usbdev_endpoint_enable(&usbdev_, endpoint, kDifToggleEnabled));
293 
294  endpoint.number = 6;
295  endpoint.direction = 0;
296  EXPECT_READ32(USBDEV_EP_OUT_ENABLE_REG_OFFSET,
297  {
298  {USBDEV_EP_OUT_ENABLE_ENABLE_5_BIT, 1},
299  {USBDEV_EP_OUT_ENABLE_ENABLE_6_BIT, 1},
300  });
301  EXPECT_WRITE32(USBDEV_EP_OUT_ENABLE_REG_OFFSET,
302  {
303  {USBDEV_EP_OUT_ENABLE_ENABLE_5_BIT, 1},
304  });
305  EXPECT_DIF_OK(
306  dif_usbdev_endpoint_enable(&usbdev_, endpoint, kDifToggleDisabled));
307 
308  endpoint.number = 11;
309  endpoint.direction = 0;
310  EXPECT_READ32(USBDEV_OUT_ISO_REG_OFFSET, {
311  {USBDEV_OUT_ISO_ISO_5_BIT, 1},
312  });
313  EXPECT_WRITE32(USBDEV_OUT_ISO_REG_OFFSET, {
314  {USBDEV_OUT_ISO_ISO_5_BIT, 1},
315  {USBDEV_OUT_ISO_ISO_11_BIT, 1},
316  });
317  EXPECT_DIF_OK(
318  dif_usbdev_endpoint_iso_enable(&usbdev_, endpoint, kDifToggleEnabled));
319 
320  endpoint.number = 7;
321  endpoint.direction = 1;
322  EXPECT_READ32(USBDEV_IN_ISO_REG_OFFSET, {
323  {USBDEV_IN_ISO_ISO_1_BIT, 1},
324  {USBDEV_IN_ISO_ISO_7_BIT, 1},
325  });
326  EXPECT_WRITE32(USBDEV_IN_ISO_REG_OFFSET, {
327  {USBDEV_IN_ISO_ISO_1_BIT, 1},
328  });
329  EXPECT_DIF_OK(
330  dif_usbdev_endpoint_iso_enable(&usbdev_, endpoint, kDifToggleDisabled));
331 }
332 
333 TEST_F(UsbdevTest, OutEndpointConfig) {
334  EXPECT_READ32(USBDEV_RXENABLE_SETUP_REG_OFFSET,
335  {
336  {USBDEV_RXENABLE_SETUP_SETUP_0_BIT, 1},
337  {USBDEV_RXENABLE_SETUP_SETUP_10_BIT, 1},
338  {USBDEV_RXENABLE_SETUP_SETUP_11_BIT, 1},
339  });
340  EXPECT_WRITE32(USBDEV_RXENABLE_SETUP_REG_OFFSET,
341  {
342  {USBDEV_RXENABLE_SETUP_SETUP_0_BIT, 1},
343  {USBDEV_RXENABLE_SETUP_SETUP_9_BIT, 1},
344  {USBDEV_RXENABLE_SETUP_SETUP_10_BIT, 1},
345  {USBDEV_RXENABLE_SETUP_SETUP_11_BIT, 1},
346  });
347  EXPECT_DIF_OK(dif_usbdev_endpoint_setup_enable(&usbdev_, /*endpoint=*/9,
348  kDifToggleEnabled));
349 
350  EXPECT_READ32(USBDEV_RXENABLE_SETUP_REG_OFFSET,
351  {
352  {USBDEV_RXENABLE_SETUP_SETUP_8_BIT, 1},
353  {USBDEV_RXENABLE_SETUP_SETUP_9_BIT, 1},
354  {USBDEV_RXENABLE_SETUP_SETUP_10_BIT, 1},
355  });
356  EXPECT_WRITE32(USBDEV_RXENABLE_SETUP_REG_OFFSET,
357  {
358  {USBDEV_RXENABLE_SETUP_SETUP_8_BIT, 1},
359  {USBDEV_RXENABLE_SETUP_SETUP_9_BIT, 1},
360  });
361  EXPECT_DIF_OK(dif_usbdev_endpoint_setup_enable(&usbdev_, /*endpoint=*/10,
362  kDifToggleDisabled));
363 
364  EXPECT_READ32(USBDEV_RXENABLE_OUT_REG_OFFSET,
365  {
366  {USBDEV_RXENABLE_OUT_OUT_0_BIT, 1},
367  {USBDEV_RXENABLE_OUT_OUT_2_BIT, 1},
368  {USBDEV_RXENABLE_OUT_OUT_9_BIT, 1},
369  });
370  EXPECT_WRITE32(USBDEV_RXENABLE_OUT_REG_OFFSET,
371  {
372  {USBDEV_RXENABLE_OUT_OUT_0_BIT, 1},
373  {USBDEV_RXENABLE_OUT_OUT_2_BIT, 1},
374  {USBDEV_RXENABLE_OUT_OUT_5_BIT, 1},
375  {USBDEV_RXENABLE_OUT_OUT_9_BIT, 1},
376  });
377  EXPECT_DIF_OK(dif_usbdev_endpoint_out_enable(&usbdev_, /*endpoint=*/5,
378  kDifToggleEnabled));
379 
380  EXPECT_READ32(USBDEV_RXENABLE_OUT_REG_OFFSET,
381  {
382  {USBDEV_RXENABLE_OUT_OUT_1_BIT, 1},
383  {USBDEV_RXENABLE_OUT_OUT_3_BIT, 1},
384  {USBDEV_RXENABLE_OUT_OUT_7_BIT, 1},
385  });
386  EXPECT_WRITE32(USBDEV_RXENABLE_OUT_REG_OFFSET,
387  {
388  {USBDEV_RXENABLE_OUT_OUT_1_BIT, 1},
389  {USBDEV_RXENABLE_OUT_OUT_7_BIT, 1},
390  });
391  EXPECT_DIF_OK(dif_usbdev_endpoint_out_enable(&usbdev_, /*endpoint=*/3,
392  kDifToggleDisabled));
393 
394  EXPECT_READ32(USBDEV_SET_NAK_OUT_REG_OFFSET,
395  {
396  {USBDEV_SET_NAK_OUT_ENABLE_10_BIT, 1},
397  });
398  EXPECT_WRITE32(USBDEV_SET_NAK_OUT_REG_OFFSET,
399  {
400  {USBDEV_SET_NAK_OUT_ENABLE_9_BIT, 1},
401  {USBDEV_SET_NAK_OUT_ENABLE_10_BIT, 1},
402  });
403  EXPECT_DIF_OK(dif_usbdev_endpoint_set_nak_out_enable(&usbdev_, /*endpoint=*/9,
404  kDifToggleEnabled));
405 
406  EXPECT_READ32(USBDEV_SET_NAK_OUT_REG_OFFSET,
407  {
408  {USBDEV_SET_NAK_OUT_ENABLE_8_BIT, 1},
409  {USBDEV_SET_NAK_OUT_ENABLE_9_BIT, 1},
410  });
411  EXPECT_WRITE32(USBDEV_SET_NAK_OUT_REG_OFFSET,
412  {
413  {USBDEV_SET_NAK_OUT_ENABLE_9_BIT, 1},
414  });
415  EXPECT_DIF_OK(dif_usbdev_endpoint_set_nak_out_enable(&usbdev_, /*endpoint=*/8,
416  kDifToggleDisabled));
417 }
418 
419 TEST_F(UsbdevTest, StallConfig) {
420  dif_usbdev_endpoint_id_t endpoint = {
421  .number = 1,
422  .direction = 1,
423  };
424  EXPECT_READ32(USBDEV_IN_STALL_REG_OFFSET,
425  {
426  {USBDEV_IN_STALL_ENDPOINT_0_BIT, 1},
427  });
428  EXPECT_WRITE32(USBDEV_IN_STALL_REG_OFFSET,
429  {
430  {USBDEV_IN_STALL_ENDPOINT_0_BIT, 1},
431  {USBDEV_IN_STALL_ENDPOINT_1_BIT, 1},
432  });
433  EXPECT_DIF_OK(
434  dif_usbdev_endpoint_stall_enable(&usbdev_, endpoint, kDifToggleEnabled));
435 
436  endpoint.number = 3;
437  endpoint.direction = 0;
438  EXPECT_READ32(USBDEV_OUT_STALL_REG_OFFSET,
439  {
440  {USBDEV_OUT_STALL_ENDPOINT_5_BIT, 1},
441  });
442  EXPECT_WRITE32(USBDEV_OUT_STALL_REG_OFFSET,
443  {
444  {USBDEV_OUT_STALL_ENDPOINT_3_BIT, 1},
445  {USBDEV_OUT_STALL_ENDPOINT_5_BIT, 1},
446  });
447  EXPECT_DIF_OK(
448  dif_usbdev_endpoint_stall_enable(&usbdev_, endpoint, kDifToggleEnabled));
449 
450  bool enabled;
451  endpoint.number = 5;
452  endpoint.direction = 1;
453  EXPECT_READ32(USBDEV_IN_STALL_REG_OFFSET,
454  {
455  {USBDEV_IN_STALL_ENDPOINT_5_BIT, 1},
456  });
457  EXPECT_DIF_OK(dif_usbdev_endpoint_stall_get(&usbdev_, endpoint, &enabled));
458  EXPECT_TRUE(enabled);
459 
460  endpoint.number = 11;
461  endpoint.direction = 0;
462  EXPECT_READ32(USBDEV_OUT_STALL_REG_OFFSET,
463  {
464  {USBDEV_OUT_STALL_ENDPOINT_5_BIT, 1},
465  {USBDEV_OUT_STALL_ENDPOINT_9_BIT, 1},
466  {USBDEV_OUT_STALL_ENDPOINT_10_BIT, 1},
467  });
468  EXPECT_DIF_OK(dif_usbdev_endpoint_stall_get(&usbdev_, endpoint, &enabled));
469  EXPECT_FALSE(enabled);
470 }
471 
472 TEST_F(UsbdevTest, OutPacket) {
473  // Note: the DIF only strives to ensure that at least 2 SETUP buffers are
474  // available, in an effort to prevent buffer exhaustion; the FIFO physically
475  // has more entries, as a contingency.
476  constexpr uint32_t kMaxAvSetupBuffers = 2u;
477  constexpr uint32_t kMaxAvOutBuffers = 8u;
478  dif_usbdev_buffer_pool_t buffer_pool;
479  dif_usbdev_config_t phy_config = {
480  .have_differential_receiver = kDifToggleEnabled,
481  .use_tx_d_se0 = kDifToggleDisabled,
482  .single_bit_eop = kDifToggleDisabled,
483  .pin_flip = kDifToggleDisabled,
484  .clock_sync_signals = kDifToggleEnabled,
485  };
486  EXPECT_WRITE32(USBDEV_PHY_CONFIG_REG_OFFSET,
487  {
488  {USBDEV_PHY_CONFIG_USE_DIFF_RCVR_BIT, 1},
489  {USBDEV_PHY_CONFIG_TX_USE_D_SE0_BIT, 0},
490  {USBDEV_PHY_CONFIG_EOP_SINGLE_BIT_BIT, 0},
491  {USBDEV_PHY_CONFIG_PINFLIP_BIT, 0},
492  {USBDEV_PHY_CONFIG_USB_REF_DISABLE_BIT, 0},
493  });
494  EXPECT_DIF_OK(dif_usbdev_configure(&usbdev_, &buffer_pool, phy_config));
495 
496  // Add buffers to the AV SETUP FIFO and Av OUT FIFO to receive.
497  for (uint32_t i = 0u; i < kMaxAvSetupBuffers + kMaxAvOutBuffers; ++i) {
498  uint8_t setup_depth = (i >= kMaxAvSetupBuffers) ? kMaxAvSetupBuffers : i;
499  uint8_t out_depth =
500  (i >= kMaxAvSetupBuffers) ? (i - kMaxAvSetupBuffers) : 0u;
501  int top = buffer_pool.top;
502  EXPECT_READ32(USBDEV_USBSTAT_REG_OFFSET,
503  {
504  {USBDEV_USBSTAT_FRAME_OFFSET, 10},
505  {USBDEV_USBSTAT_LINK_STATE_OFFSET,
506  USBDEV_USBSTAT_LINK_STATE_VALUE_ACTIVE},
507  {USBDEV_USBSTAT_SENSE_BIT, 1},
508  {USBDEV_USBSTAT_AV_OUT_DEPTH_OFFSET, out_depth},
509  {USBDEV_USBSTAT_AV_SETUP_DEPTH_OFFSET, setup_depth},
510  {USBDEV_USBSTAT_AV_OUT_FULL_BIT, 0},
511  {USBDEV_USBSTAT_AV_SETUP_FULL_BIT, 0},
512  });
513  if (i >= kMaxAvSetupBuffers) {
514  EXPECT_WRITE32(
515  USBDEV_AVOUTBUFFER_REG_OFFSET,
516  {{USBDEV_AVOUTBUFFER_BUFFER_OFFSET, buffer_pool.buffers[top - i]}});
517  } else {
518  EXPECT_WRITE32(
519  USBDEV_AVSETUPBUFFER_REG_OFFSET,
520  {{USBDEV_AVSETUPBUFFER_BUFFER_OFFSET, buffer_pool.buffers[top - i]}});
521  }
522  }
523  EXPECT_READ32(
524  USBDEV_USBSTAT_REG_OFFSET,
525  {
526  {USBDEV_USBSTAT_FRAME_OFFSET, 10},
527  {USBDEV_USBSTAT_LINK_STATE_OFFSET,
528  USBDEV_USBSTAT_LINK_STATE_VALUE_ACTIVE},
529  {USBDEV_USBSTAT_SENSE_BIT, 1},
530  {USBDEV_USBSTAT_AV_OUT_DEPTH_OFFSET, kMaxAvOutBuffers},
531  {USBDEV_USBSTAT_AV_SETUP_DEPTH_OFFSET, kMaxAvSetupBuffers},
532  {USBDEV_USBSTAT_AV_OUT_FULL_BIT, 1},
533  {USBDEV_USBSTAT_AV_SETUP_FULL_BIT, 0}, // FIFO is physically larger
534  });
535  EXPECT_DIF_OK(dif_usbdev_fill_available_fifos(&usbdev_, &buffer_pool));
536 
537  // No read data available yet.
538  dif_usbdev_rx_packet_info_t rx_packet_info;
539  dif_usbdev_buffer_t buffer;
540  EXPECT_READ32(USBDEV_USBSTAT_REG_OFFSET,
541  {
542  {USBDEV_USBSTAT_FRAME_OFFSET, 15},
543  {USBDEV_USBSTAT_LINK_STATE_OFFSET,
544  USBDEV_USBSTAT_LINK_STATE_VALUE_ACTIVE},
545  {USBDEV_USBSTAT_SENSE_BIT, 1},
546  {USBDEV_USBSTAT_AV_OUT_DEPTH_OFFSET, kMaxAvOutBuffers},
547  {USBDEV_USBSTAT_AV_SETUP_DEPTH_OFFSET, kMaxAvSetupBuffers},
548  {USBDEV_USBSTAT_AV_OUT_FULL_BIT, 1},
549  {USBDEV_USBSTAT_AV_SETUP_FULL_BIT, 0},
550  {USBDEV_USBSTAT_RX_EMPTY_BIT, 1},
551  });
552  EXPECT_EQ(dif_usbdev_recv(&usbdev_, &rx_packet_info, &buffer),
553  kDifUnavailable);
554 
555  // Receive OUT packet all at once.
556  uint32_t expected_data[4], recvd_data[4];
557  for (size_t i = 0; i < sizeof(expected_data) / sizeof(expected_data[0]);
558  i++) {
559  expected_data[i] = i * 1023;
560  }
561  EXPECT_READ32(USBDEV_USBSTAT_REG_OFFSET,
562  {
563  {USBDEV_USBSTAT_FRAME_OFFSET, 15},
564  {USBDEV_USBSTAT_LINK_STATE_OFFSET,
565  USBDEV_USBSTAT_LINK_STATE_VALUE_ACTIVE},
566  {USBDEV_USBSTAT_SENSE_BIT, 1},
567  {USBDEV_USBSTAT_AV_OUT_DEPTH_OFFSET, kMaxAvOutBuffers - 1},
568  {USBDEV_USBSTAT_AV_SETUP_DEPTH_OFFSET, kMaxAvSetupBuffers},
569  {USBDEV_USBSTAT_AV_OUT_FULL_BIT, 0},
570  {USBDEV_USBSTAT_AV_SETUP_FULL_BIT, 0},
571  {USBDEV_USBSTAT_RX_EMPTY_BIT, 0},
572  });
573  EXPECT_READ32(USBDEV_RXFIFO_REG_OFFSET,
574  {
575  {USBDEV_RXFIFO_EP_OFFSET, 1},
576  {USBDEV_RXFIFO_SETUP_BIT, 0},
577  {USBDEV_RXFIFO_SIZE_OFFSET, sizeof(expected_data)},
578  {USBDEV_RXFIFO_BUFFER_OFFSET, 0},
579  });
580  EXPECT_DIF_OK(dif_usbdev_recv(&usbdev_, &rx_packet_info, &buffer));
581  EXPECT_EQ(rx_packet_info.endpoint, 1);
582  EXPECT_EQ(rx_packet_info.length, sizeof(expected_data));
583  EXPECT_FALSE(rx_packet_info.is_setup);
584  EXPECT_EQ(buffer.id, 0);
585  EXPECT_EQ(buffer.offset, 0);
586  EXPECT_EQ(buffer.remaining_bytes, sizeof(expected_data));
587  EXPECT_EQ(buffer.type, kDifUsbdevBufferTypeRead);
588 
589  size_t bytes_written;
590  for (size_t i = 0; i < sizeof(expected_data) / sizeof(expected_data[0]);
591  i++) {
592  EXPECT_READ32(USBDEV_BUFFER_REG_OFFSET + buffer.id * 64 + 4 * i,
593  expected_data[i]);
594  }
595  EXPECT_DIF_OK(dif_usbdev_buffer_read(&usbdev_, &buffer_pool, &buffer,
596  reinterpret_cast<uint8_t *>(recvd_data),
597  sizeof(recvd_data), &bytes_written));
598  EXPECT_EQ(bytes_written, sizeof(recvd_data));
599  EXPECT_EQ(memcmp(expected_data, recvd_data, sizeof(expected_data)), 0);
600 
601  // One more received packet to test other offsets and the Av SETUP Buffer FIFO
602  EXPECT_READ32(
603  USBDEV_USBSTAT_REG_OFFSET,
604  {
605  {USBDEV_USBSTAT_FRAME_OFFSET, 25},
606  {USBDEV_USBSTAT_LINK_STATE_OFFSET,
607  USBDEV_USBSTAT_LINK_STATE_VALUE_ACTIVE},
608  {USBDEV_USBSTAT_SENSE_BIT, 1},
609  {USBDEV_USBSTAT_AV_OUT_DEPTH_OFFSET, kMaxAvOutBuffers - 1},
610  {USBDEV_USBSTAT_AV_SETUP_DEPTH_OFFSET, kMaxAvSetupBuffers - 1},
611  {USBDEV_USBSTAT_AV_OUT_FULL_BIT, 0},
612  {USBDEV_USBSTAT_AV_SETUP_FULL_BIT, 0},
613  {USBDEV_USBSTAT_RX_EMPTY_BIT, 0},
614  });
615  EXPECT_READ32(USBDEV_RXFIFO_REG_OFFSET,
616  {
617  {USBDEV_RXFIFO_EP_OFFSET, 0},
618  {USBDEV_RXFIFO_SETUP_BIT, 1}, // SETUP packet this time
619  {USBDEV_RXFIFO_SIZE_OFFSET, sizeof(expected_data) - 1},
620  {USBDEV_RXFIFO_BUFFER_OFFSET, 1},
621  });
622  EXPECT_DIF_OK(dif_usbdev_recv(&usbdev_, &rx_packet_info, &buffer));
623  EXPECT_EQ(rx_packet_info.endpoint, 0);
624  EXPECT_EQ(rx_packet_info.length, sizeof(expected_data) - 1);
625  EXPECT_TRUE(rx_packet_info.is_setup);
626  EXPECT_EQ(buffer.id, 1);
627  EXPECT_EQ(buffer.offset, 0);
628  EXPECT_EQ(buffer.remaining_bytes, sizeof(expected_data) - 1);
629  EXPECT_EQ(buffer.type, kDifUsbdevBufferTypeRead);
630 
631  memset(recvd_data, 0, sizeof(recvd_data));
632  for (size_t i = 0; i < sizeof(expected_data) / sizeof(expected_data[0]);
633  i++) {
634  EXPECT_READ32(USBDEV_BUFFER_REG_OFFSET + buffer.id * 64 + 4 * i,
635  expected_data[i]);
636  }
637  EXPECT_DIF_OK(dif_usbdev_buffer_read(&usbdev_, &buffer_pool, &buffer,
638  reinterpret_cast<uint8_t *>(recvd_data),
639  4, &bytes_written));
640  EXPECT_EQ(bytes_written, 4);
641  EXPECT_DIF_OK(dif_usbdev_buffer_read(
642  &usbdev_, &buffer_pool, &buffer,
643  reinterpret_cast<uint8_t *>(recvd_data) + bytes_written,
644  sizeof(recvd_data) - bytes_written, &bytes_written));
645  EXPECT_EQ(bytes_written, sizeof(recvd_data) - 4 - 1);
646  EXPECT_EQ(memcmp(expected_data, recvd_data, sizeof(expected_data)), 0);
647 }
648 
649 TEST_F(UsbdevTest, InPacket) {
650  dif_usbdev_buffer_pool_t buffer_pool;
651  dif_usbdev_config_t phy_config = {
652  .have_differential_receiver = kDifToggleEnabled,
653  .use_tx_d_se0 = kDifToggleDisabled,
654  .single_bit_eop = kDifToggleDisabled,
655  .pin_flip = kDifToggleDisabled,
656  .clock_sync_signals = kDifToggleEnabled,
657  };
658  EXPECT_WRITE32(USBDEV_PHY_CONFIG_REG_OFFSET,
659  {
660  {USBDEV_PHY_CONFIG_USE_DIFF_RCVR_BIT, 1},
661  {USBDEV_PHY_CONFIG_TX_USE_D_SE0_BIT, 0},
662  {USBDEV_PHY_CONFIG_EOP_SINGLE_BIT_BIT, 0},
663  {USBDEV_PHY_CONFIG_PINFLIP_BIT, 0},
664  {USBDEV_PHY_CONFIG_USB_REF_DISABLE_BIT, 0},
665  });
666  EXPECT_DIF_OK(dif_usbdev_configure(&usbdev_, &buffer_pool, phy_config));
667 
668  dif_usbdev_buffer_t buffer;
669  EXPECT_DIF_OK(dif_usbdev_buffer_request(&usbdev_, &buffer_pool, &buffer));
670  EXPECT_EQ(buffer.type, kDifUsbdevBufferTypeWrite);
671 
672  uint32_t data[16];
673  uint8_t *bytes = reinterpret_cast<uint8_t *>(data);
674  size_t bytes_written;
675  EXPECT_DIF_OK(dif_usbdev_buffer_return(&usbdev_, &buffer_pool, &buffer));
676  EXPECT_EQ(buffer.type, kDifUsbdevBufferTypeStale);
677  // Can't return a stale buffer.
678  EXPECT_DIF_BADARG(dif_usbdev_buffer_return(&usbdev_, &buffer_pool, &buffer));
679  // Can't submit a stale buffer.
680  EXPECT_DIF_BADARG(dif_usbdev_buffer_write(&usbdev_, &buffer, bytes,
681  sizeof(data), &bytes_written));
682 
683  // Request the buffer.
684  EXPECT_DIF_OK(dif_usbdev_buffer_request(&usbdev_, &buffer_pool, &buffer));
685  for (size_t i = 0; i < sizeof(data); i++) {
686  bytes[i] = i;
687  if (i % 4 == 3) {
688  EXPECT_WRITE32(USBDEV_BUFFER_REG_OFFSET + buffer.id * 64 + i - 3,
689  data[i / 4]);
690  }
691  }
692  EXPECT_DIF_OK(dif_usbdev_buffer_write(&usbdev_, &buffer, bytes, sizeof(data),
693  &bytes_written));
694  EXPECT_EQ(bytes_written, sizeof(data));
695 
696  // Queue up the buffer for transmission.
697  EXPECT_WRITE32(USBDEV_CONFIGIN_5_REG_OFFSET,
698  {
699  {USBDEV_CONFIGIN_5_BUFFER_5_OFFSET, buffer.id},
700  {USBDEV_CONFIGIN_5_SIZE_5_OFFSET, bytes_written},
701  });
702  EXPECT_WRITE32(USBDEV_CONFIGIN_5_REG_OFFSET,
703  {
704  {USBDEV_CONFIGIN_5_BUFFER_5_OFFSET, buffer.id},
705  {USBDEV_CONFIGIN_5_SIZE_5_OFFSET, bytes_written},
706  {USBDEV_CONFIGIN_5_RDY_5_BIT, 1},
707  });
708  EXPECT_DIF_OK(dif_usbdev_send(&usbdev_, /*endpoint=*/5, &buffer));
709 
710  // Get TX status for a buffer with a transmission that had to be canceled. The
711  // buffer is returned to the free pool.
712  dif_usbdev_tx_status_t tx_status;
713  EXPECT_READ32(USBDEV_CONFIGIN_0_REG_OFFSET,
714  {
715  {USBDEV_CONFIGIN_0_BUFFER_0_OFFSET, buffer.id},
716  {USBDEV_CONFIGIN_0_SIZE_0_OFFSET, sizeof(data)},
717  {USBDEV_CONFIGIN_0_RDY_0_BIT, 0},
718  {USBDEV_CONFIGIN_0_PEND_0_BIT, 1},
719  });
720  EXPECT_READ32(USBDEV_IN_SENT_REG_OFFSET, {
721  {USBDEV_IN_SENT_SENT_0_BIT, 0},
722  });
723  EXPECT_DIF_OK(dif_usbdev_get_tx_status(&usbdev_, /*endpoint=*/0, &tx_status));
724  EXPECT_EQ(tx_status, kDifUsbdevTxStatusCancelled);
725  EXPECT_READ32(USBDEV_CONFIGIN_0_REG_OFFSET,
726  {
727  {USBDEV_CONFIGIN_0_BUFFER_0_OFFSET, buffer.id},
728  {USBDEV_CONFIGIN_0_SIZE_0_OFFSET, sizeof(data)},
729  {USBDEV_CONFIGIN_0_RDY_0_BIT, 0},
730  {USBDEV_CONFIGIN_0_PEND_0_BIT, 1},
731  });
732  EXPECT_WRITE32(USBDEV_CONFIGIN_0_REG_OFFSET,
733  {{USBDEV_CONFIGIN_0_PEND_0_BIT, 1}});
734  EXPECT_WRITE32(USBDEV_IN_SENT_REG_OFFSET, {{USBDEV_IN_SENT_SENT_0_BIT, 1}});
735  EXPECT_DIF_OK(
736  dif_usbdev_clear_tx_status(&usbdev_, &buffer_pool, /*endpoint=*/0));
737 
738  // Request a new buffer.
739  EXPECT_DIF_OK(dif_usbdev_buffer_request(&usbdev_, &buffer_pool, &buffer));
740  for (size_t i = 0; i < sizeof(data); i++) {
741  bytes[i] = i;
742  if (i % 4 == 3) {
743  EXPECT_WRITE32(USBDEV_BUFFER_REG_OFFSET + buffer.id * 64 + i - 3,
744  data[i / 4]);
745  }
746  }
747  EXPECT_DIF_OK(dif_usbdev_buffer_write(&usbdev_, &buffer, bytes, sizeof(data),
748  &bytes_written));
749 
750  // Queue the buffer for transmission.
751  EXPECT_WRITE32(USBDEV_CONFIGIN_4_REG_OFFSET,
752  {
753  {USBDEV_CONFIGIN_4_BUFFER_4_OFFSET, buffer.id},
754  {USBDEV_CONFIGIN_4_SIZE_4_OFFSET, sizeof(data)},
755  });
756  EXPECT_WRITE32(USBDEV_CONFIGIN_4_REG_OFFSET,
757  {
758  {USBDEV_CONFIGIN_4_BUFFER_4_OFFSET, buffer.id},
759  {USBDEV_CONFIGIN_4_SIZE_4_OFFSET, sizeof(data)},
760  {USBDEV_CONFIGIN_4_RDY_4_BIT, 1},
761  });
762  EXPECT_DIF_OK(dif_usbdev_send(&usbdev_, /*endpoint=*/4, &buffer));
763 
764  // Get status of an endpoint without a buffer queued for transmission.
765  EXPECT_READ32(USBDEV_CONFIGIN_7_REG_OFFSET,
766  {
767  {USBDEV_CONFIGIN_7_BUFFER_7_OFFSET, buffer.id},
768  {USBDEV_CONFIGIN_7_SIZE_7_OFFSET, sizeof(data)},
769  {USBDEV_CONFIGIN_7_RDY_7_BIT, 0},
770  });
771  EXPECT_READ32(USBDEV_IN_SENT_REG_OFFSET, {
772  {USBDEV_IN_SENT_SENT_7_BIT, 0},
773  });
774  EXPECT_DIF_OK(dif_usbdev_get_tx_status(&usbdev_, /*endpoint=*/7, &tx_status));
775  EXPECT_EQ(tx_status, kDifUsbdevTxStatusNoPacket);
776 
777  // Get TX status for a queued, but not sent buffer.
778  EXPECT_READ32(USBDEV_CONFIGIN_8_REG_OFFSET,
779  {
780  {USBDEV_CONFIGIN_8_BUFFER_8_OFFSET, buffer.id},
781  {USBDEV_CONFIGIN_8_SIZE_8_OFFSET, sizeof(data)},
782  {USBDEV_CONFIGIN_8_RDY_8_BIT, 1},
783  });
784  EXPECT_DIF_OK(dif_usbdev_get_tx_status(&usbdev_, /*endpoint=*/8, &tx_status));
785  EXPECT_EQ(tx_status, kDifUsbdevTxStatusPending);
786 
787  // Buffer was transmitted successfully.
788  uint16_t endpoints_done;
789  EXPECT_READ32(USBDEV_IN_SENT_REG_OFFSET, {
790  {USBDEV_IN_SENT_SENT_3_BIT, 1},
791  {USBDEV_IN_SENT_SENT_5_BIT, 1},
792  });
793  EXPECT_DIF_OK(dif_usbdev_get_tx_sent(&usbdev_, &endpoints_done));
794  EXPECT_EQ(endpoints_done, (1u << 3) | (1u << 5));
795 
796  EXPECT_READ32(USBDEV_CONFIGIN_5_REG_OFFSET,
797  {
798  {USBDEV_CONFIGIN_5_BUFFER_5_OFFSET, buffer.id},
799  {USBDEV_CONFIGIN_5_SIZE_5_OFFSET, sizeof(data)},
800  {USBDEV_CONFIGIN_5_RDY_5_BIT, 0},
801  });
802  EXPECT_READ32(USBDEV_IN_SENT_REG_OFFSET, {
803  {USBDEV_IN_SENT_SENT_3_BIT, 1},
804  {USBDEV_IN_SENT_SENT_5_BIT, 1},
805  });
806  EXPECT_DIF_OK(dif_usbdev_get_tx_status(&usbdev_, /*endpoint=*/5, &tx_status));
807  EXPECT_EQ(tx_status, kDifUsbdevTxStatusSent);
808  EXPECT_EQ(buffer.type, kDifUsbdevBufferTypeStale);
809 
810  EXPECT_READ32(USBDEV_CONFIGIN_5_REG_OFFSET,
811  {
812  {USBDEV_CONFIGIN_5_BUFFER_5_OFFSET, buffer.id},
813  {USBDEV_CONFIGIN_5_SIZE_5_OFFSET, sizeof(data)},
814  {USBDEV_CONFIGIN_5_RDY_5_BIT, 0},
815  });
816  EXPECT_WRITE32(USBDEV_CONFIGIN_5_REG_OFFSET,
817  {{USBDEV_CONFIGIN_5_PEND_5_BIT, 1}});
818  EXPECT_WRITE32(USBDEV_IN_SENT_REG_OFFSET, {{USBDEV_IN_SENT_SENT_5_BIT, 1}});
819  EXPECT_DIF_OK(
820  dif_usbdev_clear_tx_status(&usbdev_, &buffer_pool, /*endpoint=*/5));
821 }
822 
823 TEST_F(UsbdevTest, DeviceAddresses) {
824  uint8_t address = 101;
825  EXPECT_READ32(USBDEV_USBCTRL_REG_OFFSET,
826  {
827  {USBDEV_USBCTRL_ENABLE_BIT, 1},
828  {USBDEV_USBCTRL_DEVICE_ADDRESS_OFFSET, 0},
829  });
830  EXPECT_WRITE32(USBDEV_USBCTRL_REG_OFFSET,
831  {
832  {USBDEV_USBCTRL_ENABLE_BIT, 1},
833  {USBDEV_USBCTRL_DEVICE_ADDRESS_OFFSET, address},
834  });
835  EXPECT_DIF_OK(dif_usbdev_address_set(&usbdev_, address));
836 
837  EXPECT_READ32(USBDEV_USBCTRL_REG_OFFSET,
838  {
839  {USBDEV_USBCTRL_ENABLE_BIT, 1},
840  {USBDEV_USBCTRL_DEVICE_ADDRESS_OFFSET, 58},
841  });
842  EXPECT_DIF_OK(dif_usbdev_address_get(&usbdev_, &address));
843  EXPECT_EQ(address, 58);
844 }
845 
846 TEST_F(UsbdevTest, Status) {
847  // dif_usbdev_clear_data_toggle compatibility with earlier implementations
848  EXPECT_WRITE32(USBDEV_OUT_DATA_TOGGLE_REG_OFFSET,
849  {
850  {USBDEV_OUT_DATA_TOGGLE_STATUS_OFFSET, 0u},
851  {USBDEV_OUT_DATA_TOGGLE_MASK_OFFSET, 1u << 3},
852  });
853  EXPECT_WRITE32(USBDEV_IN_DATA_TOGGLE_REG_OFFSET,
854  {
855  {USBDEV_IN_DATA_TOGGLE_STATUS_OFFSET, 0u},
856  {USBDEV_IN_DATA_TOGGLE_MASK_OFFSET, 1u << 3},
857  });
858  EXPECT_DIF_OK(dif_usbdev_clear_data_toggle(&usbdev_, /*endpoint=*/3));
859  EXPECT_WRITE32(USBDEV_OUT_DATA_TOGGLE_REG_OFFSET,
860  {
861  {USBDEV_OUT_DATA_TOGGLE_STATUS_OFFSET, 0u},
862  {USBDEV_OUT_DATA_TOGGLE_MASK_OFFSET, 1u << 9},
863  });
864  EXPECT_WRITE32(USBDEV_IN_DATA_TOGGLE_REG_OFFSET,
865  {
866  {USBDEV_IN_DATA_TOGGLE_STATUS_OFFSET, 0u},
867  {USBDEV_IN_DATA_TOGGLE_MASK_OFFSET, 1u << 9},
868  });
869  EXPECT_DIF_OK(dif_usbdev_clear_data_toggle(&usbdev_, /*endpoint=*/9));
870  // Setting of all data toggles to known values; eg. restoring after Deep Sleep
871  const uint16_t all_endpoints = (1u << USBDEV_NUM_ENDPOINTS) - 1u;
872  const uint16_t even_endpoints = (0x40000000u / 3) & all_endpoints;
873  const uint16_t odd_endpoints = even_endpoints << 1;
874  EXPECT_WRITE32(USBDEV_OUT_DATA_TOGGLE_REG_OFFSET,
875  {
876  {USBDEV_OUT_DATA_TOGGLE_STATUS_OFFSET, even_endpoints},
877  {USBDEV_OUT_DATA_TOGGLE_MASK_OFFSET, all_endpoints},
878  });
879  EXPECT_DIF_OK(dif_usbdev_data_toggle_out_write(&usbdev_, all_endpoints,
880  even_endpoints));
881  EXPECT_WRITE32(USBDEV_IN_DATA_TOGGLE_REG_OFFSET,
882  {
883  {USBDEV_IN_DATA_TOGGLE_STATUS_OFFSET, odd_endpoints},
884  {USBDEV_IN_DATA_TOGGLE_MASK_OFFSET, all_endpoints},
885  });
886  EXPECT_DIF_OK(
887  dif_usbdev_data_toggle_in_write(&usbdev_, all_endpoints, odd_endpoints));
888  // Saving of data toggles; eg. capturing at entry to Deep Sleep
889  uint16_t out_toggles;
890  EXPECT_READ32(USBDEV_OUT_DATA_TOGGLE_REG_OFFSET,
891  {
892  {USBDEV_OUT_DATA_TOGGLE_STATUS_OFFSET, odd_endpoints},
893  {USBDEV_OUT_DATA_TOGGLE_MASK_OFFSET, 0u}, // Reads as zero
894  });
895  EXPECT_DIF_OK(dif_usbdev_data_toggle_out_read(&usbdev_, &out_toggles));
896  EXPECT_EQ(out_toggles, odd_endpoints);
897  uint16_t in_toggles;
898  EXPECT_READ32(USBDEV_IN_DATA_TOGGLE_REG_OFFSET,
899  {
900  {USBDEV_IN_DATA_TOGGLE_STATUS_OFFSET, even_endpoints},
901  {USBDEV_OUT_DATA_TOGGLE_MASK_OFFSET, 0u}, // Reads as zero
902  });
903  EXPECT_DIF_OK(dif_usbdev_data_toggle_in_read(&usbdev_, &in_toggles));
904  EXPECT_EQ(in_toggles, even_endpoints);
905 
906  uint16_t frame;
907  EXPECT_READ32(USBDEV_USBSTAT_REG_OFFSET,
908  {
909  {USBDEV_USBSTAT_FRAME_OFFSET, 92},
910  {USBDEV_USBSTAT_SENSE_BIT, 1},
911  {USBDEV_USBSTAT_LINK_STATE_OFFSET,
912  USBDEV_USBSTAT_LINK_STATE_VALUE_ACTIVE},
913  {USBDEV_USBSTAT_AV_OUT_DEPTH_OFFSET, 2},
914  });
915  EXPECT_DIF_OK(dif_usbdev_status_get_frame(&usbdev_, &frame));
916  EXPECT_EQ(frame, 92);
917 
918  bool host_lost;
919  EXPECT_READ32(USBDEV_USBSTAT_REG_OFFSET,
920  {
921  {USBDEV_USBSTAT_FRAME_OFFSET, 18},
922  {USBDEV_USBSTAT_SENSE_BIT, 1},
923  {USBDEV_USBSTAT_LINK_STATE_OFFSET,
924  USBDEV_USBSTAT_LINK_STATE_VALUE_ACTIVE_NOSOF},
925  {USBDEV_USBSTAT_AV_OUT_DEPTH_OFFSET, 2},
926  {USBDEV_USBSTAT_HOST_LOST_BIT, 1},
927  });
928  EXPECT_DIF_OK(dif_usbdev_status_get_host_lost(&usbdev_, &host_lost));
929  EXPECT_TRUE(host_lost);
930  EXPECT_READ32(USBDEV_USBSTAT_REG_OFFSET,
931  {
932  {USBDEV_USBSTAT_FRAME_OFFSET, 18},
933  {USBDEV_USBSTAT_LINK_STATE_OFFSET,
934  USBDEV_USBSTAT_LINK_STATE_VALUE_ACTIVE_NOSOF},
935  {USBDEV_USBSTAT_SENSE_BIT, 1},
936  {USBDEV_USBSTAT_AV_OUT_DEPTH_OFFSET, 2},
937  {USBDEV_USBSTAT_HOST_LOST_BIT, 0},
938  });
939  EXPECT_DIF_OK(dif_usbdev_status_get_host_lost(&usbdev_, &host_lost));
940  EXPECT_FALSE(host_lost);
941 
942  bool vbus_sense;
943  EXPECT_READ32(USBDEV_USBSTAT_REG_OFFSET,
944  {
945  {USBDEV_USBSTAT_FRAME_OFFSET, 31},
946  {USBDEV_USBSTAT_LINK_STATE_OFFSET,
947  USBDEV_USBSTAT_LINK_STATE_VALUE_ACTIVE_NOSOF},
948  {USBDEV_USBSTAT_SENSE_BIT, 1},
949  });
950  EXPECT_DIF_OK(dif_usbdev_status_get_sense(&usbdev_, &vbus_sense));
951  EXPECT_TRUE(vbus_sense);
952 
953  EXPECT_READ32(USBDEV_USBSTAT_REG_OFFSET,
954  {
955  {USBDEV_USBSTAT_FRAME_OFFSET, 31},
956  {USBDEV_USBSTAT_LINK_STATE_OFFSET,
957  USBDEV_USBSTAT_LINK_STATE_VALUE_DISCONNECTED},
958  {USBDEV_USBSTAT_SENSE_BIT, 0},
959  });
960  EXPECT_DIF_OK(dif_usbdev_status_get_sense(&usbdev_, &vbus_sense));
961  EXPECT_FALSE(vbus_sense);
962 
963  uint8_t av_setup_fifo_depth;
964  uint8_t av_out_fifo_depth;
965  EXPECT_READ32(USBDEV_USBSTAT_REG_OFFSET,
966  {
967  {USBDEV_USBSTAT_FRAME_OFFSET, 11},
968  {USBDEV_USBSTAT_LINK_STATE_OFFSET,
969  USBDEV_USBSTAT_LINK_STATE_VALUE_ACTIVE},
970  {USBDEV_USBSTAT_SENSE_BIT, 1},
971  {USBDEV_USBSTAT_AV_OUT_DEPTH_OFFSET, 3},
972  {USBDEV_USBSTAT_RX_EMPTY_BIT, 1},
973  });
974  EXPECT_DIF_OK(dif_usbdev_status_get_available_fifo_depths(
975  &usbdev_, &av_setup_fifo_depth, &av_out_fifo_depth));
976  EXPECT_EQ(av_out_fifo_depth, 3);
977 
978  bool av_setup_fifo_full;
979  bool av_out_fifo_full;
980  EXPECT_READ32(USBDEV_USBSTAT_REG_OFFSET,
981  {
982  {USBDEV_USBSTAT_FRAME_OFFSET, 12},
983  {USBDEV_USBSTAT_LINK_STATE_OFFSET,
984  USBDEV_USBSTAT_LINK_STATE_VALUE_ACTIVE},
985  {USBDEV_USBSTAT_SENSE_BIT, 1},
986  {USBDEV_USBSTAT_AV_OUT_DEPTH_OFFSET, 4},
987  {USBDEV_USBSTAT_AV_OUT_FULL_BIT, 1},
988  {USBDEV_USBSTAT_RX_EMPTY_BIT, 1},
989  });
990  EXPECT_DIF_OK(dif_usbdev_status_get_available_fifo_full(
991  &usbdev_, &av_setup_fifo_full, &av_out_fifo_full));
992  EXPECT_TRUE(av_out_fifo_full);
993 
994  uint8_t rx_fifo_depth;
995  EXPECT_READ32(USBDEV_USBSTAT_REG_OFFSET,
996  {
997  {USBDEV_USBSTAT_FRAME_OFFSET, 12},
998  {USBDEV_USBSTAT_LINK_STATE_OFFSET,
999  USBDEV_USBSTAT_LINK_STATE_VALUE_ACTIVE},
1000  {USBDEV_USBSTAT_SENSE_BIT, 1},
1001  {USBDEV_USBSTAT_AV_OUT_DEPTH_OFFSET, 4},
1002  {USBDEV_USBSTAT_AV_OUT_FULL_BIT, 1},
1003  {USBDEV_USBSTAT_RX_EMPTY_BIT, 0},
1004  {USBDEV_USBSTAT_RX_DEPTH_OFFSET, 2},
1005  });
1006  EXPECT_DIF_OK(dif_usbdev_status_get_rx_fifo_depth(&usbdev_, &rx_fifo_depth));
1007  EXPECT_EQ(rx_fifo_depth, 2);
1008 
1009  bool rx_fifo_empty;
1010  EXPECT_READ32(USBDEV_USBSTAT_REG_OFFSET,
1011  {
1012  {USBDEV_USBSTAT_FRAME_OFFSET, 12},
1013  {USBDEV_USBSTAT_LINK_STATE_OFFSET,
1014  USBDEV_USBSTAT_LINK_STATE_VALUE_ACTIVE},
1015  {USBDEV_USBSTAT_SENSE_BIT, 1},
1016  {USBDEV_USBSTAT_AV_OUT_DEPTH_OFFSET, 4},
1017  {USBDEV_USBSTAT_AV_OUT_FULL_BIT, 1},
1018  {USBDEV_USBSTAT_RX_EMPTY_BIT, 1},
1019  });
1020  EXPECT_DIF_OK(dif_usbdev_status_get_rx_fifo_empty(&usbdev_, &rx_fifo_empty));
1021  EXPECT_TRUE(rx_fifo_empty);
1022 }
1023 
1024 TEST_F(UsbdevTest, LinkState) {
1025  dif_usbdev_link_state_t link_state;
1026  EXPECT_READ32(USBDEV_USBSTAT_REG_OFFSET,
1027  {
1028  {USBDEV_USBSTAT_FRAME_OFFSET, 27},
1029  {USBDEV_USBSTAT_SENSE_BIT, 1},
1030  {USBDEV_USBSTAT_LINK_STATE_OFFSET,
1031  USBDEV_USBSTAT_LINK_STATE_VALUE_ACTIVE},
1032  {USBDEV_USBSTAT_AV_OUT_DEPTH_OFFSET, 2},
1033  });
1034  EXPECT_DIF_OK(dif_usbdev_status_get_link_state(&usbdev_, &link_state));
1035  EXPECT_EQ(link_state, kDifUsbdevLinkStateActive);
1036 
1037  EXPECT_READ32(USBDEV_USBSTAT_REG_OFFSET,
1038  {
1039  {USBDEV_USBSTAT_LINK_STATE_OFFSET,
1040  USBDEV_USBSTAT_LINK_STATE_VALUE_DISCONNECTED},
1041  });
1042  EXPECT_DIF_OK(dif_usbdev_status_get_link_state(&usbdev_, &link_state));
1043  EXPECT_EQ(link_state, kDifUsbdevLinkStateDisconnected);
1044 
1045  EXPECT_READ32(USBDEV_USBSTAT_REG_OFFSET,
1046  {
1047  {USBDEV_USBSTAT_SENSE_BIT, 1},
1048  {USBDEV_USBSTAT_LINK_STATE_OFFSET,
1049  USBDEV_USBSTAT_LINK_STATE_VALUE_POWERED},
1050  });
1051  EXPECT_DIF_OK(dif_usbdev_status_get_link_state(&usbdev_, &link_state));
1052  EXPECT_EQ(link_state, kDifUsbdevLinkStatePowered);
1053 
1054  EXPECT_READ32(USBDEV_USBSTAT_REG_OFFSET,
1055  {
1056  {USBDEV_USBSTAT_SENSE_BIT, 1},
1057  {USBDEV_USBSTAT_LINK_STATE_OFFSET,
1058  USBDEV_USBSTAT_LINK_STATE_VALUE_POWERED_SUSPENDED},
1059  });
1060  EXPECT_DIF_OK(dif_usbdev_status_get_link_state(&usbdev_, &link_state));
1061  EXPECT_EQ(link_state, kDifUsbdevLinkStatePoweredSuspended);
1062 
1063  EXPECT_READ32(USBDEV_USBSTAT_REG_OFFSET,
1064  {
1065  {USBDEV_USBSTAT_SENSE_BIT, 1},
1066  {USBDEV_USBSTAT_LINK_STATE_OFFSET,
1067  USBDEV_USBSTAT_LINK_STATE_VALUE_SUSPENDED},
1068  });
1069  EXPECT_DIF_OK(dif_usbdev_status_get_link_state(&usbdev_, &link_state));
1070  EXPECT_EQ(link_state, kDifUsbdevLinkStateSuspended);
1071 
1072  EXPECT_READ32(USBDEV_USBSTAT_REG_OFFSET,
1073  {
1074  {USBDEV_USBSTAT_SENSE_BIT, 1},
1075  {USBDEV_USBSTAT_LINK_STATE_OFFSET,
1076  USBDEV_USBSTAT_LINK_STATE_VALUE_ACTIVE_NOSOF},
1077  });
1078  EXPECT_DIF_OK(dif_usbdev_status_get_link_state(&usbdev_, &link_state));
1079  EXPECT_EQ(link_state, kDifUsbdevLinkStateActiveNoSof);
1080 
1081  EXPECT_READ32(USBDEV_USBSTAT_REG_OFFSET,
1082  {
1083  {USBDEV_USBSTAT_SENSE_BIT, 1},
1084  {USBDEV_USBSTAT_LINK_STATE_OFFSET,
1085  USBDEV_USBSTAT_LINK_STATE_VALUE_RESUMING},
1086  });
1087  EXPECT_DIF_OK(dif_usbdev_status_get_link_state(&usbdev_, &link_state));
1088  EXPECT_EQ(link_state, kDifUsbdevLinkStateResuming);
1089 }
1090 
1091 TEST_F(UsbdevTest, WakeFromSleep) {
1092  EXPECT_WRITE32(USBDEV_WAKE_CONTROL_REG_OFFSET,
1093  {{USBDEV_WAKE_CONTROL_SUSPEND_REQ_BIT, 1}});
1094  EXPECT_DIF_OK(dif_usbdev_set_wake_enable(&usbdev_, kDifToggleEnabled));
1095 
1096  dif_usbdev_wake_status_t wake_status;
1097  EXPECT_READ32(USBDEV_WAKE_EVENTS_REG_OFFSET,
1098  {
1099  {USBDEV_WAKE_EVENTS_MODULE_ACTIVE_BIT, 1},
1100  {USBDEV_WAKE_EVENTS_DISCONNECTED_BIT, 0},
1101  {USBDEV_WAKE_EVENTS_BUS_RESET_BIT, 1},
1102  });
1103  EXPECT_DIF_OK(dif_usbdev_get_wake_status(&usbdev_, &wake_status));
1104  EXPECT_TRUE(wake_status.active);
1105  EXPECT_FALSE(wake_status.disconnected);
1106  EXPECT_TRUE(wake_status.bus_reset);
1107 
1108  EXPECT_READ32(USBDEV_USBCTRL_REG_OFFSET,
1109  {
1110  {USBDEV_USBCTRL_ENABLE_BIT, 1},
1111  {USBDEV_USBCTRL_DEVICE_ADDRESS_OFFSET, 88},
1112  {USBDEV_USBCTRL_RESUME_LINK_ACTIVE_BIT, 0},
1113  });
1114  EXPECT_WRITE32(USBDEV_USBCTRL_REG_OFFSET,
1115  {
1116  {USBDEV_USBCTRL_ENABLE_BIT, 1},
1117  {USBDEV_USBCTRL_DEVICE_ADDRESS_OFFSET, 88},
1118  {USBDEV_USBCTRL_RESUME_LINK_ACTIVE_BIT, 1},
1119  });
1120  EXPECT_DIF_OK(dif_usbdev_resume_link_to_active(&usbdev_));
1121 
1122  EXPECT_WRITE32(USBDEV_WAKE_CONTROL_REG_OFFSET,
1123  {{USBDEV_WAKE_CONTROL_WAKE_ACK_BIT, 1}});
1124  EXPECT_DIF_OK(dif_usbdev_set_wake_enable(&usbdev_, kDifToggleDisabled));
1125 }
1126 
1127 } // namespace
1128 } // namespace dif_usbdev_unittest
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