Software APIs
dif_uart_unittest.cc
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 #include "sw/device/lib/dif/dif_uart.h"
6 
7 #include "gtest/gtest.h"
8 #include "sw/device/lib/base/mmio.h"
9 #include "sw/device/lib/base/mock_mmio.h"
10 #include "sw/device/lib/dif/dif_test_base.h"
11 
12 #include "uart_regs.h" // Generated.
13 
14 namespace dif_uart_unittest {
15 namespace {
16 using mock_mmio::MmioTest;
17 using mock_mmio::MockDevice;
18 using testing::Each;
19 using testing::Eq;
20 using testing::Test;
21 
22 const std::vector<uint8_t> kBytesArray = {
23  '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'a',
24  'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l',
25  'm', 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v',
26 };
27 
28 class UartTest : public Test, public MmioTest {
29  protected:
30  void ExpectDeviceReset() {
31  EXPECT_WRITE32(UART_CTRL_REG_OFFSET, 0);
32  EXPECT_WRITE32(UART_FIFO_CTRL_REG_OFFSET,
33  {
34  {UART_FIFO_CTRL_RXRST_BIT, true},
35  {UART_FIFO_CTRL_TXRST_BIT, true},
36  });
37  EXPECT_WRITE32(UART_OVRD_REG_OFFSET, 0);
38  EXPECT_WRITE32(UART_TIMEOUT_CTRL_REG_OFFSET, 0);
39  EXPECT_WRITE32(UART_INTR_ENABLE_REG_OFFSET, 0);
40  EXPECT_WRITE32(UART_INTR_STATE_REG_OFFSET,
41  std::numeric_limits<uint32_t>::max());
42  }
43 
44  dif_uart_t uart_ = {
45  .base_addr = dev().region(),
46  };
47 
48  // NCO is calculated as NCO = 2^20 * fbaud / fpclk, so the following values
49  // should result in NCO of 1. This is the default configuration, which will
50  // be used unless the values are overridden.
51  dif_uart_config_t config_ = {
52  .baudrate = 1,
53  .clk_freq_hz = 1048576,
54  .parity_enable = kDifToggleDisabled,
55  .parity = kDifUartParityEven,
56  .tx_enable = kDifToggleEnabled,
57  .rx_enable = kDifToggleEnabled,
58  };
59 };
60 
61 class ConfigTest : public UartTest {};
62 
63 TEST_F(ConfigTest, NullArgs) {
64  EXPECT_DIF_BADARG(dif_uart_configure(nullptr, config_));
65 }
66 
67 TEST_F(ConfigTest, BadRxBreakLevel) {
68  dif_uart_config_t config = config_;
69  config.rx_break_level = (dif_uart_rx_break_level_t)5;
70  EXPECT_DIF_BADARG(dif_uart_configure(&uart_, config));
71 }
72 
73 TEST_F(ConfigTest, DefaultTxRxEnabled) {
74  ExpectDeviceReset();
75  EXPECT_WRITE32(UART_CTRL_REG_OFFSET, {
76  {UART_CTRL_TX_BIT, true},
77  {UART_CTRL_RX_BIT, true},
78  {UART_CTRL_NCO_OFFSET, 1},
79  });
80  EXPECT_WRITE32(UART_INTR_ENABLE_REG_OFFSET, 0);
81  EXPECT_DIF_OK(dif_uart_configure(&uart_, config_));
82 }
83 
84 TEST_F(ConfigTest, DefaultTxEnabled) {
85  ExpectDeviceReset();
86  EXPECT_WRITE32(UART_CTRL_REG_OFFSET, {
87  {UART_CTRL_TX_BIT, true},
88  {UART_CTRL_NCO_OFFSET, 1},
89  });
90  EXPECT_WRITE32(UART_INTR_ENABLE_REG_OFFSET, 0);
91  config_.rx_enable = kDifToggleDisabled;
92  EXPECT_DIF_OK(dif_uart_configure(&uart_, config_));
93 }
94 
95 TEST_F(ConfigTest, DefaultRxEnabled) {
96  ExpectDeviceReset();
97  EXPECT_WRITE32(UART_CTRL_REG_OFFSET, {
98  {UART_CTRL_RX_BIT, true},
99  {UART_CTRL_NCO_OFFSET, 1},
100  });
101  EXPECT_WRITE32(UART_INTR_ENABLE_REG_OFFSET, 0);
102  config_.tx_enable = kDifToggleDisabled;
103  EXPECT_DIF_OK(dif_uart_configure(&uart_, config_));
104 }
105 
106 TEST_F(ConfigTest, DefaultTxRxDisabled) {
107  ExpectDeviceReset();
108  EXPECT_WRITE32(UART_CTRL_REG_OFFSET, {{UART_CTRL_NCO_OFFSET, 1}});
109  EXPECT_WRITE32(UART_INTR_ENABLE_REG_OFFSET, 0);
110  config_.tx_enable = kDifToggleDisabled;
111  config_.rx_enable = kDifToggleDisabled;
112  EXPECT_DIF_OK(dif_uart_configure(&uart_, config_));
113 }
114 
115 TEST_F(ConfigTest, ParityEven) {
116  config_.parity_enable = kDifToggleEnabled;
117  config_.parity = kDifUartParityEven;
118 
119  ExpectDeviceReset();
120 
121  EXPECT_WRITE32(UART_CTRL_REG_OFFSET, {
122  {UART_CTRL_TX_BIT, true},
123  {UART_CTRL_RX_BIT, true},
124  {UART_CTRL_PARITY_EN_BIT, true},
125  {UART_CTRL_NCO_OFFSET, 1},
126  });
127 
128  EXPECT_WRITE32(UART_INTR_ENABLE_REG_OFFSET, 0);
129 
130  EXPECT_DIF_OK(dif_uart_configure(&uart_, config_));
131 }
132 
133 TEST_F(ConfigTest, ParityOdd) {
134  config_.parity_enable = kDifToggleEnabled;
135  config_.parity = kDifUartParityOdd;
136 
137  ExpectDeviceReset();
138 
139  EXPECT_WRITE32(UART_CTRL_REG_OFFSET, {
140  {UART_CTRL_TX_BIT, true},
141  {UART_CTRL_RX_BIT, true},
142  {UART_CTRL_PARITY_EN_BIT, true},
143  {UART_CTRL_PARITY_ODD_BIT, true},
144  {UART_CTRL_NCO_OFFSET, 1},
145  });
146 
147  EXPECT_WRITE32(UART_INTR_ENABLE_REG_OFFSET, 0);
148 
149  EXPECT_DIF_OK(dif_uart_configure(&uart_, config_));
150 }
151 
152 class RxBreakLevelSetTest : public UartTest {};
153 
154 TEST_F(RxBreakLevelSetTest, UartNull) {
155  EXPECT_DIF_BADARG(
156  dif_uart_rx_break_level_set(nullptr, kDifUartRxBreakLevel2));
157 }
158 
159 TEST_F(RxBreakLevelSetTest, Success) {
160  EXPECT_MASK32(UART_CTRL_REG_OFFSET,
161  {
162  {UART_CTRL_RXBLVL_OFFSET, UART_CTRL_RXBLVL_MASK,
163  UART_CTRL_RXBLVL_VALUE_BREAK2},
164  });
165  EXPECT_DIF_OK(dif_uart_rx_break_level_set(&uart_, kDifUartRxBreakLevel2));
166 
167  EXPECT_MASK32(UART_CTRL_REG_OFFSET,
168  {
169  {UART_CTRL_RXBLVL_OFFSET, UART_CTRL_RXBLVL_MASK,
170  UART_CTRL_RXBLVL_VALUE_BREAK16},
171  });
172  EXPECT_DIF_OK(dif_uart_rx_break_level_set(&uart_, kDifUartRxBreakLevel16));
173 }
174 
175 class WatermarkRxSetTest : public UartTest {};
176 
177 TEST_F(WatermarkRxSetTest, UartNull) {
178  dif_result_t result =
179  dif_uart_watermark_rx_set(nullptr, kDifUartWatermarkByte1);
180  EXPECT_DIF_BADARG(result);
181 }
182 
183 /**
184  * Tests the first and the last RX watermark variants.
185  */
186 TEST_F(WatermarkRxSetTest, Success) {
187  EXPECT_MASK32(UART_FIFO_CTRL_REG_OFFSET,
188  {
189  {UART_FIFO_CTRL_RXILVL_OFFSET, UART_FIFO_CTRL_RXILVL_MASK,
190  UART_FIFO_CTRL_RXILVL_VALUE_RXLVL1},
191  });
192  EXPECT_DIF_OK(dif_uart_watermark_rx_set(&uart_, kDifUartWatermarkByte1));
193 
194  EXPECT_MASK32(UART_FIFO_CTRL_REG_OFFSET,
195  {
196  {UART_FIFO_CTRL_RXILVL_OFFSET, UART_FIFO_CTRL_RXILVL_MASK,
197  UART_FIFO_CTRL_RXILVL_VALUE_RXLVL62},
198  });
199  EXPECT_DIF_OK(dif_uart_watermark_rx_set(&uart_, kDifUartWatermarkByte62));
200 }
201 
202 class WatermarkTxSetTest : public UartTest {};
203 
204 TEST_F(WatermarkTxSetTest, NullArgs) {
205  EXPECT_DIF_BADARG(dif_uart_watermark_tx_set(nullptr, kDifUartWatermarkByte1));
206 }
207 
208 TEST_F(WatermarkTxSetTest, InvalidWatermark) {
209  EXPECT_EQ(dif_uart_watermark_tx_set(&uart_, kDifUartWatermarkByte62),
210  kDifError);
211 }
212 
213 /**
214  * Tests the first and the last TX watermark variants.
215  */
216 TEST_F(WatermarkTxSetTest, Success) {
217  EXPECT_MASK32(UART_FIFO_CTRL_REG_OFFSET,
218  {
219  {UART_FIFO_CTRL_TXILVL_OFFSET, UART_FIFO_CTRL_TXILVL_MASK,
220  UART_FIFO_CTRL_TXILVL_VALUE_TXLVL1},
221  });
222  EXPECT_DIF_OK(dif_uart_watermark_tx_set(&uart_, kDifUartWatermarkByte1));
223 
224  EXPECT_MASK32(UART_FIFO_CTRL_REG_OFFSET,
225  {
226  {UART_FIFO_CTRL_TXILVL_OFFSET, UART_FIFO_CTRL_TXILVL_MASK,
227  UART_FIFO_CTRL_TXILVL_VALUE_TXLVL16},
228  });
229  EXPECT_DIF_OK(dif_uart_watermark_tx_set(&uart_, kDifUartWatermarkByte16));
230 }
231 
232 class SetEnableTest : public UartTest {};
233 
234 TEST_F(SetEnableTest, NullArg) {
235  EXPECT_DIF_BADARG(
236  dif_uart_set_enable(nullptr, kDifUartDatapathAll, kDifToggleEnabled));
237 }
238 
239 TEST_F(SetEnableTest, BadEnabled) {
240  EXPECT_DIF_BADARG(dif_uart_set_enable(&uart_, kDifUartDatapathAll,
241  static_cast<dif_toggle_t>(2)));
242 }
243 
244 TEST_F(SetEnableTest, BadDatapath) {
245  EXPECT_READ32(UART_CTRL_REG_OFFSET, 0);
246  EXPECT_DIF_BADARG(dif_uart_set_enable(
247  &uart_, static_cast<dif_uart_datapath_t>(kDifUartDatapathAll + 1),
248  kDifToggleEnabled));
249 }
250 
251 TEST_F(SetEnableTest, SuccessRxEnabledDisabled) {
252  EXPECT_READ32(UART_CTRL_REG_OFFSET, {
253  {UART_CTRL_RX_BIT, 0},
254  {UART_CTRL_TX_BIT, 1},
255  });
256  EXPECT_WRITE32(UART_CTRL_REG_OFFSET, {
257  {UART_CTRL_RX_BIT, 1},
258  {UART_CTRL_TX_BIT, 1},
259  });
260  EXPECT_DIF_OK(
261  dif_uart_set_enable(&uart_, kDifUartDatapathRx, kDifToggleEnabled));
262 
263  EXPECT_READ32(UART_CTRL_REG_OFFSET, {
264  {UART_CTRL_RX_BIT, 1},
265  {UART_CTRL_TX_BIT, 1},
266  });
267  EXPECT_WRITE32(UART_CTRL_REG_OFFSET, {
268  {UART_CTRL_RX_BIT, 0},
269  {UART_CTRL_TX_BIT, 1},
270  });
271  EXPECT_DIF_OK(
272  dif_uart_set_enable(&uart_, kDifUartDatapathRx, kDifToggleDisabled));
273 }
274 
275 TEST_F(SetEnableTest, SuccessTxEnabledDisabled) {
276  EXPECT_READ32(UART_CTRL_REG_OFFSET, {
277  {UART_CTRL_RX_BIT, 1},
278  {UART_CTRL_TX_BIT, 0},
279  });
280  EXPECT_WRITE32(UART_CTRL_REG_OFFSET, {
281  {UART_CTRL_RX_BIT, 1},
282  {UART_CTRL_TX_BIT, 1},
283  });
284  EXPECT_DIF_OK(
285  dif_uart_set_enable(&uart_, kDifUartDatapathTx, kDifToggleEnabled));
286 
287  EXPECT_READ32(UART_CTRL_REG_OFFSET, {
288  {UART_CTRL_RX_BIT, 1},
289  {UART_CTRL_TX_BIT, 1},
290  });
291  EXPECT_WRITE32(UART_CTRL_REG_OFFSET, {
292  {UART_CTRL_RX_BIT, 1},
293  {UART_CTRL_TX_BIT, 0},
294  });
295  EXPECT_DIF_OK(
296  dif_uart_set_enable(&uart_, kDifUartDatapathTx, kDifToggleDisabled));
297 }
298 
299 TEST_F(SetEnableTest, SuccessRxTxEnabledDisabled) {
300  EXPECT_READ32(UART_CTRL_REG_OFFSET, {
301  {UART_CTRL_RX_BIT, 0},
302  {UART_CTRL_TX_BIT, 0},
303  });
304  EXPECT_WRITE32(UART_CTRL_REG_OFFSET, {
305  {UART_CTRL_RX_BIT, 1},
306  {UART_CTRL_TX_BIT, 1},
307  });
308  EXPECT_DIF_OK(
309  dif_uart_set_enable(&uart_, kDifUartDatapathAll, kDifToggleEnabled));
310 
311  EXPECT_READ32(UART_CTRL_REG_OFFSET, {
312  {UART_CTRL_RX_BIT, 1},
313  {UART_CTRL_TX_BIT, 1},
314  });
315  EXPECT_WRITE32(UART_CTRL_REG_OFFSET, {
316  {UART_CTRL_RX_BIT, 0},
317  {UART_CTRL_TX_BIT, 0},
318  });
319  EXPECT_DIF_OK(
320  dif_uart_set_enable(&uart_, kDifUartDatapathAll, kDifToggleDisabled));
321 }
322 
323 class BytesSendTest : public UartTest {
324  protected:
325  /**
326  * Sets TX bytes expectations.
327  *
328  * Every sent byte by the "send bytes" routine is expected to result in the
329  * STATUS read of 0 (FIFO not full), and write to WDATA.
330  */
331  void ExpectSendBytes(int num_elements = kBytesArray.size()) {
332  ASSERT_LE(num_elements, kBytesArray.size());
333  for (int i = 0; i < num_elements; ++i) {
334  uint32_t value = static_cast<uint32_t>(kBytesArray[i]);
335  EXPECT_READ32(UART_STATUS_REG_OFFSET, 0);
336  EXPECT_WRITE32(UART_WDATA_REG_OFFSET, value);
337  }
338  }
339 };
340 
341 TEST_F(BytesSendTest, NullArgs) {
342  EXPECT_DIF_BADARG(
343  dif_uart_bytes_send(nullptr, kBytesArray.data(), 1, nullptr));
344 
345  EXPECT_DIF_BADARG(dif_uart_bytes_send(&uart_, nullptr, 1, nullptr));
346 
347  EXPECT_DIF_BADARG(dif_uart_bytes_send(nullptr, nullptr, 1, nullptr));
348 }
349 
350 TEST_F(BytesSendTest, TxFifoEmptyBytesWrittenNull) {
351  ExpectSendBytes();
352  EXPECT_DIF_OK(dif_uart_bytes_send(&uart_, kBytesArray.data(),
353  kBytesArray.size(), nullptr));
354 }
355 
356 TEST_F(BytesSendTest, TxFifoEmpty) {
357  ExpectSendBytes();
358 
359  size_t bytes_written;
360  EXPECT_DIF_OK(dif_uart_bytes_send(&uart_, kBytesArray.data(),
361  kBytesArray.size(), &bytes_written));
362  EXPECT_EQ(bytes_written, kBytesArray.size());
363 }
364 
365 TEST_F(BytesSendTest, TxFifoFull) {
366  EXPECT_READ32(UART_STATUS_REG_OFFSET, {{UART_STATUS_TXFULL_BIT, true}});
367 
368  size_t bytes_written;
369  EXPECT_DIF_OK(dif_uart_bytes_send(&uart_, kBytesArray.data(),
370  kBytesArray.size(), &bytes_written));
371  EXPECT_EQ(bytes_written, 0);
372 }
373 
374 class BytesReceiveTest : public UartTest {
375  protected:
376  /**
377  * Sets RX bytes expectations.
378  *
379  * Every read byte by the "receive bytes" routine is expected to result in the
380  * STATUS read of 0 (FIFO not empty), and read of RDATA.
381  */
382  void ExpectReceiveBytes(int num_elements) {
383  for (int i = 0; i < num_elements; ++i) {
384  uint32_t value = static_cast<uint32_t>(kBytesArray[i]);
385  EXPECT_READ32(UART_STATUS_REG_OFFSET, 0);
386  EXPECT_READ32(UART_RDATA_REG_OFFSET, value);
387  }
388  }
389 };
390 
391 TEST_F(BytesReceiveTest, UartNull) {
392  std::vector<uint8_t> receive_bytes(1);
393 
394  EXPECT_DIF_BADARG(
395  dif_uart_bytes_receive(nullptr, 1, receive_bytes.data(), nullptr));
396  EXPECT_THAT(receive_bytes, Each(Eq(0)));
397 
398  EXPECT_DIF_BADARG(dif_uart_bytes_receive(&uart_, 1, nullptr, nullptr));
399 
400  EXPECT_DIF_BADARG(dif_uart_bytes_receive(nullptr, 1, nullptr, nullptr));
401 }
402 
403 TEST_F(BytesReceiveTest, RxFifoFullBytesWrittenNull) {
404  uint8_t num_bytes = kBytesArray.size();
405  ExpectReceiveBytes(num_bytes);
406 
407  std::vector<uint8_t> receive_bytes(num_bytes);
408  EXPECT_DIF_OK(
409  dif_uart_bytes_receive(&uart_, num_bytes, receive_bytes.data(), nullptr));
410  EXPECT_EQ(receive_bytes, kBytesArray);
411 }
412 
413 TEST_F(BytesReceiveTest, RxFifoFull) {
414  uint8_t num_bytes = kBytesArray.size();
415  ExpectReceiveBytes(num_bytes);
416 
417  size_t bytes_read;
418  std::vector<uint8_t> receive_bytes(num_bytes);
419  EXPECT_DIF_OK(dif_uart_bytes_receive(&uart_, num_bytes, receive_bytes.data(),
420  &bytes_read));
421  EXPECT_EQ(bytes_read, num_bytes);
422  EXPECT_EQ(receive_bytes, kBytesArray);
423 }
424 
425 TEST_F(BytesReceiveTest, RxFifoEmpty) {
426  EXPECT_READ32(UART_STATUS_REG_OFFSET, {{UART_STATUS_RXEMPTY_BIT, true}});
427 
428  uint8_t num_bytes = kBytesArray.size();
429 
430  size_t bytes_read;
431  std::vector<uint8_t> receive_bytes(num_bytes);
432  EXPECT_DIF_OK(dif_uart_bytes_receive(&uart_, num_bytes, receive_bytes.data(),
433  &bytes_read));
434  EXPECT_EQ(bytes_read, 0);
435  EXPECT_THAT(receive_bytes, Each(Eq(0)));
436 }
437 
438 class BytesSendPolledTest : public UartTest {};
439 
440 TEST_F(BytesSendPolledTest, NullArgs) {
441  dif_result_t result = dif_uart_byte_send_polled(nullptr, 'X');
442  EXPECT_DIF_BADARG(result);
443 }
444 
445 TEST_F(BytesSendPolledTest, Success) {
446  // Busy loop 1 iteration (waiting for TX FIFO to free up)
447  EXPECT_READ32(UART_STATUS_REG_OFFSET, {{UART_STATUS_TXFULL_BIT, true}});
448  EXPECT_READ32(UART_STATUS_REG_OFFSET, {{UART_STATUS_TXFULL_BIT, false}});
449 
450  // Set expectations for the byte to be set
451  EXPECT_READ32(UART_STATUS_REG_OFFSET, {{UART_STATUS_TXFULL_BIT, false}});
452  EXPECT_WRITE32(UART_WDATA_REG_OFFSET, 'X');
453 
454  // Busy loop 1 iteration (waiting for the byte to be sent out by the HW)
455  EXPECT_READ32(UART_STATUS_REG_OFFSET, {{UART_STATUS_TXIDLE_BIT, false}});
456  EXPECT_READ32(UART_STATUS_REG_OFFSET, {{UART_STATUS_TXIDLE_BIT, true}});
457 
458  EXPECT_DIF_OK(dif_uart_byte_send_polled(&uart_, 'X'));
459 }
460 
461 class BytesReceivePolledTest : public UartTest {};
462 
463 TEST_F(BytesReceivePolledTest, NullArgs) {
464  uint8_t byte;
465  EXPECT_DIF_BADARG(dif_uart_byte_receive_polled(nullptr, &byte));
466 
467  EXPECT_DIF_BADARG(dif_uart_byte_receive_polled(&uart_, nullptr));
468 
469  EXPECT_DIF_BADARG(dif_uart_byte_receive_polled(nullptr, nullptr));
470 }
471 
472 TEST_F(BytesReceivePolledTest, Success) {
473  // Busy loop 1 iteration (waiting for RX FIFO to fill up)
474  EXPECT_READ32(UART_STATUS_REG_OFFSET, {{UART_STATUS_RXEMPTY_BIT, true}});
475  EXPECT_READ32(UART_STATUS_REG_OFFSET, {{UART_STATUS_RXEMPTY_BIT, false}});
476 
477  // Set expectations for the byte to be read
478  EXPECT_READ32(UART_STATUS_REG_OFFSET, {{UART_STATUS_RXEMPTY_BIT, false}});
479  EXPECT_READ32(UART_RDATA_REG_OFFSET, 'X');
480 
481  uint8_t byte = 'Y';
482  EXPECT_DIF_OK(dif_uart_byte_receive_polled(&uart_, &byte));
483  EXPECT_EQ(byte, 'X');
484 }
485 
486 class RxBytesAvailableTest : public UartTest {};
487 
488 TEST_F(RxBytesAvailableTest, NullArgs) {
489  size_t num_bytes;
490  EXPECT_DIF_BADARG(dif_uart_rx_bytes_available(nullptr, &num_bytes));
491 
492  EXPECT_DIF_BADARG(dif_uart_rx_bytes_available(&uart_, nullptr));
493 
494  EXPECT_DIF_BADARG(dif_uart_rx_bytes_available(nullptr, nullptr));
495 }
496 
497 TEST_F(RxBytesAvailableTest, FifoFull) {
498  // kDifUartFifoSizeBytes bytes available to read.
499  EXPECT_READ32(UART_FIFO_STATUS_REG_OFFSET,
500  {{UART_FIFO_STATUS_RXLVL_OFFSET, kDifUartFifoSizeBytes}});
501 
502  size_t num_bytes;
503  EXPECT_DIF_OK(dif_uart_rx_bytes_available(&uart_, &num_bytes));
504  EXPECT_EQ(num_bytes, kDifUartFifoSizeBytes);
505 }
506 
507 TEST_F(RxBytesAvailableTest, FifoEmpty) {
508  // 0 bytes available to read.
509  EXPECT_READ32(UART_FIFO_STATUS_REG_OFFSET,
510  {{UART_FIFO_STATUS_RXLVL_OFFSET, 0}});
511 
512  size_t num_bytes;
513  EXPECT_DIF_OK(dif_uart_rx_bytes_available(&uart_, &num_bytes));
514  EXPECT_EQ(num_bytes, 0);
515 }
516 
517 class TxBytesAvailableTest : public UartTest {};
518 
519 TEST_F(TxBytesAvailableTest, NullArgs) {
520  size_t num_bytes;
521  EXPECT_DIF_BADARG(dif_uart_tx_bytes_available(nullptr, &num_bytes));
522 
523  EXPECT_DIF_BADARG(dif_uart_tx_bytes_available(&uart_, nullptr));
524 
525  EXPECT_DIF_BADARG(dif_uart_tx_bytes_available(nullptr, nullptr));
526 }
527 
528 TEST_F(TxBytesAvailableTest, FifoFull) {
529  // 0 bytes available to write.
530  EXPECT_READ32(UART_FIFO_STATUS_REG_OFFSET,
531  {{UART_FIFO_STATUS_TXLVL_OFFSET, kDifUartFifoSizeBytes}});
532 
533  size_t num_bytes;
534  EXPECT_DIF_OK(dif_uart_tx_bytes_available(&uart_, &num_bytes));
535  EXPECT_EQ(num_bytes, 0);
536 }
537 
538 TEST_F(TxBytesAvailableTest, FifoEmpty) {
539  // kDifUartFifoSizeBytes available to write.
540  EXPECT_READ32(UART_FIFO_STATUS_REG_OFFSET,
541  {{UART_FIFO_STATUS_TXLVL_OFFSET, 0}});
542 
543  size_t num_bytes;
544  EXPECT_DIF_OK(dif_uart_tx_bytes_available(&uart_, &num_bytes));
545  EXPECT_EQ(num_bytes, kDifUartFifoSizeBytes);
546 }
547 
548 class FifoResetTest : public UartTest {};
549 
550 TEST_F(FifoResetTest, NullArgs) {
551  dif_result_t result = dif_uart_fifo_reset(nullptr, kDifUartDatapathRx);
552  EXPECT_DIF_BADARG(result);
553 }
554 
555 TEST_F(FifoResetTest, Success) {
556  EXPECT_READ32(UART_FIFO_CTRL_REG_OFFSET, 0);
557  EXPECT_WRITE32(UART_FIFO_CTRL_REG_OFFSET, {{UART_FIFO_CTRL_RXRST_BIT, true}});
558  EXPECT_DIF_OK(dif_uart_fifo_reset(&uart_, kDifUartDatapathRx));
559 
560  EXPECT_READ32(UART_FIFO_CTRL_REG_OFFSET, 0);
561  EXPECT_WRITE32(UART_FIFO_CTRL_REG_OFFSET, {{UART_FIFO_CTRL_TXRST_BIT, true}});
562  EXPECT_DIF_OK(dif_uart_fifo_reset(&uart_, kDifUartDatapathTx));
563 
564  EXPECT_READ32(UART_FIFO_CTRL_REG_OFFSET, 0);
565  EXPECT_WRITE32(UART_FIFO_CTRL_REG_OFFSET,
566  {
567  {UART_FIFO_CTRL_RXRST_BIT, true},
568  {UART_FIFO_CTRL_TXRST_BIT, true},
569  });
570  EXPECT_DIF_OK(dif_uart_fifo_reset(&uart_, kDifUartDatapathAll));
571 }
572 
573 class LoopbackSetTest : public UartTest {};
574 
575 TEST_F(LoopbackSetTest, NullArgs) {
576  EXPECT_DIF_BADARG(dif_uart_loopback_set(nullptr, kDifUartLoopbackSystem,
577  kDifToggleEnabled));
578 }
579 
580 TEST_F(LoopbackSetTest, Success) {
581  EXPECT_MASK32(UART_CTRL_REG_OFFSET, {{UART_CTRL_SLPBK_BIT, 0x1, true}});
582  EXPECT_DIF_OK(
583  dif_uart_loopback_set(&uart_, kDifUartLoopbackSystem, kDifToggleEnabled));
584 
585  EXPECT_MASK32(UART_CTRL_REG_OFFSET, {{UART_CTRL_SLPBK_BIT, 0x1, false}});
586  EXPECT_DIF_OK(dif_uart_loopback_set(&uart_, kDifUartLoopbackSystem,
587  kDifToggleDisabled));
588 
589  EXPECT_MASK32(UART_CTRL_REG_OFFSET, {{UART_CTRL_LLPBK_BIT, 0x1, true}});
590  EXPECT_DIF_OK(
591  dif_uart_loopback_set(&uart_, kDifUartLoopbackLine, kDifToggleEnabled));
592 
593  EXPECT_MASK32(UART_CTRL_REG_OFFSET, {{UART_CTRL_LLPBK_BIT, 0x1, false}});
594  EXPECT_DIF_OK(
595  dif_uart_loopback_set(&uart_, kDifUartLoopbackLine, kDifToggleDisabled));
596 }
597 
598 class RxTimeoutTest : public UartTest {};
599 
600 TEST_F(RxTimeoutTest, NullArgs) {
601  EXPECT_DIF_BADARG(dif_uart_enable_rx_timeout(nullptr, 1));
602  EXPECT_DIF_BADARG(dif_uart_disable_rx_timeout(nullptr));
603 
604  uint32_t value; // optional
605  dif_toggle_t status; // mandatory
606  EXPECT_DIF_BADARG(dif_uart_get_rx_timeout(nullptr, &status, &value));
607  EXPECT_DIF_BADARG(dif_uart_get_rx_timeout(&uart_, nullptr, &value));
608 }
609 
610 TEST_F(RxTimeoutTest, OutOfRange) {
611  // RX timeout value must be in the range [0,0xffffff].
612  EXPECT_DIF_BADARG(dif_uart_enable_rx_timeout(&uart_, 0x01000000));
613  EXPECT_DIF_BADARG(dif_uart_enable_rx_timeout(&uart_, 0xffffffff));
614 }
615 
616 TEST_F(RxTimeoutTest, Enable) {
617  // Enable RX timeout and set to 0x123.
618  const uint32_t duration = 0x123;
619  EXPECT_WRITE32(UART_TIMEOUT_CTRL_REG_OFFSET,
620  {{UART_TIMEOUT_CTRL_VAL_OFFSET, duration},
621  {UART_TIMEOUT_CTRL_EN_BIT, true}});
622  EXPECT_DIF_OK(dif_uart_enable_rx_timeout(&uart_, duration));
623 }
624 
625 TEST_F(RxTimeoutTest, Disable) {
626  // Disable RX timeout.
627  EXPECT_WRITE32(
628  UART_TIMEOUT_CTRL_REG_OFFSET,
629  {{UART_TIMEOUT_CTRL_VAL_OFFSET, 0}, {UART_TIMEOUT_CTRL_EN_BIT, false}});
630  EXPECT_DIF_OK(dif_uart_disable_rx_timeout(&uart_));
631 }
632 
633 TEST_F(RxTimeoutTest, GetStatusOnly) {
634  // Enable RX timeout and set to 0x800000.
635  const uint32_t duration = 0x800000;
636  EXPECT_WRITE32(UART_TIMEOUT_CTRL_REG_OFFSET,
637  {{UART_TIMEOUT_CTRL_VAL_OFFSET, duration},
638  {UART_TIMEOUT_CTRL_EN_BIT, true}});
639  EXPECT_DIF_OK(dif_uart_enable_rx_timeout(&uart_, duration));
640 
641  // Read out status only.
642  dif_toggle_t status = kDifToggleDisabled;
643  EXPECT_READ32(UART_TIMEOUT_CTRL_REG_OFFSET,
644  {{UART_TIMEOUT_CTRL_VAL_OFFSET, duration},
645  {UART_TIMEOUT_CTRL_EN_BIT, true}});
646  EXPECT_DIF_OK(dif_uart_get_rx_timeout(&uart_, &status, nullptr));
647  EXPECT_EQ(status, kDifToggleEnabled);
648 }
649 
650 TEST_F(RxTimeoutTest, GetAll) {
651  // Enable RX timeout and set to 0xf0f0f0.
652  const uint32_t duration = 0xf0f0f0;
653  EXPECT_WRITE32(UART_TIMEOUT_CTRL_REG_OFFSET,
654  {{UART_TIMEOUT_CTRL_VAL_OFFSET, duration},
655  {UART_TIMEOUT_CTRL_EN_BIT, true}});
656  EXPECT_DIF_OK(dif_uart_enable_rx_timeout(&uart_, duration));
657 
658  // Read out duration and status.
659  uint32_t out = 0;
660  dif_toggle_t status = kDifToggleDisabled;
661  EXPECT_READ32(UART_TIMEOUT_CTRL_REG_OFFSET,
662  {{UART_TIMEOUT_CTRL_VAL_OFFSET, duration},
663  {UART_TIMEOUT_CTRL_EN_BIT, true}});
664  EXPECT_DIF_OK(dif_uart_get_rx_timeout(&uart_, &status, &out));
665  EXPECT_EQ(status, kDifToggleEnabled);
666  EXPECT_EQ(out, duration);
667 }
668 
669 } // namespace
670 } // namespace dif_uart_unittest
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