7 #include "gtest/gtest.h"
9 #include "sw/device/lib/base/mock_mmio.h"
13 #include "sysrst_ctrl_regs.h"
15 namespace dif_sysrst_ctrl_unittest {
17 using ::mock_mmio::LeInt;
18 using ::mock_mmio::MmioTest;
19 using ::mock_mmio::MockDevice;
23 dif_sysrst_ctrl_t sysrst_ctrl_ = {.base_addr = dev().region()};
30 .pre_condition_detection_time_threshold = 0x1000,
32 .detection_time_threshold = 0x5000,
34 .embedded_controller_reset_duration = 0x100,
43 TEST_F(KeyComboDetectConfigTest, BadArgs) {
49 config_.pre_condition_keys = 1U << 5;
55 config_.keys = 1U << 5;
66 TEST_F(KeyComboDetectConfigTest, Locked) {
67 EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 0);
73 TEST_F(KeyComboDetectConfigTest, SuccessWithoutEcReset) {
77 EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 1);
78 EXPECT_WRITE32(SYSRST_CTRL_COM_PRE_SEL_CTL_1_REG_OFFSET,
79 config_.pre_condition_keys);
80 EXPECT_WRITE32(SYSRST_CTRL_COM_PRE_DET_CTL_1_REG_OFFSET,
81 config_.pre_condition_detection_time_threshold);
82 EXPECT_WRITE32(SYSRST_CTRL_COM_SEL_CTL_1_REG_OFFSET, config_.keys);
83 EXPECT_WRITE32(SYSRST_CTRL_COM_DET_CTL_1_REG_OFFSET,
84 config_.detection_time_threshold);
85 EXPECT_WRITE32(SYSRST_CTRL_COM_OUT_CTL_1_REG_OFFSET, config_.actions);
91 TEST_F(KeyComboDetectConfigTest, SuccessWithEcReset) {
92 EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 1);
93 EXPECT_WRITE32(SYSRST_CTRL_COM_PRE_SEL_CTL_1_REG_OFFSET,
94 config_.pre_condition_keys);
95 EXPECT_WRITE32(SYSRST_CTRL_COM_PRE_DET_CTL_1_REG_OFFSET,
96 config_.pre_condition_detection_time_threshold);
97 EXPECT_WRITE32(SYSRST_CTRL_COM_SEL_CTL_1_REG_OFFSET, config_.keys);
98 EXPECT_WRITE32(SYSRST_CTRL_COM_DET_CTL_1_REG_OFFSET,
99 config_.detection_time_threshold);
100 EXPECT_WRITE32(SYSRST_CTRL_COM_OUT_CTL_1_REG_OFFSET, config_.actions);
101 EXPECT_WRITE32(SYSRST_CTRL_EC_RST_CTL_REG_OFFSET,
102 config_.embedded_controller_reset_duration);
112 .debounce_time_threshold = 0x1000,
121 TEST_F(InputChangeDetectConfigTest, BadArgs) {
128 TEST_F(InputChangeDetectConfigTest, Locked) {
129 EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 0);
135 TEST_F(InputChangeDetectConfigTest, Success) {
136 EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 1);
137 EXPECT_WRITE32(SYSRST_CTRL_KEY_INTR_CTL_REG_OFFSET, config_.input_changes);
138 EXPECT_WRITE32(SYSRST_CTRL_KEY_INTR_DEBOUNCE_CTL_REG_OFFSET,
139 config_.debounce_time_threshold);
150 .override_value =
true,
159 TEST_F(OutputPinOverrideConfigTest, BadArgs) {
174 .override_value =
false,
182 .override_value =
true,
188 TEST_F(OutputPinOverrideConfigTest, Locked) {
189 EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 0);
195 TEST_F(OutputPinOverrideConfigTest, Success) {
196 EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 1);
197 EXPECT_READ32(SYSRST_CTRL_PIN_OUT_CTL_REG_OFFSET,
198 {{SYSRST_CTRL_PIN_OUT_CTL_Z3_WAKEUP_BIT, 1}});
199 EXPECT_WRITE32(SYSRST_CTRL_PIN_OUT_CTL_REG_OFFSET,
200 {{SYSRST_CTRL_PIN_OUT_CTL_BAT_DISABLE_BIT, 1},
201 {SYSRST_CTRL_PIN_OUT_CTL_Z3_WAKEUP_BIT, 1}});
202 EXPECT_READ32(SYSRST_CTRL_PIN_OUT_VALUE_REG_OFFSET,
203 {{SYSRST_CTRL_PIN_OUT_VALUE_Z3_WAKEUP_BIT, 1}});
204 EXPECT_WRITE32(SYSRST_CTRL_PIN_OUT_VALUE_REG_OFFSET,
205 {{SYSRST_CTRL_PIN_OUT_VALUE_BAT_DISABLE_BIT, 1},
206 {SYSRST_CTRL_PIN_OUT_VALUE_Z3_WAKEUP_BIT, 1}});
207 EXPECT_READ32(SYSRST_CTRL_PIN_ALLOWED_CTL_REG_OFFSET,
208 {{SYSRST_CTRL_PIN_ALLOWED_CTL_Z3_WAKEUP_0_BIT, 1}});
209 EXPECT_WRITE32(SYSRST_CTRL_PIN_ALLOWED_CTL_REG_OFFSET,
210 {{SYSRST_CTRL_PIN_ALLOWED_CTL_Z3_WAKEUP_0_BIT, 1},
211 {SYSRST_CTRL_PIN_ALLOWED_CTL_BAT_DISABLE_0_BIT, 1},
212 {SYSRST_CTRL_PIN_ALLOWED_CTL_BAT_DISABLE_1_BIT, 1}});
221 .ac_power_debounce_time_threshold = 0x100,
222 .lid_open_debounce_time_threshold = 0x200,
223 .power_button_debounce_time_threshold = 0x300,
231 TEST_F(UlpWakeupConfigTest, BadArgs) {
238 TEST_F(UlpWakeupConfigTest, Locked) {
239 EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 0);
244 TEST_F(UlpWakeupConfigTest, Success) {
245 EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 1);
246 EXPECT_WRITE32(SYSRST_CTRL_ULP_CTL_REG_OFFSET, 1);
247 EXPECT_WRITE32(SYSRST_CTRL_ULP_AC_DEBOUNCE_CTL_REG_OFFSET,
248 config_.ac_power_debounce_time_threshold);
249 EXPECT_WRITE32(SYSRST_CTRL_ULP_LID_DEBOUNCE_CTL_REG_OFFSET,
250 config_.lid_open_debounce_time_threshold);
251 EXPECT_WRITE32(SYSRST_CTRL_ULP_PWRB_DEBOUNCE_CTL_REG_OFFSET,
252 config_.power_button_debounce_time_threshold);
263 TEST_F(UlpWakeupSetEnabledTest, BadEnabled) {
268 TEST_F(UlpWakeupSetEnabledTest, Success) {
269 EXPECT_WRITE32(SYSRST_CTRL_ULP_CTL_REG_OFFSET, 0);
273 EXPECT_WRITE32(SYSRST_CTRL_ULP_CTL_REG_OFFSET, 1);
289 TEST_F(UlpWakeupGetEnabledTest, Success) {
292 EXPECT_READ32(SYSRST_CTRL_ULP_CTL_REG_OFFSET, 0);
297 EXPECT_READ32(SYSRST_CTRL_ULP_CTL_REG_OFFSET, 1);
312 TEST_F(PinsSetInvertedTest, BadPins) {
317 TEST_F(PinsSetInvertedTest, Locked) {
318 EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 0);
323 TEST_F(PinsSetInvertedTest, Success) {
324 EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 1);
325 EXPECT_READ32(SYSRST_CTRL_KEY_INVERT_CTL_REG_OFFSET, 0);
326 EXPECT_WRITE32(SYSRST_CTRL_KEY_INVERT_CTL_REG_OFFSET, pins_);
329 EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 1);
330 EXPECT_READ32(SYSRST_CTRL_KEY_INVERT_CTL_REG_OFFSET,
332 EXPECT_WRITE32(SYSRST_CTRL_KEY_INVERT_CTL_REG_OFFSET,
340 uint32_t inverted_pins;
346 TEST_F(PinsGetInvertedTest, Success) {
347 uint32_t inverted_pins;
348 EXPECT_READ32(SYSRST_CTRL_KEY_INVERT_CTL_REG_OFFSET,
362 TEST_F(PinOverrideSetAllowedTest, BadPin) {
367 TEST_F(PinOverrideSetAllowedTest, Locked) {
368 EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 0);
374 TEST_F(PinOverrideSetAllowedTest, Success) {
375 EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 1);
376 EXPECT_READ32(SYSRST_CTRL_PIN_ALLOWED_CTL_REG_OFFSET,
377 {{SYSRST_CTRL_PIN_ALLOWED_CTL_PWRB_OUT_0_BIT, 1}});
378 EXPECT_WRITE32(SYSRST_CTRL_PIN_ALLOWED_CTL_REG_OFFSET,
379 {{SYSRST_CTRL_PIN_ALLOWED_CTL_PWRB_OUT_0_BIT, 1},
380 {SYSRST_CTRL_PIN_ALLOWED_CTL_EC_RST_L_0_BIT, 1},
381 {SYSRST_CTRL_PIN_ALLOWED_CTL_EC_RST_L_1_BIT, 1}});
401 TEST_F(PinOverrideGetAllowedTest, BadPin) {
408 TEST_F(PinOverrideGetAllowedTest, Success) {
411 EXPECT_READ32(SYSRST_CTRL_PIN_ALLOWED_CTL_REG_OFFSET,
412 {{SYSRST_CTRL_PIN_ALLOWED_CTL_PWRB_OUT_0_BIT, 1},
413 {SYSRST_CTRL_PIN_ALLOWED_CTL_EC_RST_L_0_BIT, 1},
414 {SYSRST_CTRL_PIN_ALLOWED_CTL_EC_RST_L_1_BIT, 1}});
417 EXPECT_TRUE(allow_zero_);
418 EXPECT_TRUE(allow_one_);
428 TEST_F(PinOverrideSetEnabledTest, BadArgs) {
437 TEST_F(PinOverrideSetEnabledTest, Success) {
438 EXPECT_READ32(SYSRST_CTRL_PIN_OUT_CTL_REG_OFFSET,
439 {{SYSRST_CTRL_PIN_OUT_CTL_Z3_WAKEUP_BIT, 1},
440 {SYSRST_CTRL_PIN_OUT_CTL_KEY2_OUT_BIT, 1}});
441 EXPECT_WRITE32(SYSRST_CTRL_PIN_OUT_CTL_REG_OFFSET,
442 {{SYSRST_CTRL_PIN_OUT_CTL_Z3_WAKEUP_BIT, 1},
443 {SYSRST_CTRL_PIN_OUT_CTL_KEY2_OUT_BIT, 1},
444 {SYSRST_CTRL_PIN_OUT_CTL_KEY1_OUT_BIT, 1}});
448 EXPECT_READ32(SYSRST_CTRL_PIN_OUT_CTL_REG_OFFSET,
449 {{SYSRST_CTRL_PIN_OUT_CTL_Z3_WAKEUP_BIT, 1},
450 {SYSRST_CTRL_PIN_OUT_CTL_KEY2_OUT_BIT, 1},
451 {SYSRST_CTRL_PIN_OUT_CTL_KEY1_OUT_BIT, 1}});
452 EXPECT_WRITE32(SYSRST_CTRL_PIN_OUT_CTL_REG_OFFSET,
453 {{SYSRST_CTRL_PIN_OUT_CTL_Z3_WAKEUP_BIT, 1},
454 {SYSRST_CTRL_PIN_OUT_CTL_KEY1_OUT_BIT, 1}});
471 TEST_F(PinOverrideGetEnabledTest, BadPin) {
477 TEST_F(PinOverrideGetEnabledTest, Success) {
480 EXPECT_READ32(SYSRST_CTRL_PIN_OUT_CTL_REG_OFFSET,
481 {{SYSRST_CTRL_PIN_OUT_CTL_Z3_WAKEUP_BIT, 1}});
486 EXPECT_READ32(SYSRST_CTRL_PIN_OUT_CTL_REG_OFFSET, 0);
499 TEST_F(PinSetOverrideTest, BadPin) {
504 TEST_F(PinSetOverrideTest, Success) {
505 EXPECT_READ32(SYSRST_CTRL_PIN_OUT_VALUE_REG_OFFSET,
506 {{SYSRST_CTRL_PIN_OUT_VALUE_FLASH_WP_L_BIT, 1}});
507 EXPECT_WRITE32(SYSRST_CTRL_PIN_OUT_VALUE_REG_OFFSET,
508 {{SYSRST_CTRL_PIN_OUT_VALUE_KEY1_OUT_BIT, 1},
509 {SYSRST_CTRL_PIN_OUT_VALUE_FLASH_WP_L_BIT, 1}});
526 TEST_F(PinGetOverrideTest, BadPin) {
532 TEST_F(PinGetOverrideTest, Success) {
534 EXPECT_READ32(SYSRST_CTRL_PIN_OUT_VALUE_REG_OFFSET,
535 {{SYSRST_CTRL_PIN_OUT_VALUE_KEY1_OUT_BIT, 1}});
540 EXPECT_READ32(SYSRST_CTRL_PIN_OUT_VALUE_REG_OFFSET,
541 {{SYSRST_CTRL_PIN_OUT_VALUE_KEY1_OUT_BIT, 1}});
559 TEST_F(InputPinReadTest, BadPin) {
565 TEST_F(InputPinReadTest, Success) {
567 EXPECT_READ32(SYSRST_CTRL_PIN_IN_VALUE_REG_OFFSET,
568 {{SYSRST_CTRL_PIN_IN_VALUE_KEY1_IN_BIT, 1}});
573 EXPECT_READ32(SYSRST_CTRL_PIN_IN_VALUE_REG_OFFSET,
574 {{SYSRST_CTRL_PIN_IN_VALUE_KEY1_IN_BIT, 1}});
585 .key_0_override_value =
false,
587 .key_1_override_value =
true,
589 .key_2_override_value =
true,
598 TEST_F(AutoOverrideConfigTest, BadArgs) {
618 TEST_F(AutoOverrideConfigTest, Locked) {
619 EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 0);
625 TEST_F(AutoOverrideConfigTest, Success) {
626 EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 1);
628 SYSRST_CTRL_AUTO_BLOCK_DEBOUNCE_CTL_REG_OFFSET,
629 {{SYSRST_CTRL_AUTO_BLOCK_DEBOUNCE_CTL_AUTO_BLOCK_ENABLE_BIT,
true},
630 {SYSRST_CTRL_AUTO_BLOCK_DEBOUNCE_CTL_DEBOUNCE_TIMER_OFFSET,
631 config_.debounce_time_threshold}});
632 EXPECT_WRITE32(SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_REG_OFFSET,
633 {{SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY0_OUT_SEL_BIT,
true},
634 {SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY1_OUT_SEL_BIT,
false},
635 {SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY2_OUT_SEL_BIT,
true},
636 {SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY0_OUT_VALUE_BIT,
false},
637 {SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY1_OUT_VALUE_BIT,
true},
638 {SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY2_OUT_VALUE_BIT,
true}});
650 TEST_F(AutoOverrideSetEnabledTest, BadArgs) {
657 TEST_F(AutoOverrideSetEnabledTest, Locked) {
658 EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 0);
664 TEST_F(AutoOverrideSetEnabledTest, Success) {
665 EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 1);
666 EXPECT_READ32(SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_REG_OFFSET,
667 {{SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY0_OUT_SEL_BIT,
true},
668 {SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY1_OUT_SEL_BIT,
false},
669 {SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY2_OUT_SEL_BIT,
true}});
670 EXPECT_WRITE32(SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_REG_OFFSET,
671 {{SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY0_OUT_SEL_BIT,
true},
672 {SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY1_OUT_SEL_BIT,
false},
673 {SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY2_OUT_SEL_BIT,
false}});
690 TEST_F(AutoOverrideGetEnabledTest, BadKey) {
696 TEST_F(AutoOverrideGetEnabledTest, Success) {
698 EXPECT_READ32(SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_REG_OFFSET,
699 {{SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY0_OUT_SEL_BIT,
true},
700 {SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY1_OUT_SEL_BIT,
false},
701 {SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY2_OUT_SEL_BIT,
true}});
717 TEST_F(KeyComboIrqGetCausesTest, Success) {
719 EXPECT_READ32(SYSRST_CTRL_COMBO_INTR_STATUS_REG_OFFSET, 0xf);
722 EXPECT_EQ(causes, 0xf);
731 TEST_F(KeyComboIrqClearCausesTest, BadCauses) {
736 TEST_F(KeyComboIrqClearCausesTest, Success) {
737 EXPECT_WRITE32(SYSRST_CTRL_COMBO_INTR_STATUS_REG_OFFSET, 0xf);
753 TEST_F(InputChangeIrqGetCausesTest, Success) {
755 EXPECT_READ32(SYSRST_CTRL_KEY_INTR_STATUS_REG_OFFSET, 0x3f);
758 EXPECT_EQ(causes, 0x3f);
768 TEST_F(InputChangeIrqClearCausesTest, BadCauses) {
773 TEST_F(InputChangeIrqClearCausesTest, Success) {
774 EXPECT_WRITE32(SYSRST_CTRL_KEY_INTR_STATUS_REG_OFFSET, 0xff);
782 bool wakeup_detected;
790 TEST_F(UlpWakeupGetStatusTest, Success) {
791 bool wakeup_detected;
792 EXPECT_READ32(SYSRST_CTRL_WKUP_STATUS_REG_OFFSET, 1);
795 EXPECT_TRUE(wakeup_detected);
797 EXPECT_READ32(SYSRST_CTRL_WKUP_STATUS_REG_OFFSET, 0);
800 EXPECT_FALSE(wakeup_detected);
809 TEST_F(UlpWakeupClearStatusTest, Success) {
810 EXPECT_WRITE32(SYSRST_CTRL_WKUP_STATUS_REG_OFFSET, 1);
818 TEST_F(LockTest, Success) {
819 EXPECT_WRITE32(SYSRST_CTRL_REGWEN_REG_OFFSET, 0);
832 TEST_F(IsLockedTest, Success) {
834 EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 0);
836 EXPECT_TRUE(is_locked);
838 EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 1);
840 EXPECT_FALSE(is_locked);