Software APIs
dif_sysrst_ctrl_unittest.cc
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
6 
7 #include "gtest/gtest.h"
9 #include "sw/device/lib/base/mock_mmio.h"
12 
13 #include "sysrst_ctrl_regs.h" // Generated.
14 
15 namespace dif_sysrst_ctrl_unittest {
16 namespace {
17 using ::mock_mmio::LeInt;
18 using ::mock_mmio::MmioTest;
19 using ::mock_mmio::MockDevice;
20 
21 class SysrstCtrlTest : public testing::Test, public MmioTest {
22  protected:
23  dif_sysrst_ctrl_t sysrst_ctrl_ = {.base_addr = dev().region()};
24 };
25 
27  protected:
30  .pre_condition_detection_time_threshold = 0x1000,
32  .detection_time_threshold = 0x5000,
34  .embedded_controller_reset_duration = 0x100,
35  };
36 };
37 
38 TEST_F(KeyComboDetectConfigTest, NullArgs) {
40  nullptr, kDifSysrstCtrlKeyCombo1, config_));
41 }
42 
43 TEST_F(KeyComboDetectConfigTest, BadArgs) {
44  // Bad key combination.
46  &sysrst_ctrl_, kDifSysrstCtrlKeyComboAll, config_));
47 
48  // Bad pre-condition keys.
49  config_.pre_condition_keys = 1U << 5;
51  &sysrst_ctrl_, kDifSysrstCtrlKeyCombo1, config_));
52 
53  // Bad keys.
54  config_.pre_condition_keys = kDifSysrstCtrlKey2;
55  config_.keys = 1U << 5;
57  &sysrst_ctrl_, kDifSysrstCtrlKeyCombo1, config_));
58 
59  // Bad actions.
61  config_.actions = static_cast<dif_sysrst_ctrl_key_combo_action_t>(1U << 5);
63  &sysrst_ctrl_, kDifSysrstCtrlKeyCombo1, config_));
64 }
65 
66 TEST_F(KeyComboDetectConfigTest, Locked) {
67  EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 0);
69  &sysrst_ctrl_, kDifSysrstCtrlKeyCombo1, config_),
70  kDifLocked);
71 }
72 
73 TEST_F(KeyComboDetectConfigTest, SuccessWithoutEcReset) {
74  config_.actions = kDifSysrstCtrlKeyComboActionInterrupt |
76 
77  EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 1);
78  EXPECT_WRITE32(SYSRST_CTRL_COM_PRE_SEL_CTL_1_REG_OFFSET,
79  config_.pre_condition_keys);
80  EXPECT_WRITE32(SYSRST_CTRL_COM_PRE_DET_CTL_1_REG_OFFSET,
81  config_.pre_condition_detection_time_threshold);
82  EXPECT_WRITE32(SYSRST_CTRL_COM_SEL_CTL_1_REG_OFFSET, config_.keys);
83  EXPECT_WRITE32(SYSRST_CTRL_COM_DET_CTL_1_REG_OFFSET,
84  config_.detection_time_threshold);
85  EXPECT_WRITE32(SYSRST_CTRL_COM_OUT_CTL_1_REG_OFFSET, config_.actions);
86 
88  &sysrst_ctrl_, kDifSysrstCtrlKeyCombo1, config_));
89 }
90 
91 TEST_F(KeyComboDetectConfigTest, SuccessWithEcReset) {
92  EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 1);
93  EXPECT_WRITE32(SYSRST_CTRL_COM_PRE_SEL_CTL_1_REG_OFFSET,
94  config_.pre_condition_keys);
95  EXPECT_WRITE32(SYSRST_CTRL_COM_PRE_DET_CTL_1_REG_OFFSET,
96  config_.pre_condition_detection_time_threshold);
97  EXPECT_WRITE32(SYSRST_CTRL_COM_SEL_CTL_1_REG_OFFSET, config_.keys);
98  EXPECT_WRITE32(SYSRST_CTRL_COM_DET_CTL_1_REG_OFFSET,
99  config_.detection_time_threshold);
100  EXPECT_WRITE32(SYSRST_CTRL_COM_OUT_CTL_1_REG_OFFSET, config_.actions);
101  EXPECT_WRITE32(SYSRST_CTRL_EC_RST_CTL_REG_OFFSET,
102  config_.embedded_controller_reset_duration);
103 
105  &sysrst_ctrl_, kDifSysrstCtrlKeyCombo1, config_));
106 }
107 
109  protected:
112  .debounce_time_threshold = 0x1000,
113  };
114 };
115 
116 TEST_F(InputChangeDetectConfigTest, NullArgs) {
119 }
120 
121 TEST_F(InputChangeDetectConfigTest, BadArgs) {
122  // Bad input signal changes.
123  config_.input_changes = static_cast<dif_sysrst_ctrl_input_change_t>(1U << 14);
125  dif_sysrst_ctrl_input_change_detect_configure(&sysrst_ctrl_, config_));
126 }
127 
128 TEST_F(InputChangeDetectConfigTest, Locked) {
129  EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 0);
130  EXPECT_EQ(
131  dif_sysrst_ctrl_input_change_detect_configure(&sysrst_ctrl_, config_),
132  kDifLocked);
133 }
134 
135 TEST_F(InputChangeDetectConfigTest, Success) {
136  EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 1);
137  EXPECT_WRITE32(SYSRST_CTRL_KEY_INTR_CTL_REG_OFFSET, config_.input_changes);
138  EXPECT_WRITE32(SYSRST_CTRL_KEY_INTR_DEBOUNCE_CTL_REG_OFFSET,
139  config_.debounce_time_threshold);
141  dif_sysrst_ctrl_input_change_detect_configure(&sysrst_ctrl_, config_));
142 }
143 
145  protected:
146  dif_sysrst_ctrl_pin_config_t config_ = {
148  .allow_zero = true,
149  .allow_one = true,
150  .override_value = true,
151  };
152 };
153 
154 TEST_F(OutputPinOverrideConfigTest, NullArgs) {
156  nullptr, kDifSysrstCtrlPinBatteryDisableOut, config_));
157 }
158 
159 TEST_F(OutputPinOverrideConfigTest, BadArgs) {
160  // Bad pin.
162  &sysrst_ctrl_, kDifSysrstCtrlPinKey0In, config_));
163 
164  // Bad enabled.
165  config_.enabled = static_cast<dif_toggle_t>(2);
167  &sysrst_ctrl_, kDifSysrstCtrlPinKey0Out, config_));
168 
169  // Bad allow values.
170  config_ = {
171  .enabled = kDifToggleEnabled,
172  .allow_zero = false,
173  .allow_one = true,
174  .override_value = false,
175  };
177  &sysrst_ctrl_, kDifSysrstCtrlPinBatteryDisableOut, config_));
178  config_ = {
179  .enabled = kDifToggleEnabled,
180  .allow_zero = true,
181  .allow_one = false,
182  .override_value = true,
183  };
185  &sysrst_ctrl_, kDifSysrstCtrlPinBatteryDisableOut, config_));
186 }
187 
188 TEST_F(OutputPinOverrideConfigTest, Locked) {
189  EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 0);
191  &sysrst_ctrl_, kDifSysrstCtrlPinBatteryDisableOut, config_),
192  kDifLocked);
193 }
194 
195 TEST_F(OutputPinOverrideConfigTest, Success) {
196  EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 1);
197  EXPECT_READ32(SYSRST_CTRL_PIN_OUT_CTL_REG_OFFSET,
198  {{SYSRST_CTRL_PIN_OUT_CTL_Z3_WAKEUP_BIT, 1}});
199  EXPECT_WRITE32(SYSRST_CTRL_PIN_OUT_CTL_REG_OFFSET,
200  {{SYSRST_CTRL_PIN_OUT_CTL_BAT_DISABLE_BIT, 1},
201  {SYSRST_CTRL_PIN_OUT_CTL_Z3_WAKEUP_BIT, 1}});
202  EXPECT_READ32(SYSRST_CTRL_PIN_OUT_VALUE_REG_OFFSET,
203  {{SYSRST_CTRL_PIN_OUT_VALUE_Z3_WAKEUP_BIT, 1}});
204  EXPECT_WRITE32(SYSRST_CTRL_PIN_OUT_VALUE_REG_OFFSET,
205  {{SYSRST_CTRL_PIN_OUT_VALUE_BAT_DISABLE_BIT, 1},
206  {SYSRST_CTRL_PIN_OUT_VALUE_Z3_WAKEUP_BIT, 1}});
207  EXPECT_READ32(SYSRST_CTRL_PIN_ALLOWED_CTL_REG_OFFSET,
208  {{SYSRST_CTRL_PIN_ALLOWED_CTL_Z3_WAKEUP_0_BIT, 1}});
209  EXPECT_WRITE32(SYSRST_CTRL_PIN_ALLOWED_CTL_REG_OFFSET,
210  {{SYSRST_CTRL_PIN_ALLOWED_CTL_Z3_WAKEUP_0_BIT, 1},
211  {SYSRST_CTRL_PIN_ALLOWED_CTL_BAT_DISABLE_0_BIT, 1},
212  {SYSRST_CTRL_PIN_ALLOWED_CTL_BAT_DISABLE_1_BIT, 1}});
214  &sysrst_ctrl_, kDifSysrstCtrlPinBatteryDisableOut, config_));
215 }
216 
218  protected:
221  .ac_power_debounce_time_threshold = 0x100,
222  .lid_open_debounce_time_threshold = 0x200,
223  .power_button_debounce_time_threshold = 0x300,
224  };
225 };
226 
227 TEST_F(UlpWakeupConfigTest, NullArgs) {
229 }
230 
231 TEST_F(UlpWakeupConfigTest, BadArgs) {
232  // Bad enabled.
233  config_.enabled = static_cast<dif_toggle_t>(2);
235  dif_sysrst_ctrl_ulp_wakeup_configure(&sysrst_ctrl_, config_));
236 }
237 
238 TEST_F(UlpWakeupConfigTest, Locked) {
239  EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 0);
240  EXPECT_EQ(dif_sysrst_ctrl_ulp_wakeup_configure(&sysrst_ctrl_, config_),
241  kDifLocked);
242 }
243 
244 TEST_F(UlpWakeupConfigTest, Success) {
245  EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 1);
246  EXPECT_WRITE32(SYSRST_CTRL_ULP_CTL_REG_OFFSET, 1);
247  EXPECT_WRITE32(SYSRST_CTRL_ULP_AC_DEBOUNCE_CTL_REG_OFFSET,
248  config_.ac_power_debounce_time_threshold);
249  EXPECT_WRITE32(SYSRST_CTRL_ULP_LID_DEBOUNCE_CTL_REG_OFFSET,
250  config_.lid_open_debounce_time_threshold);
251  EXPECT_WRITE32(SYSRST_CTRL_ULP_PWRB_DEBOUNCE_CTL_REG_OFFSET,
252  config_.power_button_debounce_time_threshold);
253  EXPECT_DIF_OK(dif_sysrst_ctrl_ulp_wakeup_configure(&sysrst_ctrl_, config_));
254 }
255 
257 
258 TEST_F(UlpWakeupSetEnabledTest, NullArgs) {
261 }
262 
263 TEST_F(UlpWakeupSetEnabledTest, BadEnabled) {
265  &sysrst_ctrl_, static_cast<dif_toggle_t>(2)));
266 }
267 
268 TEST_F(UlpWakeupSetEnabledTest, Success) {
269  EXPECT_WRITE32(SYSRST_CTRL_ULP_CTL_REG_OFFSET, 0);
272 
273  EXPECT_WRITE32(SYSRST_CTRL_ULP_CTL_REG_OFFSET, 1);
276 }
277 
279 
280 TEST_F(UlpWakeupGetEnabledTest, NullArgs) {
281  dif_toggle_t is_enabled;
283  dif_sysrst_ctrl_ulp_wakeup_get_enabled(nullptr, &is_enabled));
285  dif_sysrst_ctrl_ulp_wakeup_get_enabled(&sysrst_ctrl_, nullptr));
287 }
288 
289 TEST_F(UlpWakeupGetEnabledTest, Success) {
290  dif_toggle_t is_enabled;
291 
292  EXPECT_READ32(SYSRST_CTRL_ULP_CTL_REG_OFFSET, 0);
294  dif_sysrst_ctrl_ulp_wakeup_get_enabled(&sysrst_ctrl_, &is_enabled));
295  EXPECT_EQ(is_enabled, kDifToggleDisabled);
296 
297  EXPECT_READ32(SYSRST_CTRL_ULP_CTL_REG_OFFSET, 1);
299  dif_sysrst_ctrl_ulp_wakeup_get_enabled(&sysrst_ctrl_, &is_enabled));
300  EXPECT_EQ(is_enabled, kDifToggleEnabled);
301 }
302 
304  protected:
306 };
307 
308 TEST_F(PinsSetInvertedTest, NullArgs) {
310 }
311 
312 TEST_F(PinsSetInvertedTest, BadPins) {
314  &sysrst_ctrl_, pins_ | kDifSysrstCtrlPinEcResetInOut, true));
315 }
316 
317 TEST_F(PinsSetInvertedTest, Locked) {
318  EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 0);
319  EXPECT_EQ(dif_sysrst_ctrl_pins_set_inverted(&sysrst_ctrl_, pins_, true),
320  kDifLocked);
321 }
322 
323 TEST_F(PinsSetInvertedTest, Success) {
324  EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 1);
325  EXPECT_READ32(SYSRST_CTRL_KEY_INVERT_CTL_REG_OFFSET, 0);
326  EXPECT_WRITE32(SYSRST_CTRL_KEY_INVERT_CTL_REG_OFFSET, pins_);
327  EXPECT_DIF_OK(dif_sysrst_ctrl_pins_set_inverted(&sysrst_ctrl_, pins_, true));
328 
329  EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 1);
330  EXPECT_READ32(SYSRST_CTRL_KEY_INVERT_CTL_REG_OFFSET,
332  EXPECT_WRITE32(SYSRST_CTRL_KEY_INVERT_CTL_REG_OFFSET,
334  EXPECT_DIF_OK(dif_sysrst_ctrl_pins_set_inverted(&sysrst_ctrl_, pins_, false));
335 }
336 
338 
339 TEST_F(PinsGetInvertedTest, NullArgs) {
340  uint32_t inverted_pins;
341  EXPECT_DIF_BADARG(dif_sysrst_ctrl_pins_get_inverted(nullptr, &inverted_pins));
342  EXPECT_DIF_BADARG(dif_sysrst_ctrl_pins_get_inverted(&sysrst_ctrl_, nullptr));
344 }
345 
346 TEST_F(PinsGetInvertedTest, Success) {
347  uint32_t inverted_pins;
348  EXPECT_READ32(SYSRST_CTRL_KEY_INVERT_CTL_REG_OFFSET,
351  dif_sysrst_ctrl_pins_get_inverted(&sysrst_ctrl_, &inverted_pins));
352  EXPECT_EQ(inverted_pins, kDifSysrstCtrlPinKey0In | kDifSysrstCtrlPinKey2Out);
353 }
354 
356 
357 TEST_F(PinOverrideSetAllowedTest, NullArgs) {
359  nullptr, kDifSysrstCtrlPinKey1Out, true, true));
360 }
361 
362 TEST_F(PinOverrideSetAllowedTest, BadPin) {
364  &sysrst_ctrl_, kDifSysrstCtrlPinKey1In, true, true));
365 }
366 
367 TEST_F(PinOverrideSetAllowedTest, Locked) {
368  EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 0);
370  &sysrst_ctrl_, kDifSysrstCtrlPinKey1Out, true, true),
371  kDifLocked);
372 }
373 
374 TEST_F(PinOverrideSetAllowedTest, Success) {
375  EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 1);
376  EXPECT_READ32(SYSRST_CTRL_PIN_ALLOWED_CTL_REG_OFFSET,
377  {{SYSRST_CTRL_PIN_ALLOWED_CTL_PWRB_OUT_0_BIT, 1}});
378  EXPECT_WRITE32(SYSRST_CTRL_PIN_ALLOWED_CTL_REG_OFFSET,
379  {{SYSRST_CTRL_PIN_ALLOWED_CTL_PWRB_OUT_0_BIT, 1},
380  {SYSRST_CTRL_PIN_ALLOWED_CTL_EC_RST_L_0_BIT, 1},
381  {SYSRST_CTRL_PIN_ALLOWED_CTL_EC_RST_L_1_BIT, 1}});
383  &sysrst_ctrl_, kDifSysrstCtrlPinEcResetInOut, true, true));
384 }
385 
387 
388 TEST_F(PinOverrideGetAllowedTest, NullArgs) {
389  bool allow_zero_;
390  bool allow_one_;
392  nullptr, kDifSysrstCtrlPinKey1Out, &allow_zero_, &allow_one_));
394  &sysrst_ctrl_, kDifSysrstCtrlPinKey1Out, nullptr, &allow_one_));
396  &sysrst_ctrl_, kDifSysrstCtrlPinKey1Out, &allow_zero_, nullptr));
398  nullptr, kDifSysrstCtrlPinKey1Out, nullptr, nullptr));
399 }
400 
401 TEST_F(PinOverrideGetAllowedTest, BadPin) {
402  bool allow_zero_;
403  bool allow_one_;
405  &sysrst_ctrl_, kDifSysrstCtrlPinKey1In, &allow_zero_, &allow_one_));
406 }
407 
408 TEST_F(PinOverrideGetAllowedTest, Success) {
409  bool allow_zero_;
410  bool allow_one_;
411  EXPECT_READ32(SYSRST_CTRL_PIN_ALLOWED_CTL_REG_OFFSET,
412  {{SYSRST_CTRL_PIN_ALLOWED_CTL_PWRB_OUT_0_BIT, 1},
413  {SYSRST_CTRL_PIN_ALLOWED_CTL_EC_RST_L_0_BIT, 1},
414  {SYSRST_CTRL_PIN_ALLOWED_CTL_EC_RST_L_1_BIT, 1}});
416  &sysrst_ctrl_, kDifSysrstCtrlPinEcResetInOut, &allow_zero_, &allow_one_));
417  EXPECT_TRUE(allow_zero_);
418  EXPECT_TRUE(allow_one_);
419 }
420 
422 
423 TEST_F(PinOverrideSetEnabledTest, NullArgs) {
426 }
427 
428 TEST_F(PinOverrideSetEnabledTest, BadArgs) {
429  // Bad enabled.
431  &sysrst_ctrl_, kDifSysrstCtrlPinKey1Out, static_cast<dif_toggle_t>(2)));
432  // Bad pin.
434  &sysrst_ctrl_, kDifSysrstCtrlPinKey1In, kDifToggleEnabled));
435 }
436 
437 TEST_F(PinOverrideSetEnabledTest, Success) {
438  EXPECT_READ32(SYSRST_CTRL_PIN_OUT_CTL_REG_OFFSET,
439  {{SYSRST_CTRL_PIN_OUT_CTL_Z3_WAKEUP_BIT, 1},
440  {SYSRST_CTRL_PIN_OUT_CTL_KEY2_OUT_BIT, 1}});
441  EXPECT_WRITE32(SYSRST_CTRL_PIN_OUT_CTL_REG_OFFSET,
442  {{SYSRST_CTRL_PIN_OUT_CTL_Z3_WAKEUP_BIT, 1},
443  {SYSRST_CTRL_PIN_OUT_CTL_KEY2_OUT_BIT, 1},
444  {SYSRST_CTRL_PIN_OUT_CTL_KEY1_OUT_BIT, 1}});
447 
448  EXPECT_READ32(SYSRST_CTRL_PIN_OUT_CTL_REG_OFFSET,
449  {{SYSRST_CTRL_PIN_OUT_CTL_Z3_WAKEUP_BIT, 1},
450  {SYSRST_CTRL_PIN_OUT_CTL_KEY2_OUT_BIT, 1},
451  {SYSRST_CTRL_PIN_OUT_CTL_KEY1_OUT_BIT, 1}});
452  EXPECT_WRITE32(SYSRST_CTRL_PIN_OUT_CTL_REG_OFFSET,
453  {{SYSRST_CTRL_PIN_OUT_CTL_Z3_WAKEUP_BIT, 1},
454  {SYSRST_CTRL_PIN_OUT_CTL_KEY1_OUT_BIT, 1}});
457 }
458 
460 
461 TEST_F(PinOverrideGetEnabledTest, NullArgs) {
462  dif_toggle_t is_enabled;
464  nullptr, kDifSysrstCtrlPinKey1Out, &is_enabled));
466  &sysrst_ctrl_, kDifSysrstCtrlPinKey1Out, nullptr));
468  nullptr, kDifSysrstCtrlPinKey1Out, nullptr));
469 }
470 
471 TEST_F(PinOverrideGetEnabledTest, BadPin) {
472  dif_toggle_t is_enabled;
474  &sysrst_ctrl_, kDifSysrstCtrlPinKey1In, &is_enabled));
475 }
476 
477 TEST_F(PinOverrideGetEnabledTest, Success) {
478  dif_toggle_t is_enabled;
479 
480  EXPECT_READ32(SYSRST_CTRL_PIN_OUT_CTL_REG_OFFSET,
481  {{SYSRST_CTRL_PIN_OUT_CTL_Z3_WAKEUP_BIT, 1}});
483  &sysrst_ctrl_, kDifSysrstCtrlPinZ3WakeupOut, &is_enabled));
484  EXPECT_EQ(is_enabled, kDifToggleEnabled);
485 
486  EXPECT_READ32(SYSRST_CTRL_PIN_OUT_CTL_REG_OFFSET, 0);
488  &sysrst_ctrl_, kDifSysrstCtrlPinZ3WakeupOut, &is_enabled));
489  EXPECT_EQ(is_enabled, kDifToggleDisabled);
490 }
491 
493 
494 TEST_F(PinSetOverrideTest, NullArgs) {
496  nullptr, kDifSysrstCtrlPinKey1Out, true));
497 }
498 
499 TEST_F(PinSetOverrideTest, BadPin) {
501  &sysrst_ctrl_, kDifSysrstCtrlPinKey1In, true));
502 }
503 
504 TEST_F(PinSetOverrideTest, Success) {
505  EXPECT_READ32(SYSRST_CTRL_PIN_OUT_VALUE_REG_OFFSET,
506  {{SYSRST_CTRL_PIN_OUT_VALUE_FLASH_WP_L_BIT, 1}});
507  EXPECT_WRITE32(SYSRST_CTRL_PIN_OUT_VALUE_REG_OFFSET,
508  {{SYSRST_CTRL_PIN_OUT_VALUE_KEY1_OUT_BIT, 1},
509  {SYSRST_CTRL_PIN_OUT_VALUE_FLASH_WP_L_BIT, 1}});
511  &sysrst_ctrl_, kDifSysrstCtrlPinKey1Out, true));
512 }
513 
515 
516 TEST_F(PinGetOverrideTest, NullArgs) {
517  bool value;
519  nullptr, kDifSysrstCtrlPinKey1Out, &value));
521  &sysrst_ctrl_, kDifSysrstCtrlPinKey1Out, nullptr));
523  nullptr, kDifSysrstCtrlPinKey1Out, nullptr));
524 }
525 
526 TEST_F(PinGetOverrideTest, BadPin) {
527  bool value;
529  &sysrst_ctrl_, kDifSysrstCtrlPinKey1In, &value));
530 }
531 
532 TEST_F(PinGetOverrideTest, Success) {
533  bool value;
534  EXPECT_READ32(SYSRST_CTRL_PIN_OUT_VALUE_REG_OFFSET,
535  {{SYSRST_CTRL_PIN_OUT_VALUE_KEY1_OUT_BIT, 1}});
537  &sysrst_ctrl_, kDifSysrstCtrlPinKey1Out, &value));
538  EXPECT_TRUE(value);
539 
540  EXPECT_READ32(SYSRST_CTRL_PIN_OUT_VALUE_REG_OFFSET,
541  {{SYSRST_CTRL_PIN_OUT_VALUE_KEY1_OUT_BIT, 1}});
543  &sysrst_ctrl_, kDifSysrstCtrlPinKey2Out, &value));
544  EXPECT_FALSE(value);
545 }
546 
548 
549 TEST_F(InputPinReadTest, NullArgs) {
550  bool value;
554  &sysrst_ctrl_, kDifSysrstCtrlPinKey2In, nullptr));
556  nullptr, kDifSysrstCtrlPinKey2In, nullptr));
557 }
558 
559 TEST_F(InputPinReadTest, BadPin) {
560  bool value;
562  &sysrst_ctrl_, kDifSysrstCtrlPinKey2Out, &value));
563 }
564 
565 TEST_F(InputPinReadTest, Success) {
566  bool value;
567  EXPECT_READ32(SYSRST_CTRL_PIN_IN_VALUE_REG_OFFSET,
568  {{SYSRST_CTRL_PIN_IN_VALUE_KEY1_IN_BIT, 1}});
570  &sysrst_ctrl_, kDifSysrstCtrlPinKey1In, &value));
571  EXPECT_TRUE(value);
572 
573  EXPECT_READ32(SYSRST_CTRL_PIN_IN_VALUE_REG_OFFSET,
574  {{SYSRST_CTRL_PIN_IN_VALUE_KEY1_IN_BIT, 1}});
576  &sysrst_ctrl_, kDifSysrstCtrlPinKey2In, &value));
577  EXPECT_FALSE(value);
578 }
579 
581  protected:
583  .debounce_time_threshold = 0x150,
584  .override_key_0 = kDifToggleEnabled,
585  .key_0_override_value = false,
586  .override_key_1 = kDifToggleDisabled,
587  .key_1_override_value = true,
588  .override_key_2 = kDifToggleEnabled,
589  .key_2_override_value = true,
590  };
591 };
592 
593 TEST_F(AutoOverrideConfigTest, NullArgs) {
596 }
597 
598 TEST_F(AutoOverrideConfigTest, BadArgs) {
600  &sysrst_ctrl_, config_, static_cast<dif_toggle_t>(2)));
601 
602  config_.override_key_0 = static_cast<dif_toggle_t>(2);
604  &sysrst_ctrl_, config_, kDifToggleEnabled));
605  config_.override_key_0 = kDifToggleEnabled;
606 
607  config_.override_key_1 = static_cast<dif_toggle_t>(2);
609  &sysrst_ctrl_, config_, kDifToggleEnabled));
610  config_.override_key_1 = kDifToggleDisabled;
611 
612  config_.override_key_2 = static_cast<dif_toggle_t>(2);
614  &sysrst_ctrl_, config_, kDifToggleEnabled));
615  config_.override_key_2 = kDifToggleEnabled;
616 }
617 
618 TEST_F(AutoOverrideConfigTest, Locked) {
619  EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 0);
620  EXPECT_EQ(dif_sysrst_ctrl_auto_override_configure(&sysrst_ctrl_, config_,
622  kDifLocked);
623 }
624 
625 TEST_F(AutoOverrideConfigTest, Success) {
626  EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 1);
627  EXPECT_WRITE32(
628  SYSRST_CTRL_AUTO_BLOCK_DEBOUNCE_CTL_REG_OFFSET,
629  {{SYSRST_CTRL_AUTO_BLOCK_DEBOUNCE_CTL_AUTO_BLOCK_ENABLE_BIT, true},
630  {SYSRST_CTRL_AUTO_BLOCK_DEBOUNCE_CTL_DEBOUNCE_TIMER_OFFSET,
631  config_.debounce_time_threshold}});
632  EXPECT_WRITE32(SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_REG_OFFSET,
633  {{SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY0_OUT_SEL_BIT, true},
634  {SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY1_OUT_SEL_BIT, false},
635  {SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY2_OUT_SEL_BIT, true},
636  {SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY0_OUT_VALUE_BIT, false},
637  {SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY1_OUT_VALUE_BIT, true},
638  {SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY2_OUT_VALUE_BIT, true}});
641 }
642 
644 
645 TEST_F(AutoOverrideSetEnabledTest, NullArgs) {
648 }
649 
650 TEST_F(AutoOverrideSetEnabledTest, BadArgs) {
654  &sysrst_ctrl_, kDifSysrstCtrlKey2, static_cast<dif_toggle_t>(2)));
655 }
656 
657 TEST_F(AutoOverrideSetEnabledTest, Locked) {
658  EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 0);
660  &sysrst_ctrl_, kDifSysrstCtrlKey2, kDifToggleEnabled),
661  kDifLocked);
662 }
663 
664 TEST_F(AutoOverrideSetEnabledTest, Success) {
665  EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 1);
666  EXPECT_READ32(SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_REG_OFFSET,
667  {{SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY0_OUT_SEL_BIT, true},
668  {SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY1_OUT_SEL_BIT, false},
669  {SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY2_OUT_SEL_BIT, true}});
670  EXPECT_WRITE32(SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_REG_OFFSET,
671  {{SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY0_OUT_SEL_BIT, true},
672  {SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY1_OUT_SEL_BIT, false},
673  {SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY2_OUT_SEL_BIT, false}});
675  &sysrst_ctrl_, kDifSysrstCtrlKey2, kDifToggleDisabled));
676 }
677 
679 
680 TEST_F(AutoOverrideGetEnabledTest, NullArgs) {
681  dif_toggle_t is_enabled;
683  nullptr, kDifSysrstCtrlKey1, &is_enabled));
685  &sysrst_ctrl_, kDifSysrstCtrlKey1, nullptr));
687  nullptr, kDifSysrstCtrlKey1, nullptr));
688 }
689 
690 TEST_F(AutoOverrideGetEnabledTest, BadKey) {
691  dif_toggle_t is_enabled;
693  &sysrst_ctrl_, kDifSysrstCtrlKeyPowerButton, &is_enabled));
694 }
695 
696 TEST_F(AutoOverrideGetEnabledTest, Success) {
697  dif_toggle_t is_enabled;
698  EXPECT_READ32(SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_REG_OFFSET,
699  {{SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY0_OUT_SEL_BIT, true},
700  {SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY1_OUT_SEL_BIT, false},
701  {SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_KEY2_OUT_SEL_BIT, true}});
703  &sysrst_ctrl_, kDifSysrstCtrlKey2, &is_enabled));
704  EXPECT_EQ(is_enabled, kDifToggleEnabled);
705 }
706 
708 
709 TEST_F(KeyComboIrqGetCausesTest, NullArgs) {
710  uint32_t causes;
713  dif_sysrst_ctrl_key_combo_irq_get_causes(&sysrst_ctrl_, nullptr));
715 }
716 
717 TEST_F(KeyComboIrqGetCausesTest, Success) {
718  uint32_t causes;
719  EXPECT_READ32(SYSRST_CTRL_COMBO_INTR_STATUS_REG_OFFSET, 0xf);
721  dif_sysrst_ctrl_key_combo_irq_get_causes(&sysrst_ctrl_, &causes));
722  EXPECT_EQ(causes, 0xf);
723 }
724 
726 
727 TEST_F(KeyComboIrqClearCausesTest, NullArgs) {
729 }
730 
731 TEST_F(KeyComboIrqClearCausesTest, BadCauses) {
733  dif_sysrst_ctrl_key_combo_irq_clear_causes(&sysrst_ctrl_, 0x1f));
734 }
735 
736 TEST_F(KeyComboIrqClearCausesTest, Success) {
737  EXPECT_WRITE32(SYSRST_CTRL_COMBO_INTR_STATUS_REG_OFFSET, 0xf);
739 }
740 
742 
743 TEST_F(InputChangeIrqGetCausesTest, NullArgs) {
744  uint32_t causes;
748  dif_sysrst_ctrl_input_change_irq_get_causes(&sysrst_ctrl_, nullptr));
751 }
752 
753 TEST_F(InputChangeIrqGetCausesTest, Success) {
754  uint32_t causes;
755  EXPECT_READ32(SYSRST_CTRL_KEY_INTR_STATUS_REG_OFFSET, 0x3f);
757  dif_sysrst_ctrl_input_change_irq_get_causes(&sysrst_ctrl_, &causes));
758  EXPECT_EQ(causes, 0x3f);
759 }
760 
762 
763 TEST_F(InputChangeIrqClearCausesTest, NullArgs) {
766 }
767 
768 TEST_F(InputChangeIrqClearCausesTest, BadCauses) {
770  dif_sysrst_ctrl_input_change_irq_clear_causes(&sysrst_ctrl_, 0x4000));
771 }
772 
773 TEST_F(InputChangeIrqClearCausesTest, Success) {
774  EXPECT_WRITE32(SYSRST_CTRL_KEY_INTR_STATUS_REG_OFFSET, 0xff);
776  dif_sysrst_ctrl_input_change_irq_clear_causes(&sysrst_ctrl_, 0xff));
777 }
778 
780 
781 TEST_F(UlpWakeupGetStatusTest, NullArgs) {
782  bool wakeup_detected;
784  dif_sysrst_ctrl_ulp_wakeup_get_status(nullptr, &wakeup_detected));
786  dif_sysrst_ctrl_ulp_wakeup_get_status(&sysrst_ctrl_, nullptr));
788 }
789 
790 TEST_F(UlpWakeupGetStatusTest, Success) {
791  bool wakeup_detected;
792  EXPECT_READ32(SYSRST_CTRL_WKUP_STATUS_REG_OFFSET, 1);
794  dif_sysrst_ctrl_ulp_wakeup_get_status(&sysrst_ctrl_, &wakeup_detected));
795  EXPECT_TRUE(wakeup_detected);
796 
797  EXPECT_READ32(SYSRST_CTRL_WKUP_STATUS_REG_OFFSET, 0);
799  dif_sysrst_ctrl_ulp_wakeup_get_status(&sysrst_ctrl_, &wakeup_detected));
800  EXPECT_FALSE(wakeup_detected);
801 }
802 
804 
805 TEST_F(UlpWakeupClearStatusTest, NullArgs) {
807 }
808 
809 TEST_F(UlpWakeupClearStatusTest, Success) {
810  EXPECT_WRITE32(SYSRST_CTRL_WKUP_STATUS_REG_OFFSET, 1);
812 }
813 
814 class LockTest : public SysrstCtrlTest {};
815 
816 TEST_F(LockTest, NullArgs) { EXPECT_DIF_BADARG(dif_sysrst_ctrl_lock(nullptr)); }
817 
818 TEST_F(LockTest, Success) {
819  EXPECT_WRITE32(SYSRST_CTRL_REGWEN_REG_OFFSET, 0);
820  EXPECT_DIF_OK(dif_sysrst_ctrl_lock(&sysrst_ctrl_));
821 }
822 
823 class IsLockedTest : public SysrstCtrlTest {};
824 
825 TEST_F(IsLockedTest, NullArgs) {
826  bool is_locked;
827  EXPECT_DIF_BADARG(dif_sysrst_ctrl_is_locked(nullptr, &is_locked));
828  EXPECT_DIF_BADARG(dif_sysrst_ctrl_is_locked(&sysrst_ctrl_, nullptr));
829  EXPECT_DIF_BADARG(dif_sysrst_ctrl_is_locked(nullptr, nullptr));
830 }
831 
832 TEST_F(IsLockedTest, Success) {
833  bool is_locked;
834  EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 0);
835  EXPECT_DIF_OK(dif_sysrst_ctrl_is_locked(&sysrst_ctrl_, &is_locked));
836  EXPECT_TRUE(is_locked);
837 
838  EXPECT_READ32(SYSRST_CTRL_REGWEN_REG_OFFSET, 1);
839  EXPECT_DIF_OK(dif_sysrst_ctrl_is_locked(&sysrst_ctrl_, &is_locked));
840  EXPECT_FALSE(is_locked);
841 }
842 
843 } // namespace
844 } // namespace dif_sysrst_ctrl_unittest