Software APIs
dif_sysrst_ctrl_autogen.c
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 // THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
6 // util/make_new_dif.py --mode=regen --only=autogen
7 
8 #include "sw/device/lib/dif/autogen/dif_sysrst_ctrl_autogen.h"
9 
10 #include <stdint.h>
11 
12 #include "sw/device/lib/dif/dif_base.h"
13 
14 #include "sysrst_ctrl_regs.h" // Generated.
15 
16 OT_WARN_UNUSED_RESULT
17 dif_result_t dif_sysrst_ctrl_init(mmio_region_t base_addr,
18  dif_sysrst_ctrl_t *sysrst_ctrl) {
19  if (sysrst_ctrl == NULL) {
20  return kDifBadArg;
21  }
22 
23  sysrst_ctrl->base_addr = base_addr;
24 
25  return kDifOk;
26 }
27 
28 dif_result_t dif_sysrst_ctrl_alert_force(const dif_sysrst_ctrl_t *sysrst_ctrl,
29  dif_sysrst_ctrl_alert_t alert) {
30  if (sysrst_ctrl == NULL) {
31  return kDifBadArg;
32  }
33 
34  bitfield_bit32_index_t alert_idx;
35  switch (alert) {
36  case kDifSysrstCtrlAlertFatalFault:
37  alert_idx = SYSRST_CTRL_ALERT_TEST_FATAL_FAULT_BIT;
38  break;
39  default:
40  return kDifBadArg;
41  }
42 
43  uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx, true);
44  mmio_region_write32(sysrst_ctrl->base_addr,
45  (ptrdiff_t)SYSRST_CTRL_ALERT_TEST_REG_OFFSET,
46  alert_test_reg);
47 
48  return kDifOk;
49 }
50 
51 /**
52  * Get the corresponding interrupt register bit offset of the IRQ.
53  */
54 static bool sysrst_ctrl_get_irq_bit_index(dif_sysrst_ctrl_irq_t irq,
55  bitfield_bit32_index_t *index_out) {
56  switch (irq) {
57  case kDifSysrstCtrlIrqEventDetected:
58  *index_out = SYSRST_CTRL_INTR_COMMON_EVENT_DETECTED_BIT;
59  break;
60  default:
61  return false;
62  }
63 
64  return true;
65 }
66 
67 static dif_irq_type_t irq_types[] = {
68  kDifIrqTypeStatus,
69 };
70 
71 OT_WARN_UNUSED_RESULT
72 dif_result_t dif_sysrst_ctrl_irq_get_type(const dif_sysrst_ctrl_t *sysrst_ctrl,
73  dif_sysrst_ctrl_irq_t irq,
74  dif_irq_type_t *type) {
75  if (sysrst_ctrl == NULL || type == NULL || irq < 0 ||
76  irq > kDifSysrstCtrlIrqEventDetected) {
77  return kDifBadArg;
78  }
79 
80  *type = irq_types[irq];
81 
82  return kDifOk;
83 }
84 
85 OT_WARN_UNUSED_RESULT
86 dif_result_t dif_sysrst_ctrl_irq_get_state(
87  const dif_sysrst_ctrl_t *sysrst_ctrl,
88  dif_sysrst_ctrl_irq_state_snapshot_t *snapshot) {
89  if (sysrst_ctrl == NULL || snapshot == NULL) {
90  return kDifBadArg;
91  }
92 
93  *snapshot = mmio_region_read32(sysrst_ctrl->base_addr,
94  (ptrdiff_t)SYSRST_CTRL_INTR_STATE_REG_OFFSET);
95 
96  return kDifOk;
97 }
98 
99 OT_WARN_UNUSED_RESULT
100 dif_result_t dif_sysrst_ctrl_irq_acknowledge_state(
101  const dif_sysrst_ctrl_t *sysrst_ctrl,
102  dif_sysrst_ctrl_irq_state_snapshot_t snapshot) {
103  if (sysrst_ctrl == NULL) {
104  return kDifBadArg;
105  }
106 
107  mmio_region_write32(sysrst_ctrl->base_addr,
108  (ptrdiff_t)SYSRST_CTRL_INTR_STATE_REG_OFFSET, snapshot);
109 
110  return kDifOk;
111 }
112 
113 OT_WARN_UNUSED_RESULT
114 dif_result_t dif_sysrst_ctrl_irq_is_pending(
115  const dif_sysrst_ctrl_t *sysrst_ctrl, dif_sysrst_ctrl_irq_t irq,
116  bool *is_pending) {
117  if (sysrst_ctrl == NULL || is_pending == NULL) {
118  return kDifBadArg;
119  }
120 
121  bitfield_bit32_index_t index;
122  if (!sysrst_ctrl_get_irq_bit_index(irq, &index)) {
123  return kDifBadArg;
124  }
125 
126  uint32_t intr_state_reg = mmio_region_read32(
127  sysrst_ctrl->base_addr, (ptrdiff_t)SYSRST_CTRL_INTR_STATE_REG_OFFSET);
128 
129  *is_pending = bitfield_bit32_read(intr_state_reg, index);
130 
131  return kDifOk;
132 }
133 
134 OT_WARN_UNUSED_RESULT
135 dif_result_t dif_sysrst_ctrl_irq_acknowledge_all(
136  const dif_sysrst_ctrl_t *sysrst_ctrl) {
137  if (sysrst_ctrl == NULL) {
138  return kDifBadArg;
139  }
140 
141  // Writing to the register clears the corresponding bits (Write-one clear).
142  mmio_region_write32(sysrst_ctrl->base_addr,
143  (ptrdiff_t)SYSRST_CTRL_INTR_STATE_REG_OFFSET, UINT32_MAX);
144 
145  return kDifOk;
146 }
147 
148 OT_WARN_UNUSED_RESULT
149 dif_result_t dif_sysrst_ctrl_irq_acknowledge(
150  const dif_sysrst_ctrl_t *sysrst_ctrl, dif_sysrst_ctrl_irq_t irq) {
151  if (sysrst_ctrl == NULL) {
152  return kDifBadArg;
153  }
154 
155  bitfield_bit32_index_t index;
156  if (!sysrst_ctrl_get_irq_bit_index(irq, &index)) {
157  return kDifBadArg;
158  }
159 
160  // Writing to the register clears the corresponding bits (Write-one clear).
161  uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
162  mmio_region_write32(sysrst_ctrl->base_addr,
163  (ptrdiff_t)SYSRST_CTRL_INTR_STATE_REG_OFFSET,
164  intr_state_reg);
165 
166  return kDifOk;
167 }
168 
169 OT_WARN_UNUSED_RESULT
170 dif_result_t dif_sysrst_ctrl_irq_force(const dif_sysrst_ctrl_t *sysrst_ctrl,
171  dif_sysrst_ctrl_irq_t irq,
172  const bool val) {
173  if (sysrst_ctrl == NULL) {
174  return kDifBadArg;
175  }
176 
177  bitfield_bit32_index_t index;
178  if (!sysrst_ctrl_get_irq_bit_index(irq, &index)) {
179  return kDifBadArg;
180  }
181 
182  uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
183  mmio_region_write32(sysrst_ctrl->base_addr,
184  (ptrdiff_t)SYSRST_CTRL_INTR_TEST_REG_OFFSET,
185  intr_test_reg);
186 
187  return kDifOk;
188 }
189 
190 OT_WARN_UNUSED_RESULT
191 dif_result_t dif_sysrst_ctrl_irq_get_enabled(
192  const dif_sysrst_ctrl_t *sysrst_ctrl, dif_sysrst_ctrl_irq_t irq,
193  dif_toggle_t *state) {
194  if (sysrst_ctrl == NULL || state == NULL) {
195  return kDifBadArg;
196  }
197 
198  bitfield_bit32_index_t index;
199  if (!sysrst_ctrl_get_irq_bit_index(irq, &index)) {
200  return kDifBadArg;
201  }
202 
203  uint32_t intr_enable_reg = mmio_region_read32(
204  sysrst_ctrl->base_addr, (ptrdiff_t)SYSRST_CTRL_INTR_ENABLE_REG_OFFSET);
205 
206  bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
207  *state = is_enabled ? kDifToggleEnabled : kDifToggleDisabled;
208 
209  return kDifOk;
210 }
211 
212 OT_WARN_UNUSED_RESULT
213 dif_result_t dif_sysrst_ctrl_irq_set_enabled(
214  const dif_sysrst_ctrl_t *sysrst_ctrl, dif_sysrst_ctrl_irq_t irq,
215  dif_toggle_t state) {
216  if (sysrst_ctrl == NULL) {
217  return kDifBadArg;
218  }
219 
220  bitfield_bit32_index_t index;
221  if (!sysrst_ctrl_get_irq_bit_index(irq, &index)) {
222  return kDifBadArg;
223  }
224 
225  uint32_t intr_enable_reg = mmio_region_read32(
226  sysrst_ctrl->base_addr, (ptrdiff_t)SYSRST_CTRL_INTR_ENABLE_REG_OFFSET);
227 
228  bool enable_bit = (state == kDifToggleEnabled) ? true : false;
229  intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
230  mmio_region_write32(sysrst_ctrl->base_addr,
231  (ptrdiff_t)SYSRST_CTRL_INTR_ENABLE_REG_OFFSET,
232  intr_enable_reg);
233 
234  return kDifOk;
235 }
236 
237 OT_WARN_UNUSED_RESULT
238 dif_result_t dif_sysrst_ctrl_irq_disable_all(
239  const dif_sysrst_ctrl_t *sysrst_ctrl,
240  dif_sysrst_ctrl_irq_enable_snapshot_t *snapshot) {
241  if (sysrst_ctrl == NULL) {
242  return kDifBadArg;
243  }
244 
245  // Pass the current interrupt state to the caller, if requested.
246  if (snapshot != NULL) {
247  *snapshot = mmio_region_read32(
248  sysrst_ctrl->base_addr, (ptrdiff_t)SYSRST_CTRL_INTR_ENABLE_REG_OFFSET);
249  }
250 
251  // Disable all interrupts.
252  mmio_region_write32(sysrst_ctrl->base_addr,
253  (ptrdiff_t)SYSRST_CTRL_INTR_ENABLE_REG_OFFSET, 0u);
254 
255  return kDifOk;
256 }
257 
258 OT_WARN_UNUSED_RESULT
259 dif_result_t dif_sysrst_ctrl_irq_restore_all(
260  const dif_sysrst_ctrl_t *sysrst_ctrl,
261  const dif_sysrst_ctrl_irq_enable_snapshot_t *snapshot) {
262  if (sysrst_ctrl == NULL || snapshot == NULL) {
263  return kDifBadArg;
264  }
265 
266  mmio_region_write32(sysrst_ctrl->base_addr,
267  (ptrdiff_t)SYSRST_CTRL_INTR_ENABLE_REG_OFFSET, *snapshot);
268 
269  return kDifOk;
270 }
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