Software APIs
dif_sram_ctrl_unittest.cc
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 #include "sw/device/lib/dif/dif_sram_ctrl.h"
6 
7 #include "gtest/gtest.h"
8 #include "sw/device/lib/base/mmio.h"
9 #include "sw/device/lib/base/mock_mmio.h"
10 #include "sw/device/lib/base/multibits.h"
11 #include "sw/device/lib/dif/dif_base.h"
12 #include "sw/device/lib/dif/dif_test_base.h"
13 
14 #include "sram_ctrl_regs.h" // Generated.
15 
16 namespace dif_sram_ctrl_autogen_unittest {
17 namespace {
18 using ::mock_mmio::MmioTest;
19 using ::mock_mmio::MockDevice;
20 using ::testing::Test;
21 
22 class SramCtrlTest : public Test, public MmioTest {
23  protected:
24  dif_sram_ctrl_t sram_ctrl_ = {.base_addr = dev().region()};
25 };
26 
27 class Scramble : public SramCtrlTest {};
28 
29 TEST_F(Scramble, NullArgs) {
30  EXPECT_DIF_BADARG(dif_sram_ctrl_scramble(nullptr));
31 }
32 
33 TEST_F(Scramble, Locked) {
34  EXPECT_READ32(SRAM_CTRL_CTRL_REGWEN_REG_OFFSET, 0);
35  EXPECT_EQ(dif_sram_ctrl_scramble(&sram_ctrl_), kDifLocked);
36 }
37 
38 TEST_F(Scramble, Failure) {
39  EXPECT_READ32(SRAM_CTRL_CTRL_REGWEN_REG_OFFSET, 1);
40 
41  // Issue request for new scrambling key.
42  EXPECT_WRITE32(SRAM_CTRL_CTRL_REG_OFFSET,
43  {{SRAM_CTRL_CTRL_RENEW_SCR_KEY_BIT, true},
44  {SRAM_CTRL_CTRL_INIT_BIT, false}});
45  EXPECT_READ32(SRAM_CTRL_STATUS_REG_OFFSET, kDifSramCtrlStatusScrKeyValid);
46 
47  // Overwrite memory with pseudo random data.
48  EXPECT_WRITE32(SRAM_CTRL_CTRL_REG_OFFSET,
49  {{SRAM_CTRL_CTRL_RENEW_SCR_KEY_BIT, false},
50  {SRAM_CTRL_CTRL_INIT_BIT, true}});
51  EXPECT_READ32(SRAM_CTRL_STATUS_REG_OFFSET,
52  std::numeric_limits<uint32_t>::max());
53 
54  EXPECT_EQ(dif_sram_ctrl_scramble(&sram_ctrl_), kDifError);
55 }
56 
57 TEST_F(Scramble, Success) {
58  EXPECT_READ32(SRAM_CTRL_CTRL_REGWEN_REG_OFFSET, 1);
59 
60  // Issue request for new scrambling key, and emulate three iteration status
61  // read loop.
62  EXPECT_WRITE32(SRAM_CTRL_CTRL_REG_OFFSET,
63  {{SRAM_CTRL_CTRL_RENEW_SCR_KEY_BIT, true},
64  {SRAM_CTRL_CTRL_INIT_BIT, false}});
65  EXPECT_READ32(SRAM_CTRL_STATUS_REG_OFFSET, 0);
66  EXPECT_READ32(SRAM_CTRL_STATUS_REG_OFFSET, 0);
67  EXPECT_READ32(SRAM_CTRL_STATUS_REG_OFFSET, kDifSramCtrlStatusScrKeyValid);
68 
69  // Overwrite memory with pseudo random data, and emulate three iteration
70  // status read loop.
71  EXPECT_WRITE32(SRAM_CTRL_CTRL_REG_OFFSET,
72  {{SRAM_CTRL_CTRL_RENEW_SCR_KEY_BIT, false},
73  {SRAM_CTRL_CTRL_INIT_BIT, true}});
74  EXPECT_READ32(SRAM_CTRL_STATUS_REG_OFFSET, 0);
75  EXPECT_READ32(SRAM_CTRL_STATUS_REG_OFFSET, 0);
76  EXPECT_READ32(SRAM_CTRL_STATUS_REG_OFFSET, kDifSramCtrlStatusInitDone);
77 
78  EXPECT_DIF_OK(dif_sram_ctrl_scramble(&sram_ctrl_));
79 }
80 
81 class RequestNewKeyTest : public SramCtrlTest {};
82 
83 TEST_F(RequestNewKeyTest, NullArgs) {
84  EXPECT_DIF_BADARG(dif_sram_ctrl_request_new_key(nullptr));
85 }
86 
87 TEST_F(RequestNewKeyTest, Locked) {
88  EXPECT_READ32(SRAM_CTRL_CTRL_REGWEN_REG_OFFSET, 0);
89  EXPECT_EQ(dif_sram_ctrl_request_new_key(&sram_ctrl_), kDifLocked);
90 }
91 
92 TEST_F(RequestNewKeyTest, Success) {
93  EXPECT_READ32(SRAM_CTRL_CTRL_REGWEN_REG_OFFSET, 1);
94  EXPECT_WRITE32(SRAM_CTRL_CTRL_REG_OFFSET,
95  {{SRAM_CTRL_CTRL_RENEW_SCR_KEY_BIT, true},
96  {SRAM_CTRL_CTRL_INIT_BIT, false}});
97  EXPECT_DIF_OK(dif_sram_ctrl_request_new_key(&sram_ctrl_));
98 }
99 
100 class WipeTest : public SramCtrlTest {};
101 
102 TEST_F(WipeTest, NullArgs) {
103  EXPECT_EQ(dif_sram_ctrl_wipe(nullptr), kDifBadArg);
104 }
105 
106 TEST_F(WipeTest, Locked) {
107  EXPECT_READ32(SRAM_CTRL_CTRL_REGWEN_REG_OFFSET, 0);
108  EXPECT_EQ(dif_sram_ctrl_wipe(&sram_ctrl_), kDifLocked);
109 }
110 
111 TEST_F(WipeTest, Success) {
112  EXPECT_READ32(SRAM_CTRL_CTRL_REGWEN_REG_OFFSET, 1);
113  EXPECT_WRITE32(SRAM_CTRL_CTRL_REG_OFFSET,
114  {{SRAM_CTRL_CTRL_RENEW_SCR_KEY_BIT, false},
115  {SRAM_CTRL_CTRL_INIT_BIT, true}});
116  EXPECT_EQ(dif_sram_ctrl_wipe(&sram_ctrl_), kDifOk);
117 }
118 
119 class GetStatusTest : public SramCtrlTest {};
120 
121 TEST_F(GetStatusTest, NullArgs) {
122  dif_sram_ctrl_status_bitfield_t status;
123  EXPECT_DIF_BADARG(dif_sram_ctrl_get_status(&sram_ctrl_, nullptr));
124  EXPECT_DIF_BADARG(dif_sram_ctrl_get_status(nullptr, &status));
125  EXPECT_DIF_BADARG(dif_sram_ctrl_get_status(nullptr, nullptr));
126 }
127 
128 TEST_F(GetStatusTest, SuccessSome) {
129  EXPECT_READ32(SRAM_CTRL_STATUS_REG_OFFSET, 0xA5A5A5A5);
130 
131  dif_sram_ctrl_status_bitfield_t status = 0;
132  EXPECT_DIF_OK(dif_sram_ctrl_get_status(&sram_ctrl_, &status));
133  EXPECT_EQ(status, 0xA5A5A5A5);
134 }
135 
136 TEST_F(GetStatusTest, SuccessAll) {
137  EXPECT_READ32(SRAM_CTRL_STATUS_REG_OFFSET,
138  std::numeric_limits<uint32_t>::max());
139 
140  dif_sram_ctrl_status_bitfield_t status = 0;
141  EXPECT_DIF_OK(dif_sram_ctrl_get_status(&sram_ctrl_, &status));
142  EXPECT_EQ(status, std::numeric_limits<uint32_t>::max());
143 }
144 
145 TEST_F(GetStatusTest, SuccessNone) {
146  EXPECT_READ32(SRAM_CTRL_STATUS_REG_OFFSET, 0);
147 
148  dif_sram_ctrl_status_bitfield_t status = std::numeric_limits<uint32_t>::max();
149  EXPECT_DIF_OK(dif_sram_ctrl_get_status(&sram_ctrl_, &status));
150  EXPECT_EQ(status, 0);
151 }
152 
153 class ExecGetEnabledTest : public SramCtrlTest {};
154 
155 TEST_F(ExecGetEnabledTest, NullArgs) {
156  dif_toggle_t state;
157  EXPECT_DIF_BADARG(dif_sram_ctrl_exec_get_enabled(&sram_ctrl_, nullptr));
158  EXPECT_DIF_BADARG(dif_sram_ctrl_exec_get_enabled(nullptr, &state));
159  EXPECT_DIF_BADARG(dif_sram_ctrl_exec_get_enabled(nullptr, nullptr));
160 }
161 
162 TEST_F(ExecGetEnabledTest, Enabled) {
163  dif_toggle_t state;
164  EXPECT_READ32(SRAM_CTRL_EXEC_REG_OFFSET, kMultiBitBool4True);
165  EXPECT_DIF_OK(dif_sram_ctrl_exec_get_enabled(&sram_ctrl_, &state));
166  EXPECT_EQ(state, kDifToggleEnabled);
167 }
168 
169 TEST_F(ExecGetEnabledTest, Disabled) {
170  dif_toggle_t state = kDifToggleEnabled;
171  EXPECT_READ32(SRAM_CTRL_EXEC_REG_OFFSET, kMultiBitBool4False);
172  EXPECT_DIF_OK(dif_sram_ctrl_exec_get_enabled(&sram_ctrl_, &state));
173  EXPECT_EQ(state, kDifToggleDisabled);
174 
175  state = kDifToggleEnabled;
176  EXPECT_READ32(SRAM_CTRL_EXEC_REG_OFFSET, 0);
177  EXPECT_DIF_OK(dif_sram_ctrl_exec_get_enabled(&sram_ctrl_, &state));
178  EXPECT_EQ(state, kDifToggleDisabled);
179 
180  state = kDifToggleEnabled;
181  EXPECT_READ32(SRAM_CTRL_EXEC_REG_OFFSET,
182  std::numeric_limits<uint32_t>::max());
183  EXPECT_DIF_OK(dif_sram_ctrl_exec_get_enabled(&sram_ctrl_, &state));
184  EXPECT_EQ(state, kDifToggleDisabled);
185 }
186 
187 class ExecSetEnabledTest : public SramCtrlTest {};
188 
189 TEST_F(ExecSetEnabledTest, NullArgs) {
190  EXPECT_DIF_BADARG(dif_sram_ctrl_exec_set_enabled(nullptr, kDifToggleEnabled));
191  EXPECT_DIF_BADARG(
192  dif_sram_ctrl_exec_set_enabled(nullptr, kDifToggleDisabled));
193 }
194 
195 TEST_F(ExecSetEnabledTest, Locked) {
196  EXPECT_READ32(SRAM_CTRL_EXEC_REGWEN_REG_OFFSET, 0x0);
197  EXPECT_EQ(dif_sram_ctrl_exec_set_enabled(&sram_ctrl_, kDifToggleEnabled),
198  kDifLocked);
199 
200  EXPECT_READ32(SRAM_CTRL_EXEC_REGWEN_REG_OFFSET, 0x0);
201  EXPECT_EQ(dif_sram_ctrl_exec_set_enabled(&sram_ctrl_, kDifToggleDisabled),
202  kDifLocked);
203 }
204 
205 TEST_F(ExecSetEnabledTest, Enabled) {
206  EXPECT_READ32(SRAM_CTRL_EXEC_REGWEN_REG_OFFSET, 0x1);
207  EXPECT_WRITE32(SRAM_CTRL_EXEC_REG_OFFSET, kMultiBitBool4True);
208  EXPECT_DIF_OK(dif_sram_ctrl_exec_set_enabled(&sram_ctrl_, kDifToggleEnabled));
209 
210  EXPECT_READ32(SRAM_CTRL_EXEC_REGWEN_REG_OFFSET, 0x1);
211  EXPECT_WRITE32(SRAM_CTRL_EXEC_REG_OFFSET, kMultiBitBool4False);
212  EXPECT_DIF_OK(
213  dif_sram_ctrl_exec_set_enabled(&sram_ctrl_, kDifToggleDisabled));
214 }
215 
216 class LockTest : public SramCtrlTest {};
217 
218 TEST_F(LockTest, NullArgs) {
219  EXPECT_DIF_BADARG(dif_sram_ctrl_lock(nullptr, kDifSramCtrlLockCtrl));
220  EXPECT_DIF_BADARG(dif_sram_ctrl_lock(nullptr, kDifSramCtrlLockExec));
221 }
222 
223 TEST_F(LockTest, Error) {
224  dif_sram_ctrl_lock_t invalid_enum_variant =
225  static_cast<dif_sram_ctrl_lock_t>(std::numeric_limits<uint32_t>::max());
226  EXPECT_EQ(dif_sram_ctrl_lock(&sram_ctrl_, invalid_enum_variant), kDifError);
227 }
228 
229 TEST_F(LockTest, LockCtrl) {
230  EXPECT_WRITE32(SRAM_CTRL_CTRL_REGWEN_REG_OFFSET, 0x0);
231  EXPECT_DIF_OK(dif_sram_ctrl_lock(&sram_ctrl_, kDifSramCtrlLockCtrl));
232  EXPECT_WRITE32(SRAM_CTRL_CTRL_REGWEN_REG_OFFSET, 0x0);
233  EXPECT_DIF_OK(dif_sram_ctrl_lock(&sram_ctrl_, kDifSramCtrlLockCtrl));
234 }
235 
236 TEST_F(LockTest, LockExec) {
237  EXPECT_WRITE32(SRAM_CTRL_EXEC_REGWEN_REG_OFFSET, 0x0);
238  EXPECT_DIF_OK(dif_sram_ctrl_lock(&sram_ctrl_, kDifSramCtrlLockExec));
239  EXPECT_WRITE32(SRAM_CTRL_EXEC_REGWEN_REG_OFFSET, 0x0);
240  EXPECT_DIF_OK(dif_sram_ctrl_lock(&sram_ctrl_, kDifSramCtrlLockExec));
241 }
242 
243 class IsLockedTest : public SramCtrlTest {};
244 
245 TEST_F(IsLockedTest, NullArgs) {
246  bool is_locked;
247  EXPECT_DIF_BADARG(
248  dif_sram_ctrl_is_locked(nullptr, kDifSramCtrlLockCtrl, &is_locked));
249  EXPECT_DIF_BADARG(
250  dif_sram_ctrl_is_locked(nullptr, kDifSramCtrlLockCtrl, nullptr));
251  EXPECT_DIF_BADARG(
252  dif_sram_ctrl_is_locked(&sram_ctrl_, kDifSramCtrlLockCtrl, nullptr));
253 
254  EXPECT_DIF_BADARG(
255  dif_sram_ctrl_is_locked(nullptr, kDifSramCtrlLockExec, &is_locked));
256  EXPECT_DIF_BADARG(
257  dif_sram_ctrl_is_locked(nullptr, kDifSramCtrlLockExec, nullptr));
258  EXPECT_DIF_BADARG(
259  dif_sram_ctrl_is_locked(&sram_ctrl_, kDifSramCtrlLockExec, nullptr));
260 }
261 
262 TEST_F(IsLockedTest, Error) {
263  bool is_locked;
264  dif_sram_ctrl_lock_t invalid_enum_variant =
265  static_cast<dif_sram_ctrl_lock_t>(std::numeric_limits<uint32_t>::max());
266  EXPECT_EQ(
267  dif_sram_ctrl_is_locked(&sram_ctrl_, invalid_enum_variant, &is_locked),
268  kDifError);
269 }
270 
271 TEST_F(IsLockedTest, Ctrl) {
272  bool is_locked = true;
273  EXPECT_READ32(SRAM_CTRL_CTRL_REGWEN_REG_OFFSET, 0x1);
274  EXPECT_DIF_OK(
275  dif_sram_ctrl_is_locked(&sram_ctrl_, kDifSramCtrlLockCtrl, &is_locked));
276  EXPECT_EQ(is_locked, false);
277 
278  is_locked = false;
279  EXPECT_READ32(SRAM_CTRL_CTRL_REGWEN_REG_OFFSET, 0x0);
280  EXPECT_DIF_OK(
281  dif_sram_ctrl_is_locked(&sram_ctrl_, kDifSramCtrlLockCtrl, &is_locked));
282  EXPECT_EQ(is_locked, true);
283 }
284 
285 TEST_F(IsLockedTest, Exec) {
286  bool is_locked = true;
287  EXPECT_READ32(SRAM_CTRL_EXEC_REGWEN_REG_OFFSET, 0x1);
288  EXPECT_DIF_OK(
289  dif_sram_ctrl_is_locked(&sram_ctrl_, kDifSramCtrlLockExec, &is_locked));
290  EXPECT_EQ(is_locked, false);
291 
292  is_locked = false;
293  EXPECT_READ32(SRAM_CTRL_EXEC_REGWEN_REG_OFFSET, 0x0);
294  EXPECT_DIF_OK(
295  dif_sram_ctrl_is_locked(&sram_ctrl_, kDifSramCtrlLockExec, &is_locked));
296  EXPECT_EQ(is_locked, true);
297 }
298 
299 class RotatedTest : public SramCtrlTest {};
300 
301 TEST_F(RotatedTest, NullArgs) {
302  multi_bit_bool_t success;
303  EXPECT_DIF_BADARG(
304  dif_sram_ctrl_scr_key_rotated(nullptr, &success, kMultiBitBool4False));
305  EXPECT_DIF_BADARG(
306  dif_sram_ctrl_scr_key_rotated(nullptr, nullptr, kMultiBitBool4False));
307  EXPECT_DIF_BADARG(
308  dif_sram_ctrl_scr_key_rotated(&sram_ctrl_, nullptr, kMultiBitBool4False));
309 }
310 
311 TEST_F(IsLockedTest, Rotated0) {
312  multi_bit_bool_t success = kMultiBitBool4True;
313  EXPECT_READ32(SRAM_CTRL_SCR_KEY_ROTATED_REG_OFFSET, kMultiBitBool4False);
314  EXPECT_WRITE32(SRAM_CTRL_SCR_KEY_ROTATED_REG_OFFSET, kMultiBitBool4False);
315  EXPECT_DIF_OK(dif_sram_ctrl_scr_key_rotated(&sram_ctrl_, &success,
316  kMultiBitBool4False));
317  EXPECT_EQ(success, kMultiBitBool4False);
318 }
319 
320 TEST_F(IsLockedTest, Rotated1) {
321  multi_bit_bool_t success = kMultiBitBool4False;
322  EXPECT_READ32(SRAM_CTRL_SCR_KEY_ROTATED_REG_OFFSET, kMultiBitBool4True);
323  EXPECT_WRITE32(SRAM_CTRL_SCR_KEY_ROTATED_REG_OFFSET, kMultiBitBool4True);
324  EXPECT_DIF_OK(
325  dif_sram_ctrl_scr_key_rotated(&sram_ctrl_, &success, kMultiBitBool4True));
326  EXPECT_EQ(success, kMultiBitBool4True);
327 }
328 
329 TEST_F(IsLockedTest, Rotated2) {
330  multi_bit_bool_t success = kMultiBitBool4False;
331  EXPECT_READ32(SRAM_CTRL_SCR_KEY_ROTATED_REG_OFFSET, kMultiBitBool4True);
332  EXPECT_WRITE32(SRAM_CTRL_SCR_KEY_ROTATED_REG_OFFSET, kMultiBitBool4False);
333  EXPECT_DIF_OK(dif_sram_ctrl_scr_key_rotated(&sram_ctrl_, &success,
334  kMultiBitBool4False));
335  EXPECT_EQ(success, kMultiBitBool4True);
336 }
337 
338 } // namespace
339 } // namespace dif_sram_ctrl_autogen_unittest
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