Software APIs
dif_spi_host_autogen.c
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 // THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
6 // util/make_new_dif.py --mode=regen --only=autogen
7 
8 #include "sw/device/lib/dif/autogen/dif_spi_host_autogen.h"
9 
10 #include <stdint.h>
11 
12 #include "sw/device/lib/dif/dif_base.h"
13 
14 #include "spi_host_regs.h" // Generated.
15 
16 OT_WARN_UNUSED_RESULT
17 dif_result_t dif_spi_host_init(mmio_region_t base_addr,
18  dif_spi_host_t *spi_host) {
19  if (spi_host == NULL) {
20  return kDifBadArg;
21  }
22 
23  spi_host->base_addr = base_addr;
24 
25  return kDifOk;
26 }
27 
28 dif_result_t dif_spi_host_alert_force(const dif_spi_host_t *spi_host,
29  dif_spi_host_alert_t alert) {
30  if (spi_host == NULL) {
31  return kDifBadArg;
32  }
33 
34  bitfield_bit32_index_t alert_idx;
35  switch (alert) {
36  case kDifSpiHostAlertFatalFault:
37  alert_idx = SPI_HOST_ALERT_TEST_FATAL_FAULT_BIT;
38  break;
39  default:
40  return kDifBadArg;
41  }
42 
43  uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx, true);
44  mmio_region_write32(spi_host->base_addr,
45  (ptrdiff_t)SPI_HOST_ALERT_TEST_REG_OFFSET,
46  alert_test_reg);
47 
48  return kDifOk;
49 }
50 
51 /**
52  * Get the corresponding interrupt register bit offset of the IRQ.
53  */
54 static bool spi_host_get_irq_bit_index(dif_spi_host_irq_t irq,
55  bitfield_bit32_index_t *index_out) {
56  switch (irq) {
57  case kDifSpiHostIrqError:
58  *index_out = SPI_HOST_INTR_COMMON_ERROR_BIT;
59  break;
60  case kDifSpiHostIrqSpiEvent:
61  *index_out = SPI_HOST_INTR_COMMON_SPI_EVENT_BIT;
62  break;
63  default:
64  return false;
65  }
66 
67  return true;
68 }
69 
70 static dif_irq_type_t irq_types[] = {
71  kDifIrqTypeEvent,
72  kDifIrqTypeStatus,
73 };
74 
75 OT_WARN_UNUSED_RESULT
76 dif_result_t dif_spi_host_irq_get_type(const dif_spi_host_t *spi_host,
77  dif_spi_host_irq_t irq,
78  dif_irq_type_t *type) {
79  if (spi_host == NULL || type == NULL || irq < 0 ||
80  irq > kDifSpiHostIrqSpiEvent) {
81  return kDifBadArg;
82  }
83 
84  *type = irq_types[irq];
85 
86  return kDifOk;
87 }
88 
89 OT_WARN_UNUSED_RESULT
90 dif_result_t dif_spi_host_irq_get_state(
91  const dif_spi_host_t *spi_host,
92  dif_spi_host_irq_state_snapshot_t *snapshot) {
93  if (spi_host == NULL || snapshot == NULL) {
94  return kDifBadArg;
95  }
96 
97  *snapshot = mmio_region_read32(spi_host->base_addr,
98  (ptrdiff_t)SPI_HOST_INTR_STATE_REG_OFFSET);
99 
100  return kDifOk;
101 }
102 
103 OT_WARN_UNUSED_RESULT
104 dif_result_t dif_spi_host_irq_acknowledge_state(
105  const dif_spi_host_t *spi_host,
106  dif_spi_host_irq_state_snapshot_t snapshot) {
107  if (spi_host == NULL) {
108  return kDifBadArg;
109  }
110 
111  mmio_region_write32(spi_host->base_addr,
112  (ptrdiff_t)SPI_HOST_INTR_STATE_REG_OFFSET, snapshot);
113 
114  return kDifOk;
115 }
116 
117 OT_WARN_UNUSED_RESULT
118 dif_result_t dif_spi_host_irq_is_pending(const dif_spi_host_t *spi_host,
119  dif_spi_host_irq_t irq,
120  bool *is_pending) {
121  if (spi_host == NULL || is_pending == NULL) {
122  return kDifBadArg;
123  }
124 
125  bitfield_bit32_index_t index;
126  if (!spi_host_get_irq_bit_index(irq, &index)) {
127  return kDifBadArg;
128  }
129 
130  uint32_t intr_state_reg = mmio_region_read32(
131  spi_host->base_addr, (ptrdiff_t)SPI_HOST_INTR_STATE_REG_OFFSET);
132 
133  *is_pending = bitfield_bit32_read(intr_state_reg, index);
134 
135  return kDifOk;
136 }
137 
138 OT_WARN_UNUSED_RESULT
139 dif_result_t dif_spi_host_irq_acknowledge_all(const dif_spi_host_t *spi_host) {
140  if (spi_host == NULL) {
141  return kDifBadArg;
142  }
143 
144  // Writing to the register clears the corresponding bits (Write-one clear).
145  mmio_region_write32(spi_host->base_addr,
146  (ptrdiff_t)SPI_HOST_INTR_STATE_REG_OFFSET, UINT32_MAX);
147 
148  return kDifOk;
149 }
150 
151 OT_WARN_UNUSED_RESULT
152 dif_result_t dif_spi_host_irq_acknowledge(const dif_spi_host_t *spi_host,
153  dif_spi_host_irq_t irq) {
154  if (spi_host == NULL) {
155  return kDifBadArg;
156  }
157 
158  bitfield_bit32_index_t index;
159  if (!spi_host_get_irq_bit_index(irq, &index)) {
160  return kDifBadArg;
161  }
162 
163  // Writing to the register clears the corresponding bits (Write-one clear).
164  uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
165  mmio_region_write32(spi_host->base_addr,
166  (ptrdiff_t)SPI_HOST_INTR_STATE_REG_OFFSET,
167  intr_state_reg);
168 
169  return kDifOk;
170 }
171 
172 OT_WARN_UNUSED_RESULT
173 dif_result_t dif_spi_host_irq_force(const dif_spi_host_t *spi_host,
174  dif_spi_host_irq_t irq, const bool val) {
175  if (spi_host == NULL) {
176  return kDifBadArg;
177  }
178 
179  bitfield_bit32_index_t index;
180  if (!spi_host_get_irq_bit_index(irq, &index)) {
181  return kDifBadArg;
182  }
183 
184  uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
185  mmio_region_write32(spi_host->base_addr,
186  (ptrdiff_t)SPI_HOST_INTR_TEST_REG_OFFSET, intr_test_reg);
187 
188  return kDifOk;
189 }
190 
191 OT_WARN_UNUSED_RESULT
192 dif_result_t dif_spi_host_irq_get_enabled(const dif_spi_host_t *spi_host,
193  dif_spi_host_irq_t irq,
194  dif_toggle_t *state) {
195  if (spi_host == NULL || state == NULL) {
196  return kDifBadArg;
197  }
198 
199  bitfield_bit32_index_t index;
200  if (!spi_host_get_irq_bit_index(irq, &index)) {
201  return kDifBadArg;
202  }
203 
204  uint32_t intr_enable_reg = mmio_region_read32(
205  spi_host->base_addr, (ptrdiff_t)SPI_HOST_INTR_ENABLE_REG_OFFSET);
206 
207  bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
208  *state = is_enabled ? kDifToggleEnabled : kDifToggleDisabled;
209 
210  return kDifOk;
211 }
212 
213 OT_WARN_UNUSED_RESULT
214 dif_result_t dif_spi_host_irq_set_enabled(const dif_spi_host_t *spi_host,
215  dif_spi_host_irq_t irq,
216  dif_toggle_t state) {
217  if (spi_host == NULL) {
218  return kDifBadArg;
219  }
220 
221  bitfield_bit32_index_t index;
222  if (!spi_host_get_irq_bit_index(irq, &index)) {
223  return kDifBadArg;
224  }
225 
226  uint32_t intr_enable_reg = mmio_region_read32(
227  spi_host->base_addr, (ptrdiff_t)SPI_HOST_INTR_ENABLE_REG_OFFSET);
228 
229  bool enable_bit = (state == kDifToggleEnabled) ? true : false;
230  intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
231  mmio_region_write32(spi_host->base_addr,
232  (ptrdiff_t)SPI_HOST_INTR_ENABLE_REG_OFFSET,
233  intr_enable_reg);
234 
235  return kDifOk;
236 }
237 
238 OT_WARN_UNUSED_RESULT
239 dif_result_t dif_spi_host_irq_disable_all(
240  const dif_spi_host_t *spi_host,
241  dif_spi_host_irq_enable_snapshot_t *snapshot) {
242  if (spi_host == NULL) {
243  return kDifBadArg;
244  }
245 
246  // Pass the current interrupt state to the caller, if requested.
247  if (snapshot != NULL) {
248  *snapshot = mmio_region_read32(spi_host->base_addr,
249  (ptrdiff_t)SPI_HOST_INTR_ENABLE_REG_OFFSET);
250  }
251 
252  // Disable all interrupts.
253  mmio_region_write32(spi_host->base_addr,
254  (ptrdiff_t)SPI_HOST_INTR_ENABLE_REG_OFFSET, 0u);
255 
256  return kDifOk;
257 }
258 
259 OT_WARN_UNUSED_RESULT
260 dif_result_t dif_spi_host_irq_restore_all(
261  const dif_spi_host_t *spi_host,
262  const dif_spi_host_irq_enable_snapshot_t *snapshot) {
263  if (spi_host == NULL || snapshot == NULL) {
264  return kDifBadArg;
265  }
266 
267  mmio_region_write32(spi_host->base_addr,
268  (ptrdiff_t)SPI_HOST_INTR_ENABLE_REG_OFFSET, *snapshot);
269 
270  return kDifOk;
271 }
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