Software APIs
dif_spi_host_autogen.c
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 // THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
6 // util/make_new_dif.py --mode=regen --only=autogen
7 
8 #include "sw/device/lib/dif/autogen/dif_spi_host_autogen.h"
9 
10 #include <stdint.h>
11 
12 #include "sw/device/lib/dif/dif_base.h"
13 
14 #include "spi_host_regs.h" // Generated.
15 
16 OT_WARN_UNUSED_RESULT
17 dif_result_t dif_spi_host_init(mmio_region_t base_addr,
18  dif_spi_host_t *spi_host) {
19  if (spi_host == NULL) {
20  return kDifBadArg;
21  }
22 
23  spi_host->base_addr = base_addr;
24 
25  return kDifOk;
26 }
27 
28 dif_result_t dif_spi_host_alert_force(const dif_spi_host_t *spi_host,
29  dif_spi_host_alert_t alert) {
30  if (spi_host == NULL) {
31  return kDifBadArg;
32  }
33 
34  bitfield_bit32_index_t alert_idx;
35  switch (alert) {
36  case kDifSpiHostAlertFatalFault:
37  alert_idx = SPI_HOST_ALERT_TEST_FATAL_FAULT_BIT;
38  break;
39  default:
40  return kDifBadArg;
41  }
42 
43  uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx, true);
44  mmio_region_write32(spi_host->base_addr,
45  (ptrdiff_t)SPI_HOST_ALERT_TEST_REG_OFFSET,
46  alert_test_reg);
47 
48  return kDifOk;
49 }
50 
51 /**
52  * Get the corresponding interrupt register bit offset of the IRQ.
53  */
54 static bool spi_host_get_irq_bit_index(dif_spi_host_irq_t irq,
55  bitfield_bit32_index_t *index_out) {
56  switch (irq) {
57  case kDifSpiHostIrqError:
58  *index_out = SPI_HOST_INTR_COMMON_ERROR_BIT;
59  break;
60  case kDifSpiHostIrqSpiEvent:
61  *index_out = SPI_HOST_INTR_COMMON_SPI_EVENT_BIT;
62  break;
63  default:
64  return false;
65  }
66 
67  return true;
68 }
69 
70 static dif_irq_type_t irq_types[] = {
71  kDifIrqTypeEvent,
72  kDifIrqTypeStatus,
73 };
74 
75 OT_WARN_UNUSED_RESULT
76 dif_result_t dif_spi_host_irq_get_type(const dif_spi_host_t *spi_host,
77  dif_spi_host_irq_t irq,
78  dif_irq_type_t *type) {
79  if (spi_host == NULL || type == NULL || irq == kDifSpiHostIrqSpiEvent + 1) {
80  return kDifBadArg;
81  }
82 
83  *type = irq_types[irq];
84 
85  return kDifOk;
86 }
87 
88 OT_WARN_UNUSED_RESULT
89 dif_result_t dif_spi_host_irq_get_state(
90  const dif_spi_host_t *spi_host,
91  dif_spi_host_irq_state_snapshot_t *snapshot) {
92  if (spi_host == NULL || snapshot == NULL) {
93  return kDifBadArg;
94  }
95 
96  *snapshot = mmio_region_read32(spi_host->base_addr,
97  (ptrdiff_t)SPI_HOST_INTR_STATE_REG_OFFSET);
98 
99  return kDifOk;
100 }
101 
102 OT_WARN_UNUSED_RESULT
103 dif_result_t dif_spi_host_irq_acknowledge_state(
104  const dif_spi_host_t *spi_host,
105  dif_spi_host_irq_state_snapshot_t snapshot) {
106  if (spi_host == NULL) {
107  return kDifBadArg;
108  }
109 
110  mmio_region_write32(spi_host->base_addr,
111  (ptrdiff_t)SPI_HOST_INTR_STATE_REG_OFFSET, snapshot);
112 
113  return kDifOk;
114 }
115 
116 OT_WARN_UNUSED_RESULT
117 dif_result_t dif_spi_host_irq_is_pending(const dif_spi_host_t *spi_host,
118  dif_spi_host_irq_t irq,
119  bool *is_pending) {
120  if (spi_host == NULL || is_pending == NULL) {
121  return kDifBadArg;
122  }
123 
124  bitfield_bit32_index_t index;
125  if (!spi_host_get_irq_bit_index(irq, &index)) {
126  return kDifBadArg;
127  }
128 
129  uint32_t intr_state_reg = mmio_region_read32(
130  spi_host->base_addr, (ptrdiff_t)SPI_HOST_INTR_STATE_REG_OFFSET);
131 
132  *is_pending = bitfield_bit32_read(intr_state_reg, index);
133 
134  return kDifOk;
135 }
136 
137 OT_WARN_UNUSED_RESULT
138 dif_result_t dif_spi_host_irq_acknowledge_all(const dif_spi_host_t *spi_host) {
139  if (spi_host == NULL) {
140  return kDifBadArg;
141  }
142 
143  // Writing to the register clears the corresponding bits (Write-one clear).
144  mmio_region_write32(spi_host->base_addr,
145  (ptrdiff_t)SPI_HOST_INTR_STATE_REG_OFFSET, UINT32_MAX);
146 
147  return kDifOk;
148 }
149 
150 OT_WARN_UNUSED_RESULT
151 dif_result_t dif_spi_host_irq_acknowledge(const dif_spi_host_t *spi_host,
152  dif_spi_host_irq_t irq) {
153  if (spi_host == NULL) {
154  return kDifBadArg;
155  }
156 
157  bitfield_bit32_index_t index;
158  if (!spi_host_get_irq_bit_index(irq, &index)) {
159  return kDifBadArg;
160  }
161 
162  // Writing to the register clears the corresponding bits (Write-one clear).
163  uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
164  mmio_region_write32(spi_host->base_addr,
165  (ptrdiff_t)SPI_HOST_INTR_STATE_REG_OFFSET,
166  intr_state_reg);
167 
168  return kDifOk;
169 }
170 
171 OT_WARN_UNUSED_RESULT
172 dif_result_t dif_spi_host_irq_force(const dif_spi_host_t *spi_host,
173  dif_spi_host_irq_t irq, const bool val) {
174  if (spi_host == NULL) {
175  return kDifBadArg;
176  }
177 
178  bitfield_bit32_index_t index;
179  if (!spi_host_get_irq_bit_index(irq, &index)) {
180  return kDifBadArg;
181  }
182 
183  uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
184  mmio_region_write32(spi_host->base_addr,
185  (ptrdiff_t)SPI_HOST_INTR_TEST_REG_OFFSET, intr_test_reg);
186 
187  return kDifOk;
188 }
189 
190 OT_WARN_UNUSED_RESULT
191 dif_result_t dif_spi_host_irq_get_enabled(const dif_spi_host_t *spi_host,
192  dif_spi_host_irq_t irq,
193  dif_toggle_t *state) {
194  if (spi_host == NULL || state == NULL) {
195  return kDifBadArg;
196  }
197 
198  bitfield_bit32_index_t index;
199  if (!spi_host_get_irq_bit_index(irq, &index)) {
200  return kDifBadArg;
201  }
202 
203  uint32_t intr_enable_reg = mmio_region_read32(
204  spi_host->base_addr, (ptrdiff_t)SPI_HOST_INTR_ENABLE_REG_OFFSET);
205 
206  bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
207  *state = is_enabled ? kDifToggleEnabled : kDifToggleDisabled;
208 
209  return kDifOk;
210 }
211 
212 OT_WARN_UNUSED_RESULT
213 dif_result_t dif_spi_host_irq_set_enabled(const dif_spi_host_t *spi_host,
214  dif_spi_host_irq_t irq,
215  dif_toggle_t state) {
216  if (spi_host == NULL) {
217  return kDifBadArg;
218  }
219 
220  bitfield_bit32_index_t index;
221  if (!spi_host_get_irq_bit_index(irq, &index)) {
222  return kDifBadArg;
223  }
224 
225  uint32_t intr_enable_reg = mmio_region_read32(
226  spi_host->base_addr, (ptrdiff_t)SPI_HOST_INTR_ENABLE_REG_OFFSET);
227 
228  bool enable_bit = (state == kDifToggleEnabled) ? true : false;
229  intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
230  mmio_region_write32(spi_host->base_addr,
231  (ptrdiff_t)SPI_HOST_INTR_ENABLE_REG_OFFSET,
232  intr_enable_reg);
233 
234  return kDifOk;
235 }
236 
237 OT_WARN_UNUSED_RESULT
238 dif_result_t dif_spi_host_irq_disable_all(
239  const dif_spi_host_t *spi_host,
240  dif_spi_host_irq_enable_snapshot_t *snapshot) {
241  if (spi_host == NULL) {
242  return kDifBadArg;
243  }
244 
245  // Pass the current interrupt state to the caller, if requested.
246  if (snapshot != NULL) {
247  *snapshot = mmio_region_read32(spi_host->base_addr,
248  (ptrdiff_t)SPI_HOST_INTR_ENABLE_REG_OFFSET);
249  }
250 
251  // Disable all interrupts.
252  mmio_region_write32(spi_host->base_addr,
253  (ptrdiff_t)SPI_HOST_INTR_ENABLE_REG_OFFSET, 0u);
254 
255  return kDifOk;
256 }
257 
258 OT_WARN_UNUSED_RESULT
259 dif_result_t dif_spi_host_irq_restore_all(
260  const dif_spi_host_t *spi_host,
261  const dif_spi_host_irq_enable_snapshot_t *snapshot) {
262  if (spi_host == NULL || snapshot == NULL) {
263  return kDifBadArg;
264  }
265 
266  mmio_region_write32(spi_host->base_addr,
267  (ptrdiff_t)SPI_HOST_INTR_ENABLE_REG_OFFSET, *snapshot);
268 
269  return kDifOk;
270 }
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