Software APIs
dif_spi_device.h
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1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 #ifndef OPENTITAN_SW_DEVICE_LIB_DIF_DIF_SPI_DEVICE_H_
6 #define OPENTITAN_SW_DEVICE_LIB_DIF_DIF_SPI_DEVICE_H_
7 
8 /**
9  * @file
10  * @brief <a href="/hw/ip/spi_device/doc/">SPI Device</a> Device Interface
11  * Functions
12  */
13 
14 #include <stddef.h>
15 #include <stdint.h>
16 
20 
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif // __cplusplus
26 
27 /**
28  * The mode that the spi device operates in.
29  */
30 typedef enum dif_spi_device_mode {
31  /**
32  * spi_device will ignore all transactions in this mode configuration.
33  */
35  /**
36  * In flash emulation mode, the hardware behaves like a SPI NOR flash device.
37  */
39  /**
40  * In pass-through mode, the hardware forwards commands to another SPI flash
41  * device, with various tables providing rules for filtering and forwarding.
42  * The hardware may be configured to also behave like a SPI NOR flash device,
43  * with some commands and/or address regions targeting internal handling,
44  * instead of being passed through.
45  */
48 
49 /**
50  * A bit ordering within a byte.
51  */
53  /**
54  * Represents the most-significant-bit to least-significant-bit order.
55  */
57  /**
58  * Represents the least-significant-bit to most-significant-bit order.
59  */
62 
63 /**
64  * Runtime configuration for SPI.
65  *
66  * This struct describes runtime information for one-time configuration of the
67  * hardware.
68  */
69 typedef struct dif_spi_device_config {
72  dif_spi_device_mode_t device_mode;
74 
75 /**
76  * Struct containing the relevant run-time information for the DIF.
77  */
78 typedef struct dif_spi_device_handle {
79  /**
80  * Device information of the hardware.
81  */
83  /**
84  * Configuration information of the hardware.
85  */
88 
89 /**
90  * The length of the SPI device FIFO buffer, in bytes.
91  *
92  * Useful for initializing FIFO lengths: for example, for equally-sized FIFOs,
93  * `rx_fifo_len` and `tx_fifo_len` would be set to `kDifSpiDeviceBufferLen / 2`.
94  */
95 extern const uint16_t kDifSpiDeviceBufferLen;
96 
97 /**
98  * Initializes a SPI device handle for use.
99  *
100  * @param base_addr The MMIO base address of the spi_device peripheral.
101  * @param[out] Out param for the initialized handle.
102  * @return The result of the operation.
103  */
107 
108 /**
109  * Configures SPI with runtime information.
110  *
111  * This function should need to be called once for the lifetime of `handle`.
112  *
113  * @param spi A SPI handle.
114  * @param config Runtime configuration parameters.
115  * @return The result of the operation.
116  */
119  dif_spi_device_config_t config);
120 
121 /**
122  * Turn on/off passthrough without changing any other configuration.
123  *
124  * This changes the mode to one of flash mode or passthrough mode. The current
125  * mode must be one of those, else this function will fail.
126  *
127  * @param spi A SPI handle.
128  * @param enable Whether to turn on passthrough mode.
129  * @return The result of the operation.
130  */
133  dif_toggle_t enable);
134 
135 /**
136  * Get the current level of the CSB pin.
137  *
138  * This is available for the esoteric case where CSB is used like a slow GPIO.
139  * Note that for ordinary SPI operation, software sampling of the CSB pin cannot
140  * be used to determine whether it is safe to perform an operation where the
141  * host must be inactive.
142  *
143  * @param spi A SPI handle.
144  * @param[out] csb The current value of the chip-select pin (false for asserted,
145  * true for deasserted).
146  * @return The result of the operation.
147  */
150  bool *csb);
151 
152 /**
153  * Enable the mailbox region for spi_device flash / passthrough modes.
154  *
155  * Allocate 1 KiB for the mailbox, starting from the provided base `address`.
156  *
157  * @param spi A SPI device.
158  * @param address The base address of the 1 KiB mailbox. The lower 10 bits are
159  * ignored.
160  * @return kDifBadArg if spi is null, else kDifOk.
161  */
164  uint32_t address);
165 
166 /**
167  * Disable the mailbox region for spi_device flash / passthrough modes.
168  *
169  * @param spi A SPI device.
170  * @return kDifBadArg if spi is null, else kDifOk.
171  */
174 
175 /**
176  * Get the active configuration for the mailbox region.
177  *
178  * @param spi A SPI device.
179  * @param[out] is_enabled Whether the mailbox region is enabled.
180  * @param[out] address If the mailbox is enabled, the base address of the
181  * mailbox region.
182  * @return kDifBadArg if any argument is null, else kDifOk.
183  */
186  dif_spi_device_handle_t *spi, dif_toggle_t *is_enabled, uint32_t *address);
187 
188 /**
189  * Set the address mode of the SPI device in flash/passthrough mode.
190  *
191  * @param spi A SPI device.
192  * @param addr_4b If kDifToggleEnabled, set the address mode to 4 Bytes.
193  * Otherwise, set the address mode to 3 Bytes.
194  * @return kDifBadArg if spi is NULL or addr_4b is not a valid toggle. kDifOk
195  * otherwise.
196  */
199  dif_toggle_t addr_4b);
200 /**
201  * Get the address mode of the SPI device in flash/passthrough mode.
202  *
203  * @param spi A SPI device.
204  * @param[out] addr_4b Points to toggle that will be set to `kDifToggleEnabled`
205  * if the device is in 4-byte address mode, else `kDifToggleDisabled`.
206  * @return kDifBadArg if spi or addr_4b are NULL. kDifOk otherwise.
207  */
210  dif_toggle_t *addr_4b);
211 
212 /**
213  * Clear any pending software-originated flash status change requests.
214  *
215  * @param spi A SPI device.
216  * @return kDifBadArg if spi is NULL. kDifOk otherwise.
217  */
221 
222 typedef struct dif_spi_device_flash_id {
223  /** The device ID for the SPI flash. */
224  uint16_t device_id;
225  /** The JEDEC manufacturer ID. */
227  /** The continuation code used before the `manufacturer_id` byte. */
229  /** The number of continuation codes preceding the `manufacturer_id`. */
232 
233 /**
234  * Get the JEDEC ID presented when in flash / passthrough modes.
235  *
236  * @param spi A SPI device.
237  * @param[out] id Points to location that will be set to the current JEDEC ID.
238  * @return kDifBadArg if spi or id are NULL. kDifOk otherwise.
239  */
243 /**
244  * Set the JEDEC ID presented when in flash / passthrough modes.
245  *
246  * @param spi A SPI device.
247  * @param id The JEDEC ID to set.
248  * @return kDifBadArg if spi is NULL. kDifOk otherwise.
249  */
253 
254 /**
255  * Represents which optional hardware features may intercept commands in
256  * passthrough mode. If selected, the function will be handled internally and
257  * not passed to the downstream SPI flash (sometimes with conditions, such as
258  * the address matching the mailbox region when mailbox interception is
259  * selected).
260  */
262  /**
263  * Whether to intercept commands to the status registers, such as WriteStatus
264  * and ReadStatus.
265  */
266  bool status;
267  /**
268  * Whether to intercept the ReadID command and respond with the JEDEC ID
269  * programmed via `dif_spi_device_set_flash_id()`.
270  */
271  bool jedec_id;
272  /**
273  * Whether to intercept the ReadSFDP command with data programmed to the
274  * internal SFDP region.
275  */
276  bool sfdp;
277  /**
278  * Whether to intercept read memory commands with data programmed in the
279  * mailbox buffer, when the address is inside the mailbox region.
280  */
281  bool mailbox;
283 
284 /**
285  * Configure the optional hardware functions to intercept passthrough commands.
286  *
287  * @param spi A SPI handle.
288  * @param config The passthrough interception configuration.
289  * @return The result of the operation.
290  */
295 
296 /**
297  * Get the last address read from the flash memory that was not in the mailbox
298  * region.
299  *
300  * @param spi A SPI handle.
301  * @param[out] address The last address read.
302  * @return The result of the operation.
303  */
306  uint32_t *address);
307 
308 /**
309  * Set the read threshold watermark for reporting to the corresponding interrupt
310  * status bit.
311  *
312  * This function is intended to be used in flash mode for devices that
313  * sequentially read from address 0 to the end of some initial block. A supplied
314  * address of 0 disables the watermark status bit and interrupt.
315  *
316  * @param spi A SPI handle.
317  * @param address The watermark address that triggers reporting to the read
318  * threshold watermark's status bit, which can signal an interrupt.
319  * @return The result of the operation.
320  */
323  dif_spi_device_handle_t *spi, uint32_t address);
324 
325 /**
326  * Clear eflash read buffer state.
327  *
328  * Reinitialize the eflash read buffer to initial state.
329  *
330  * @param spi A SPI device.
331  * @return kDifBadArg if spi is NULL. kDifOk otherwise.
332  */
335 
337  /** No address for this command */
339  /** Address size for this command is determined by the current address mode */
341  /** Address size for this command is fixed at 3 bytes */
343  /** Address size for this command is fixed at 4 bytes */
345  kDifSpiDeviceFlashAddrCount,
346 } dif_spi_device_flash_address_type_t;
347 
348 /** An enum describing the type of I/O width used by a command's payload. */
350  /** Command does not have a payload. */
352  /** Command's payload has an I/O channel width of 1. */
354  /** Command's payload has an I/O channel width of 2. */
356  /** Command's payload has an I/O channel width of 4. */
358  /** The command info slot had an invalid setting for the payload I/O width. */
361 
363  /** No additional flash payload read pipeline stages. */
365  /**
366  * Add 2-stage pipeline to command read output. Perform half-cycle sampling on
367  * the incoming data.
368  */
370  /**
371  * Add 2-stage pipeline to command read output. Perform full-cycle sampling on
372  * the incoming data.
373  */
375  kDifSpiDeviceReadPipelineModeCount,
376 } dif_spi_device_read_pipeline_mode_t;
377 
379  /** The opcode for this command. */
380  uint8_t opcode;
381  /* The presence and type of the address phase of this command. */
382  dif_spi_device_flash_address_type_t address_type;
383  /** The number of dummy cycles between the address phase and the payload phase
384  * of a command. Note that if `payload_io_width` is
385  * `kDifSpiDevicePayloadIoNone`, a nonzero value may cause undefined behavior,
386  * possibly including the device assuming dummy cycles are part of this
387  * payload-less command.
388  */
389  uint8_t dummy_cycles;
390  /** The I/O width for the payload phase of this command. */
392  /**
393  * Whether to translate the address using the address swap mask and value
394  * provided to `dif_spi_device_passthrough_set_swap_address()`. Incompatible
395  * with a command with `address_type` that is
396  * `kDifSpiDeviceFlashAddrDisabled`.
397  */
399  /** Whether the SPI host is receiving this command's payload phase. */
401  /** Whether to swap up to the first 32 bits of the payload. */
403  /** The read payload pipeline mode to use for this command. */
404  dif_spi_device_read_pipeline_mode_t read_pipeline_mode;
405  /** Whether to upload the command to the payload FIFO. */
406  bool upload;
407  /** Whether to set the busy bit in the status register. */
410 
412  /** eFlash region */
414  /** Mailbox region */
416  /** SFDP region */
418  /** Count of buffer types */
420 } dif_spi_device_flash_buffer_type_t;
421 
422 /**
423  * Set up the indicated command info slot for flash / passthrough modes.
424  *
425  * @param spi A handle to a spi device.
426  * @param slot A command info slot ID.
427  * @param enable Whether to enable or disable the command slot.
428  * @param command_info If `enable` is set, provides the configuration for the
429  * command.
430  * @return `kDifBadArg` if `spi` is NULL or `slot` is larger than the number of
431  * command slots. `kDifOk` otherwise.
432  */
435  dif_spi_device_handle_t *spi, uint8_t slot, dif_toggle_t enable,
436  dif_spi_device_flash_command_t command_info);
437 
438 /**
439  * Get the current configuration of the indicated command info slot.
440  *
441  * @param spi A handle to a spi device.
442  * @param slot A command info slot ID.
443  * @param[out] enabled A pointer to where the current slot state can be stored.
444  * @param[out] command_info If `enabled`, points to where the current command
445  * configuration can be stored.
446  * @return `kDifBadArg` if any pointers are NULL or `slot` is larger than the
447  * number of command slots. `kDifOk` otherwise.
448  */
451  dif_spi_device_handle_t *spi, uint8_t slot, dif_toggle_t *enabled,
452  dif_spi_device_flash_command_t *command_info);
453 
454 /**
455  * Configure the command properties of the hardware's EN4B function.
456  *
457  * EN4B is the command to activate 4-byte addressing for flash and passthrough
458  * modes.
459  *
460  * @param spi A handle to a spi_device.
461  * @param enable Whether to enable the function.
462  * @param opcode Which opcode activates the function.
463  * @return The result of the operation.
464  */
467  dif_spi_device_handle_t *spi, dif_toggle_t enable, uint8_t opcode);
468 
469 /**
470  * Configure the command properties of the hardware's EX4B function.
471  *
472  * EX4B is the command to deactivate 4-byte addressing for flash and passthrough
473  * modes. This would return the device to the 3-byte address mode.
474  *
475  * @param spi A handle to a spi_device.
476  * @param enable Whether to enable the function.
477  * @param opcode Which opcode activates the function.
478  * @return The result of the operation.
479  */
482  dif_spi_device_handle_t *spi, dif_toggle_t enable, uint8_t opcode);
483 
484 /**
485  * Configure the command properties of the hardware's WREN function.
486  *
487  * WREN is the command to enable writes and set the WEL bit of the status
488  * register, for flash and passthroug modes.
489  *
490  * @param spi A handle to a spi_device.
491  * @param enable Whether to enable the function.
492  * @param opcode Which opcode activates the function.
493  * @return The result of the operation.
494  */
497  dif_spi_device_handle_t *spi, dif_toggle_t enable, uint8_t opcode);
498 
499 /**
500  * Configure the command properties of the hardware's WRDI function.
501  *
502  * WRDI is the command to disable writes and clear the WEL bit of the status
503  * register, for flash and passthrough modes.
504  *
505  * @param spi A handle to a spi_device.
506  * @param enable Whether to enable the function.
507  * @param opcode Which opcode activates the function.
508  * @return The result of the operation.
509  */
512  dif_spi_device_handle_t *spi, dif_toggle_t enable, uint8_t opcode);
513 
514 /**
515  * Set which address bits are swapped and their values for commands that have
516  * the address swap enabled.
517  *
518  * @param spi A handle to a spi device.
519  * @param mask A bitmask indicating which address bits should be replaced.
520  * @param replacement The values to swap in for the masked address bits.
521  * @return `kDifBadArg` if spi is NULL, else `kDifOk`.
522  */
525  uint32_t mask,
526  uint32_t replacement);
527 
528 /**
529  * Set which bits are swapped and their values for commands that have
530  * the first-word payload swap function enabled.
531  *
532  * @param spi A handle to a spi device.
533  * @param mask A bitmask indicating which bits should be replaced.
534  * @param replacement The values to swap in for the masked bits.
535  * @return `kDifBadArg` if spi is NULL, else `kDifOk`.
536  */
539  uint32_t mask,
540  uint32_t replacement);
541 
542 /**
543  * Get the current occupancy level of the command FIFO. Used in flash and
544  * passthrough modes.
545  *
546  * @param spi A SPI handle.
547  * @param[out] occupancy The number of command entries present in the command
548  * FIFO.
549  * @return The result of the operation.
550  */
553  dif_spi_device_handle_t *spi, uint8_t *occupancy);
554 
555 /**
556  * Get the current occupancy level of the address FIFO. Used in flash and
557  * passthrough modes.
558  *
559  * @param spi A SPI handle.
560  * @param[out] occupancy The number of address entries present in the command
561  * FIFO.
562  * @return The result of the operation.
563  */
566  dif_spi_device_handle_t *spi, uint8_t *occupancy);
567 
568 /**
569  * Get the current occupancy level of the payload FIFO. Used in flash and
570  * passthrough modes.
571  *
572  * Also get the starting offset for the data that was captured. Only up to 256
573  * bytes of payload may be captured by the SPI device, and if the SPI host sends
574  * more data, the SPI device wraps around to the beginning of the payload buffer
575  * and writes the newest data from there. The starting offset points to the
576  * oldest item in the payload buffer.
577  *
578  * @param spi A SPI handle.
579  * @param[out] occupancy The number of bytes present in the command FIFO.
580  * @param[out] start_offset The starting offset in the payload buffer for the
581  * data, which may wrap around to the beginning.
582  * @return The result of the operation.
583  */
586  dif_spi_device_handle_t *spi, uint16_t *occupancy, uint32_t *start_offset);
587 
588 /**
589  * Pop the first command from the uploaded command FIFO.
590  *
591  * @param spi A handle to a spi device.
592  * @param[out] command A pointer to where the command can be stored.
593  * @return `kDifBadArg` if any pointers are NULL. `kDifUnavailable` if the FIFO
594  * was empty. `kDifOk` otherwise.
595  */
598  uint8_t *command);
599 
600 /**
601  * Pop the first address from the uploaded address FIFO.
602  *
603  * @param spi A handle to a spi device.
604  * @param[out] address A pointer to where the address can be stored.
605  * @return `kDifBadArg` if any pointers are NULL. `kDifUnavailable` if the FIFO
606  * was empty. `kDifOk` otherwise.
607  */
610  uint32_t *address);
611 
612 /**
613  * Read data from the payload buffer associated with flash / passthrough modes.
614  *
615  * @param spi A handle to a spi device.
616  * @param offset The starting offset for read data in the memory.
617  * @param length The length, in bytes, of the data to be copied.
618  * @param[out] buf A pointer to the location where the data should be stored.
619  * @return `kDifBadArg` is any pointers are NULL or the `buffer_type` does not
620  * exist. `kDifOutOfRange` if the requested `offset` and `length` go beyond the
621  * payload buffer region. `kDifOk` otherwise.
622  */
625  dif_spi_device_handle_t *spi, uint32_t offset, size_t length, uint8_t *buf);
626 
627 /**
628  * Write data to one of the memories associated with flash / passthrough modes.
629  *
630  * @param spi A handle to a spi device.
631  * @param buffer_type An identifier for which memory space to write to.
632  * @param offset The starting offset for the write location of the data.
633  * @param length The length, in bytes, of the data to be copied.
634  * @param buf A pointer to the location where the data can be copied from.
635  * @return `kDifBadArg` is any pointers are NULL or the `buffer_type` does not
636  * exist. `kDifOutOfRange` if the requested `offset` and `length` go beyond the
637  * indicated `buffer_type` region. `kDifOk` otherwise.
638  */
642  dif_spi_device_flash_buffer_type_t buffer_type, uint32_t offset,
643  size_t length, const uint8_t *buf);
644 
645 /**
646  * Get whether the indicated command is filtered for passthrough.
647  *
648  * @param spi A handle to a spi device.
649  * @param command The command to be queried.
650  * @param[out] enabled A pointer to a location where the filter status can be
651  * stored. `kDifEnabled` means the command is filtered.
652  * @return `kDifBadArg` if any pointers are NULL. `kDifOk` otherwise.
653  */
656  dif_spi_device_handle_t *spi, uint8_t command, dif_toggle_t *enabled);
657 
658 /**
659  * Set whether the indicated command is filtered for passthrough.
660  *
661  * @param spi A handle to a spi device.
662  * @param command The command to have its filter status updated.
663  * @param enable Whether to enable the command filter for the `command`.
664  * @return `kDifBadArg` if `spi` is NULL or `enable` is invalid. `kDifOk`
665  * otherwise.
666  */
669  dif_spi_device_handle_t *spi, uint8_t command, dif_toggle_t enable);
670 
671 /**
672  * Set whether ALL commands are filtered for passthrough.
673  *
674  * Can be used for a faster initial state before using
675  * `dif_spi_device_set_passthrough_command_filter` to set the filter status for
676  * individual commands.
677  *
678  * @param spi A handle to a spi device.
679  * @param enable Whether to enable the command filter for all commands.
680  * @return `kDifBadArg` if `spi` is NULL or `enable` is invalid. `kDifOk`
681  * otherwise.
682  */
686 
687 /**
688  * Clear the busy bit and write-enable bit for flash / passthrough modes.
689  *
690  * @param spi A handle to a spi device.
691  * @return `kDifBadArg` if `spi` is NULL. `kDifOk` otherwise.
692  */
695 
696 /**
697  * Write the status registers for flash / passthrough modes.
698  *
699  * Note that the three registers are concatenated to make one 24-bit value, with
700  * the LSB being the busy bit.
701  *
702  * @param spi A handle to a spi device.
703  * @param value The value to write to the registers.
704  * @return `kDifBadArg` if `spi` is NULL. `kDifOk` otherwise.
705  */
708  dif_spi_device_handle_t *spi, uint32_t value);
709 
710 /**
711  * Get the values of the status registers for flash / passthrough modes.
712  *
713  * Note that the three registers are concatenated to make one 24-bit value, with
714  * the LSB being the busy bit.
715  *
716  * @param spi A handle to a spi device.
717  * @param[out] value A pointer to where to write the values of the registesr.
718  * @return `kDifBadArg` if any pointer arguments are NULL. `kDifOk` otherwise.
719  */
722  dif_spi_device_handle_t *spi, uint32_t *value);
723 
724 typedef struct dif_spi_device_tpm_caps {
725  /** Hardware revision of the TPM submodule. */
726  uint8_t revision;
727  /**
728  * True if the TPM supports 5 Locality. Otherwise, only 1 Locality is
729  * supported.
730  */
732  /**
733  * The maximum write size, in bytes, of the data phase of TPM
734  * transactions. This represents the maximum amount of data the FIFO can
735  * accept.
736  */
737  uint8_t max_write_size;
738  /**
739  * The maximum read size, in bytes, of the data phase of TPM
740  * transactions. This represents the maximum amount of data the FIFO can
741  * accept.
742  */
743  uint8_t max_read_size;
745 
746 /**
747  * Read the capabilities of the TPM hardware IP.
748  *
749  * @param spi A handle to a spi device.
750  * @param[out] caps The TPM's hardware capabilities.
751  * @return The result of the operation.
752  */
756 
758  /** Specifies the FIFO interface from the TPM specification. */
760  /** Specifies the CRB interface from the TPM specification. */
762  kDifSpiDeviceTpmInterfaceCount,
763 } dif_spi_device_tpm_interface_t;
764 
766  /**
767  * The register interface to implement for the TPM. Note that in CRB mode, the
768  * return-by-hardware logic is disabled.
769  */
770  dif_spi_device_tpm_interface_t interface;
771  /**
772  * Upload the commands that would ordinarily be targeted towards registers
773  * that automatically return by hardware. This includes TPM_DID_VID_x,
774  * TPM_RID_x, TPM_STS_x, and TPM_ACCESS_x.
775  */
777  /**
778  * Disable address prefix check that matches the pattern 0xD4_XXXX before
779  * using the return-by-hardware logic. When true, the upper 8 bits of the
780  * address are not required to be 0xD4 for the return-by-hardware logic to
781  * activate. When false, commands with non-matching addresses will be
782  * uploaded.
783  */
785  /**
786  * Disable locality value check to be within the max value before using the
787  * return-by-hardware logic. When true, the TPM will return 0xFF-valued data
788  * on reads and discard writes to registers in the TPM region (matching the
789  * 0xD4_XXXX address pattern) if the locality value is above the maximum. When
790  * false, commands with invalid locality will be uploaded, and software would
791  * be responsible for returning 0xFF to read requests.
792  */
795 
796 /**
797  * Configure the TPM within a SPI device.
798  *
799  * The TPM circuit has a separate chip-select input but shares the clock and
800  * data pins of the rest of the spi_device. The TPM can be enabled alongside
801  * the other data path (for generic/flash/passthrough modes).
802  *
803  * @param spi A handle to a spi device.
804  * @param enable Whether to enable the TPM block.
805  * @param config The TPM configuration.
806  * @return The result of the operation.
807  */
810  dif_toggle_t enable,
812 
814  /** True if a command and address have been captured and are can be read. */
816  /** True if the write FIFO is under software's exclusive use. */
818  /** True if the last command targeted the Read FIFO and was aborted. */
821 
822 /**
823  * Get the current status of the TPM's data FIFOs and command / address
824  * register.
825  *
826  * @param spi A handle to a spi device.
827  * @param[out] status The status of the TPM.
828  * @return The result of the operation.
829  */
833 
834 /**
835  * Set the value for the TPM_ACCESS_x register, for use when the
836  * return-by-hardware mode is active for this register type.
837  *
838  * @param spi A handle to a spi device.
839  * @param locality Which TPM_ACCESS_x register to target, indexed by the
840  * locality.
841  * @param value The value to set the TPM_ACCESS_x register to.
842  * @return The result of the operation.
843  */
846  uint8_t locality, uint8_t value);
847 
848 /**
849  * Get the value of the TPM_ACCESS_x register that is used when the
850  * return-by-hardware mode is active for this register type.
851  *
852  * @param spi A handle to a spi device.
853  * @param locality Which TPM_ACCESS_x register to query, indexed by the
854  * locality.
855  * @param[out] value The value of the TPM_ACCESS_x register.
856  * @return The result of the operation.
857  */
860  uint8_t locality,
861  uint8_t *value);
862 
863 /**
864  * Set the value for the TPM_STS register, for use when the
865  * return-by-hardware mode is active for this register type.
866  *
867  * @param spi A handle to a spi device.
868  * @param value The value to set the TPM_STS register to.
869  * @return The result of the operation.
870  */
873  uint32_t value);
874 
875 /**
876  * Get the value of the TPM_STS register that is used when the
877  * return-by-hardware mode is active for this register type.
878  *
879  * @param spi A handle to a spi device.
880  * @param[out] value The value of the TPM_STS register.
881  * @return The result of the operation.
882  */
885  uint32_t *value);
886 
887 /**
888  * Set the value for the TPM_INTF_CAPABILITY register, for use when the
889  * return-by-hardware mode is active for this register type.
890  *
891  * @param spi A handle to a spi device.
892  * @param value The value to set the TPM_INTF_CAPABILITY register to.
893  * @return The result of the operation.
894  */
897  dif_spi_device_handle_t *spi, uint32_t value);
898 
899 /**
900  * Get the value of the TPM_INTF_CAPABILITY register that is used when the
901  * return-by-hardware mode is active for this register type.
902  *
903  * @param spi A handle to a spi device.
904  * @param[out] value The value of the TPM_INTF_CAPABILITY register.
905  * @return The result of the operation.
906  */
909  dif_spi_device_handle_t *spi, uint32_t *value);
910 
911 /**
912  * Set the value for the TPM_INT_ENABLE register, for use when the
913  * return-by-hardware mode is active for this register type.
914  *
915  * @param spi A handle to a spi device.
916  * @param value The value to set the TPM_INT_ENABLE register to.
917  * @return The result of the operation.
918  */
921  uint32_t value);
922 
923 /**
924  * Get the value of the TPM_INT_ENABLE register that is used when the
925  * return-by-hardware mode is active for this register type.
926  *
927  * @param spi A handle to a spi device.
928  * @param[out] value The value of the TPM_INT_ENABLE register.
929  * @return The result of the operation.
930  */
933  uint32_t *value);
934 
935 /**
936  * Set the value for the TPM_INT_VECTOR register, for use when the
937  * return-by-hardware mode is active for this register type.
938  *
939  * @param spi A handle to a spi device.
940  * @param value The value to set the TPM_INT_VECTOR register to.
941  * @return The result of the operation.
942  */
945  uint32_t value);
946 
947 /**
948  * Get the value of the TPM_INT_VECTOR register that is used when the
949  * return-by-hardware mode is active for this register type.
950  *
951  * @param spi A handle to a spi device.
952  * @param[out] value The value of the TPM_INT_VECTOR register.
953  * @return The result of the operation.
954  */
957  uint32_t *value);
958 
959 /**
960  * Set the value for the TPM_INT_STATUS register, for use when the
961  * return-by-hardware mode is active for this register type.
962  *
963  * @param spi A handle to a spi device.
964  * @param value The value to set the TPM_INT_STATUS register to.
965  * @return The result of the operation.
966  */
969  uint32_t value);
970 
971 /**
972  * Get the value of the TPM_INT_STATUS register that is used when the
973  * return-by-hardware mode is active for this register type.
974  *
975  * @param spi A handle to a spi device.
976  * @param value[out] The value of the TPM_INT_STATUS register.
977  * @return The result of the operation.
978  */
981  uint32_t *value);
982 
983 typedef struct dif_spi_device_tpm_id {
984  /** The vendor ID found in the TPM_DID_VID register. */
985  uint16_t vendor_id;
986  /** The device ID found in the TPM_DID_VID register. */
987  uint16_t device_id;
988  /** The revision ID found in the TPM_RID register. */
989  uint8_t revision;
991 
992 /**
993  * Set the values for the TPM_DID_VID and TPM_RID registers, for use when the
994  * return-by-hardware mode is active for this register type.
995  *
996  * @param spi A handle to a spi device.
997  * @param id The values to set the registers to.
998  * @return The result of the operation.
999  */
1003 
1004 /**
1005  * Get the values of the TPM_DID_VID and TPM_RID registers that are used when
1006  * the return-by-hardware mode is active for this register type.
1007  *
1008  * @param spi A handle to a spi device.
1009  * @param[out] value The value of the registers.
1010  * @return The result of the operation.
1011  */
1014  dif_spi_device_tpm_id_t *value);
1015 
1016 /**
1017  * Retrieve the command and address of the current command.
1018  *
1019  * @param spi A handle to a spi device.
1020  * @param[out] command The command opcode.
1021  * @param[out] address The address associated with the command.
1022  * @return The result of the operation.
1023  */
1026  uint8_t *command,
1027  uint32_t *address);
1028 
1029 /**
1030  * Write data to the TPM's ReadFIFO.
1031  *
1032  * @param spi A handle to a spi device.
1033  * @param length The length, in bytes, of the data to be copied.
1034  * @param buf A pointer to the location of the data to be copied.
1035  * @return The result of the operation.
1036  */
1039  size_t length, uint8_t *buf);
1040 
1041 /**
1042  * Read data from the TPM's WriteFIFO.
1043  *
1044  * @param spi A handle to a spi device.
1045  * @param length The length, in bytes, of the data to be copied.
1046  * @param[out] buf A pointer to the location where the data should be stored.
1047  * @return The result of the operation.
1048  */
1051  size_t length, uint8_t *buf);
1052 
1053 /**
1054  * Release the TPM's WriteFIFO back to hardware.
1055  *
1056  * @param spi A handle to a spi device.
1057  * @return The result of the operation.
1058  */
1061 
1062 #ifdef __cplusplus
1063 } // extern "C"
1064 #endif // __cplusplus
1065 
1066 #endif // OPENTITAN_SW_DEVICE_LIB_DIF_DIF_SPI_DEVICE_H_