66 if (sensor_ctrl == NULL) {
73 alert_idx = SENSOR_CTRL_ALERT_TEST_RECOV_ALERT_BIT;
76 alert_idx = SENSOR_CTRL_ALERT_TEST_FATAL_ALERT_BIT;
82 uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx,
true);
84 alert_test_reg = bitfield_bit32_write(
85 alert_test_reg, SENSOR_CTRL_ALERT_TEST_REGWEN_BIT,
true);
88 (ptrdiff_t)SENSOR_CTRL_ALERT_TEST_REG_OFFSET,
178 dif_sensor_ctrl_irq_t irq,
181 if (sensor_ctrl == NULL || is_pending == NULL) {
186 if (!sensor_ctrl_get_irq_bit_index(irq, &index)) {
190 uint32_t intr_state_reg = mmio_region_read32(
192 (ptrdiff_t)SENSOR_CTRL_INTR_STATE_REG_OFFSET);
195 *is_pending = bitfield_bit32_read(intr_state_reg, index);
222 dif_sensor_ctrl_irq_t irq) {
224 if (sensor_ctrl == NULL) {
229 if (!sensor_ctrl_get_irq_bit_index(irq, &index)) {
234 uint32_t intr_state_reg = bitfield_bit32_write(0, index,
true);
237 (ptrdiff_t)SENSOR_CTRL_INTR_STATE_REG_OFFSET,
247 dif_sensor_ctrl_irq_t irq,
250 if (sensor_ctrl == NULL) {
255 if (!sensor_ctrl_get_irq_bit_index(irq, &index)) {
259 uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
262 (ptrdiff_t)SENSOR_CTRL_INTR_TEST_REG_OFFSET,
272 dif_sensor_ctrl_irq_t irq,
275 if (sensor_ctrl == NULL || state == NULL) {
280 if (!sensor_ctrl_get_irq_bit_index(irq, &index)) {
284 uint32_t intr_enable_reg = mmio_region_read32(
286 (ptrdiff_t)SENSOR_CTRL_INTR_ENABLE_REG_OFFSET);
289 bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
290 *state = is_enabled ?
299 dif_sensor_ctrl_irq_t irq,
302 if (sensor_ctrl == NULL) {
307 if (!sensor_ctrl_get_irq_bit_index(irq, &index)) {
311 uint32_t intr_enable_reg = mmio_region_read32(
313 (ptrdiff_t)SENSOR_CTRL_INTR_ENABLE_REG_OFFSET);
317 intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
320 (ptrdiff_t)SENSOR_CTRL_INTR_ENABLE_REG_OFFSET,