Software APIs
dif_sensor_ctrl_autogen.c
1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
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11// THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
12// util/autogen_dif.py -i
13// hw/top_earlgrey/ip/sensor_ctrl/data/sensor_ctrl.hjson -o
14// bazel-out/k8-fastbuild/bin/sw/device/lib/dif/autogen
15
16
17#include <stdint.h>
18
21
22#include "hw/top/sensor_ctrl_regs.h" // Generated.
23
24
26dif_result_t dif_sensor_ctrl_init(
27 mmio_region_t base_addr,
28 dif_sensor_ctrl_t *sensor_ctrl) {
29 if (sensor_ctrl == NULL) {
30 return kDifBadArg;
31 }
32
33 sensor_ctrl->dt = kDtSensorCtrlCount;
34 sensor_ctrl->base_addr = base_addr;
35
36 return kDifOk;
37}
38
40dif_result_t dif_sensor_ctrl_init_from_dt(
42 dif_sensor_ctrl_t *sensor_ctrl) {
43 if (sensor_ctrl == NULL) {
44 return kDifBadArg;
45 }
46
47 sensor_ctrl->dt = dt;
48 sensor_ctrl->base_addr = mmio_region_from_addr(dt_sensor_ctrl_primary_reg_block(dt));
49
50 return kDifOk;
51}
52
53dif_result_t dif_sensor_ctrl_get_dt(
54 const dif_sensor_ctrl_t *sensor_ctrl,
55 dt_sensor_ctrl_t *dt) {
56 if ((int)sensor_ctrl->dt == kDtSensorCtrlCount || dt == NULL) {
57 return kDifBadArg;
58 }
59 *dt = sensor_ctrl->dt;
60 return kDifOk;
61}
62
63 dif_result_t dif_sensor_ctrl_alert_force(
64 const dif_sensor_ctrl_t *sensor_ctrl,
66 if (sensor_ctrl == NULL) {
67 return kDifBadArg;
68 }
69
70 bitfield_bit32_index_t alert_idx;
71 switch (alert) {
73 alert_idx = SENSOR_CTRL_ALERT_TEST_RECOV_ALERT_BIT;
74 break;
76 alert_idx = SENSOR_CTRL_ALERT_TEST_FATAL_ALERT_BIT;
77 break;
78 default:
79 return kDifBadArg;
80 }
81
82 uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx, true);
83 // Keep the alert test enabled: writing 0 to the regwen bit locks the register.
84 alert_test_reg = bitfield_bit32_write(
85 alert_test_reg, SENSOR_CTRL_ALERT_TEST_REGWEN_BIT, true);
86 mmio_region_write32(
87 sensor_ctrl->base_addr,
88 (ptrdiff_t)SENSOR_CTRL_ALERT_TEST_REG_OFFSET,
89 alert_test_reg);
90
91
92 return kDifOk;
93}
94
95
96 /**
97 * Get the corresponding interrupt register bit offset of the IRQ.
98 */
99 static bool sensor_ctrl_get_irq_bit_index(
100 dif_sensor_ctrl_irq_t irq,
101 bitfield_bit32_index_t *index_out) {
102
103 switch (irq) {
105 *index_out = SENSOR_CTRL_INTR_COMMON_IO_STATUS_CHANGE_BIT;
106 break;
108 *index_out = SENSOR_CTRL_INTR_COMMON_INIT_STATUS_CHANGE_BIT;
109 break;
110 default:
111 return false;
112 }
113
114 return true;
115 }
116
117 static dif_irq_type_t irq_types[] = {
120 };
121
123 dif_result_t dif_sensor_ctrl_irq_get_type(
124 const dif_sensor_ctrl_t *sensor_ctrl,
125 dif_sensor_ctrl_irq_t irq,
126 dif_irq_type_t *type) {
127
128
129 if (sensor_ctrl == NULL ||
130 type == NULL ||
133 return kDifBadArg;
134 }
135
136 *type = irq_types[irq];
137
138 return kDifOk;
139 }
140
142 dif_result_t dif_sensor_ctrl_irq_get_state(
143 const dif_sensor_ctrl_t *sensor_ctrl,
145
146 if (sensor_ctrl == NULL || snapshot == NULL) {
147 return kDifBadArg;
148 }
149
150 *snapshot = mmio_region_read32(
151 sensor_ctrl->base_addr,
152 (ptrdiff_t)SENSOR_CTRL_INTR_STATE_REG_OFFSET);
153
154
155 return kDifOk;
156 }
157
159 dif_result_t dif_sensor_ctrl_irq_acknowledge_state(
160 const dif_sensor_ctrl_t *sensor_ctrl,
162 if (sensor_ctrl == NULL) {
163 return kDifBadArg;
164 }
165
166 mmio_region_write32(
167 sensor_ctrl->base_addr,
168 (ptrdiff_t)SENSOR_CTRL_INTR_STATE_REG_OFFSET,
169 snapshot);
170
171
172 return kDifOk;
173 }
174
176 dif_result_t dif_sensor_ctrl_irq_is_pending(
177 const dif_sensor_ctrl_t *sensor_ctrl,
178 dif_sensor_ctrl_irq_t irq,
179 bool *is_pending) {
180
181 if (sensor_ctrl == NULL || is_pending == NULL) {
182 return kDifBadArg;
183 }
184
186 if (!sensor_ctrl_get_irq_bit_index(irq, &index)) {
187 return kDifBadArg;
188 }
189
190 uint32_t intr_state_reg = mmio_region_read32(
191 sensor_ctrl->base_addr,
192 (ptrdiff_t)SENSOR_CTRL_INTR_STATE_REG_OFFSET);
193
194
195 *is_pending = bitfield_bit32_read(intr_state_reg, index);
196
197 return kDifOk;
198 }
199
201 dif_result_t dif_sensor_ctrl_irq_acknowledge_all(
202 const dif_sensor_ctrl_t *sensor_ctrl
203 ) {
204
205 if (sensor_ctrl == NULL) {
206 return kDifBadArg;
207 }
208
209 // Writing to the register clears the corresponding bits (Write-one clear).
210 mmio_region_write32(
211 sensor_ctrl->base_addr,
212 (ptrdiff_t)SENSOR_CTRL_INTR_STATE_REG_OFFSET,
213 UINT32_MAX);
214
215
216 return kDifOk;
217 }
218
220 dif_result_t dif_sensor_ctrl_irq_acknowledge(
221 const dif_sensor_ctrl_t *sensor_ctrl,
222 dif_sensor_ctrl_irq_t irq) {
223
224 if (sensor_ctrl == NULL) {
225 return kDifBadArg;
226 }
227
229 if (!sensor_ctrl_get_irq_bit_index(irq, &index)) {
230 return kDifBadArg;
231 }
232
233 // Writing to the register clears the corresponding bits (Write-one clear).
234 uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
235 mmio_region_write32(
236 sensor_ctrl->base_addr,
237 (ptrdiff_t)SENSOR_CTRL_INTR_STATE_REG_OFFSET,
238 intr_state_reg);
239
240
241 return kDifOk;
242 }
243
245 dif_result_t dif_sensor_ctrl_irq_force(
246 const dif_sensor_ctrl_t *sensor_ctrl,
247 dif_sensor_ctrl_irq_t irq,
248 const bool val) {
249
250 if (sensor_ctrl == NULL) {
251 return kDifBadArg;
252 }
253
255 if (!sensor_ctrl_get_irq_bit_index(irq, &index)) {
256 return kDifBadArg;
257 }
258
259 uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
260 mmio_region_write32(
261 sensor_ctrl->base_addr,
262 (ptrdiff_t)SENSOR_CTRL_INTR_TEST_REG_OFFSET,
263 intr_test_reg);
264
265
266 return kDifOk;
267 }
268
270 dif_result_t dif_sensor_ctrl_irq_get_enabled(
271 const dif_sensor_ctrl_t *sensor_ctrl,
272 dif_sensor_ctrl_irq_t irq,
273 dif_toggle_t *state) {
274
275 if (sensor_ctrl == NULL || state == NULL) {
276 return kDifBadArg;
277 }
278
280 if (!sensor_ctrl_get_irq_bit_index(irq, &index)) {
281 return kDifBadArg;
282 }
283
284 uint32_t intr_enable_reg = mmio_region_read32(
285 sensor_ctrl->base_addr,
286 (ptrdiff_t)SENSOR_CTRL_INTR_ENABLE_REG_OFFSET);
287
288
289 bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
290 *state = is_enabled ?
292
293 return kDifOk;
294 }
295
297 dif_result_t dif_sensor_ctrl_irq_set_enabled(
298 const dif_sensor_ctrl_t *sensor_ctrl,
299 dif_sensor_ctrl_irq_t irq,
300 dif_toggle_t state) {
301
302 if (sensor_ctrl == NULL) {
303 return kDifBadArg;
304 }
305
307 if (!sensor_ctrl_get_irq_bit_index(irq, &index)) {
308 return kDifBadArg;
309 }
310
311 uint32_t intr_enable_reg = mmio_region_read32(
312 sensor_ctrl->base_addr,
313 (ptrdiff_t)SENSOR_CTRL_INTR_ENABLE_REG_OFFSET);
314
315
316 bool enable_bit = (state == kDifToggleEnabled) ? true : false;
317 intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
318 mmio_region_write32(
319 sensor_ctrl->base_addr,
320 (ptrdiff_t)SENSOR_CTRL_INTR_ENABLE_REG_OFFSET,
321 intr_enable_reg);
322
323
324 return kDifOk;
325 }
326
328 dif_result_t dif_sensor_ctrl_irq_disable_all(
329 const dif_sensor_ctrl_t *sensor_ctrl,
331
332 if (sensor_ctrl == NULL) {
333 return kDifBadArg;
334 }
335
336 // Pass the current interrupt state to the caller, if requested.
337 if (snapshot != NULL) {
338 *snapshot = mmio_region_read32(
339 sensor_ctrl->base_addr,
340 (ptrdiff_t)SENSOR_CTRL_INTR_ENABLE_REG_OFFSET);
341
342 }
343
344 // Disable all interrupts.
345 mmio_region_write32(
346 sensor_ctrl->base_addr,
347 (ptrdiff_t)SENSOR_CTRL_INTR_ENABLE_REG_OFFSET,
348 0u);
349
350
351 return kDifOk;
352 }
353
355 dif_result_t dif_sensor_ctrl_irq_restore_all(
356 const dif_sensor_ctrl_t *sensor_ctrl,
358
359 if (sensor_ctrl == NULL || snapshot == NULL) {
360 return kDifBadArg;
361 }
362
363 mmio_region_write32(
364 sensor_ctrl->base_addr,
365 (ptrdiff_t)SENSOR_CTRL_INTR_ENABLE_REG_OFFSET,
366 *snapshot);
367
368
369 return kDifOk;
370 }
371