Software APIs
dif_sensor_ctrl_autogen.c
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 // THIS FILE HAS BEEN GENERATED, DO NOT EDIT MANUALLY. COMMAND:
6 // util/make_new_dif.py --mode=regen --only=autogen
7 
8 #include "sw/device/lib/dif/autogen/dif_sensor_ctrl_autogen.h"
9 
10 #include <stdint.h>
11 
12 #include "sw/device/lib/dif/dif_base.h"
13 
14 #include "sensor_ctrl_regs.h" // Generated.
15 
16 OT_WARN_UNUSED_RESULT
17 dif_result_t dif_sensor_ctrl_init(mmio_region_t base_addr,
18  dif_sensor_ctrl_t *sensor_ctrl) {
19  if (sensor_ctrl == NULL) {
20  return kDifBadArg;
21  }
22 
23  sensor_ctrl->base_addr = base_addr;
24 
25  return kDifOk;
26 }
27 
28 dif_result_t dif_sensor_ctrl_alert_force(const dif_sensor_ctrl_t *sensor_ctrl,
29  dif_sensor_ctrl_alert_t alert) {
30  if (sensor_ctrl == NULL) {
31  return kDifBadArg;
32  }
33 
34  bitfield_bit32_index_t alert_idx;
35  switch (alert) {
36  case kDifSensorCtrlAlertRecovAlert:
37  alert_idx = SENSOR_CTRL_ALERT_TEST_RECOV_ALERT_BIT;
38  break;
39  case kDifSensorCtrlAlertFatalAlert:
40  alert_idx = SENSOR_CTRL_ALERT_TEST_FATAL_ALERT_BIT;
41  break;
42  default:
43  return kDifBadArg;
44  }
45 
46  uint32_t alert_test_reg = bitfield_bit32_write(0, alert_idx, true);
47  mmio_region_write32(sensor_ctrl->base_addr,
48  (ptrdiff_t)SENSOR_CTRL_ALERT_TEST_REG_OFFSET,
49  alert_test_reg);
50 
51  return kDifOk;
52 }
53 
54 /**
55  * Get the corresponding interrupt register bit offset of the IRQ.
56  */
57 static bool sensor_ctrl_get_irq_bit_index(dif_sensor_ctrl_irq_t irq,
58  bitfield_bit32_index_t *index_out) {
59  switch (irq) {
60  case kDifSensorCtrlIrqIoStatusChange:
61  *index_out = SENSOR_CTRL_INTR_COMMON_IO_STATUS_CHANGE_BIT;
62  break;
63  case kDifSensorCtrlIrqInitStatusChange:
64  *index_out = SENSOR_CTRL_INTR_COMMON_INIT_STATUS_CHANGE_BIT;
65  break;
66  default:
67  return false;
68  }
69 
70  return true;
71 }
72 
73 static dif_irq_type_t irq_types[] = {
74  kDifIrqTypeEvent,
75  kDifIrqTypeEvent,
76 };
77 
78 OT_WARN_UNUSED_RESULT
79 dif_result_t dif_sensor_ctrl_irq_get_type(const dif_sensor_ctrl_t *sensor_ctrl,
80  dif_sensor_ctrl_irq_t irq,
81  dif_irq_type_t *type) {
82  if (sensor_ctrl == NULL || type == NULL ||
83  irq == kDifSensorCtrlIrqInitStatusChange + 1) {
84  return kDifBadArg;
85  }
86 
87  *type = irq_types[irq];
88 
89  return kDifOk;
90 }
91 
92 OT_WARN_UNUSED_RESULT
93 dif_result_t dif_sensor_ctrl_irq_get_state(
94  const dif_sensor_ctrl_t *sensor_ctrl,
95  dif_sensor_ctrl_irq_state_snapshot_t *snapshot) {
96  if (sensor_ctrl == NULL || snapshot == NULL) {
97  return kDifBadArg;
98  }
99 
100  *snapshot = mmio_region_read32(sensor_ctrl->base_addr,
101  (ptrdiff_t)SENSOR_CTRL_INTR_STATE_REG_OFFSET);
102 
103  return kDifOk;
104 }
105 
106 OT_WARN_UNUSED_RESULT
107 dif_result_t dif_sensor_ctrl_irq_acknowledge_state(
108  const dif_sensor_ctrl_t *sensor_ctrl,
109  dif_sensor_ctrl_irq_state_snapshot_t snapshot) {
110  if (sensor_ctrl == NULL) {
111  return kDifBadArg;
112  }
113 
114  mmio_region_write32(sensor_ctrl->base_addr,
115  (ptrdiff_t)SENSOR_CTRL_INTR_STATE_REG_OFFSET, snapshot);
116 
117  return kDifOk;
118 }
119 
120 OT_WARN_UNUSED_RESULT
121 dif_result_t dif_sensor_ctrl_irq_is_pending(
122  const dif_sensor_ctrl_t *sensor_ctrl, dif_sensor_ctrl_irq_t irq,
123  bool *is_pending) {
124  if (sensor_ctrl == NULL || is_pending == NULL) {
125  return kDifBadArg;
126  }
127 
128  bitfield_bit32_index_t index;
129  if (!sensor_ctrl_get_irq_bit_index(irq, &index)) {
130  return kDifBadArg;
131  }
132 
133  uint32_t intr_state_reg = mmio_region_read32(
134  sensor_ctrl->base_addr, (ptrdiff_t)SENSOR_CTRL_INTR_STATE_REG_OFFSET);
135 
136  *is_pending = bitfield_bit32_read(intr_state_reg, index);
137 
138  return kDifOk;
139 }
140 
141 OT_WARN_UNUSED_RESULT
142 dif_result_t dif_sensor_ctrl_irq_acknowledge_all(
143  const dif_sensor_ctrl_t *sensor_ctrl) {
144  if (sensor_ctrl == NULL) {
145  return kDifBadArg;
146  }
147 
148  // Writing to the register clears the corresponding bits (Write-one clear).
149  mmio_region_write32(sensor_ctrl->base_addr,
150  (ptrdiff_t)SENSOR_CTRL_INTR_STATE_REG_OFFSET, UINT32_MAX);
151 
152  return kDifOk;
153 }
154 
155 OT_WARN_UNUSED_RESULT
156 dif_result_t dif_sensor_ctrl_irq_acknowledge(
157  const dif_sensor_ctrl_t *sensor_ctrl, dif_sensor_ctrl_irq_t irq) {
158  if (sensor_ctrl == NULL) {
159  return kDifBadArg;
160  }
161 
162  bitfield_bit32_index_t index;
163  if (!sensor_ctrl_get_irq_bit_index(irq, &index)) {
164  return kDifBadArg;
165  }
166 
167  // Writing to the register clears the corresponding bits (Write-one clear).
168  uint32_t intr_state_reg = bitfield_bit32_write(0, index, true);
169  mmio_region_write32(sensor_ctrl->base_addr,
170  (ptrdiff_t)SENSOR_CTRL_INTR_STATE_REG_OFFSET,
171  intr_state_reg);
172 
173  return kDifOk;
174 }
175 
176 OT_WARN_UNUSED_RESULT
177 dif_result_t dif_sensor_ctrl_irq_force(const dif_sensor_ctrl_t *sensor_ctrl,
178  dif_sensor_ctrl_irq_t irq,
179  const bool val) {
180  if (sensor_ctrl == NULL) {
181  return kDifBadArg;
182  }
183 
184  bitfield_bit32_index_t index;
185  if (!sensor_ctrl_get_irq_bit_index(irq, &index)) {
186  return kDifBadArg;
187  }
188 
189  uint32_t intr_test_reg = bitfield_bit32_write(0, index, val);
190  mmio_region_write32(sensor_ctrl->base_addr,
191  (ptrdiff_t)SENSOR_CTRL_INTR_TEST_REG_OFFSET,
192  intr_test_reg);
193 
194  return kDifOk;
195 }
196 
197 OT_WARN_UNUSED_RESULT
198 dif_result_t dif_sensor_ctrl_irq_get_enabled(
199  const dif_sensor_ctrl_t *sensor_ctrl, dif_sensor_ctrl_irq_t irq,
200  dif_toggle_t *state) {
201  if (sensor_ctrl == NULL || state == NULL) {
202  return kDifBadArg;
203  }
204 
205  bitfield_bit32_index_t index;
206  if (!sensor_ctrl_get_irq_bit_index(irq, &index)) {
207  return kDifBadArg;
208  }
209 
210  uint32_t intr_enable_reg = mmio_region_read32(
211  sensor_ctrl->base_addr, (ptrdiff_t)SENSOR_CTRL_INTR_ENABLE_REG_OFFSET);
212 
213  bool is_enabled = bitfield_bit32_read(intr_enable_reg, index);
214  *state = is_enabled ? kDifToggleEnabled : kDifToggleDisabled;
215 
216  return kDifOk;
217 }
218 
219 OT_WARN_UNUSED_RESULT
220 dif_result_t dif_sensor_ctrl_irq_set_enabled(
221  const dif_sensor_ctrl_t *sensor_ctrl, dif_sensor_ctrl_irq_t irq,
222  dif_toggle_t state) {
223  if (sensor_ctrl == NULL) {
224  return kDifBadArg;
225  }
226 
227  bitfield_bit32_index_t index;
228  if (!sensor_ctrl_get_irq_bit_index(irq, &index)) {
229  return kDifBadArg;
230  }
231 
232  uint32_t intr_enable_reg = mmio_region_read32(
233  sensor_ctrl->base_addr, (ptrdiff_t)SENSOR_CTRL_INTR_ENABLE_REG_OFFSET);
234 
235  bool enable_bit = (state == kDifToggleEnabled) ? true : false;
236  intr_enable_reg = bitfield_bit32_write(intr_enable_reg, index, enable_bit);
237  mmio_region_write32(sensor_ctrl->base_addr,
238  (ptrdiff_t)SENSOR_CTRL_INTR_ENABLE_REG_OFFSET,
239  intr_enable_reg);
240 
241  return kDifOk;
242 }
243 
244 OT_WARN_UNUSED_RESULT
245 dif_result_t dif_sensor_ctrl_irq_disable_all(
246  const dif_sensor_ctrl_t *sensor_ctrl,
247  dif_sensor_ctrl_irq_enable_snapshot_t *snapshot) {
248  if (sensor_ctrl == NULL) {
249  return kDifBadArg;
250  }
251 
252  // Pass the current interrupt state to the caller, if requested.
253  if (snapshot != NULL) {
254  *snapshot = mmio_region_read32(
255  sensor_ctrl->base_addr, (ptrdiff_t)SENSOR_CTRL_INTR_ENABLE_REG_OFFSET);
256  }
257 
258  // Disable all interrupts.
259  mmio_region_write32(sensor_ctrl->base_addr,
260  (ptrdiff_t)SENSOR_CTRL_INTR_ENABLE_REG_OFFSET, 0u);
261 
262  return kDifOk;
263 }
264 
265 OT_WARN_UNUSED_RESULT
266 dif_result_t dif_sensor_ctrl_irq_restore_all(
267  const dif_sensor_ctrl_t *sensor_ctrl,
268  const dif_sensor_ctrl_irq_enable_snapshot_t *snapshot) {
269  if (sensor_ctrl == NULL || snapshot == NULL) {
270  return kDifBadArg;
271  }
272 
273  mmio_region_write32(sensor_ctrl->base_addr,
274  (ptrdiff_t)SENSOR_CTRL_INTR_ENABLE_REG_OFFSET, *snapshot);
275 
276  return kDifOk;
277 }
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