Software APIs
dif_rram_ctrl.h
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1// Copyright lowRISC contributors (OpenTitan project).
2// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3// SPDX-License-Identifier: Apache-2.0
4
5#ifndef OPENTITAN_SW_DEVICE_LIB_DIF_DIF_RRAM_CTRL_H_
6#define OPENTITAN_SW_DEVICE_LIB_DIF_DIF_RRAM_CTRL_H_
7
8/**
9 * @file
10 * @brief <a href="/book/hw/ip/rram_ctrl/doc/">RRAM
11 * Controller</a> Device Interface Functions
12 */
13
14#include <stdbool.h>
15#include <stdint.h>
16
19#include "sw/device/lib/base/multibits.h"
21
23
24#ifdef __cplusplus
25extern "C" {
26#endif // __cplusplus
27
28/**
29 * Carries transaction state for a RRAM controller device.
30 *
31 * All members except `dev` should be considered private and should not be
32 * accessed directly outside of the DIF implementation.
33 */
34typedef struct dif_rram_ctrl_state {
35 /**
36 * Contains autogenerated device information, like the base address for
37 * registers in the RRAM controller device.
38 */
40
41 /** Number of words remaining for the current transaction. */
43 /** Whether a transaction is pending completion. */
46
47/**
48 * Initialize the DIF state for the RRAM controller.
49 *
50 * @param handle The RRAM controller DIF state to initialize.
51 * @param base_addr The base address for the RRAM controller.
52 * @return `kDifBadArg` if `handle` is null. `kDifOk` otherwise.
53 */
56 mmio_region_t base_addr);
57
58/**
59 * Initialize the DIF state for the RRAM controller from a device tree handle.
60 *
61 * @param handle The RRAM controller DIF state to initialize.
62 * @param dt The RRAM controller device tree handle.
63 * @return `kDifBadArg` if `handle` is null. `kDifOk` otherwise.
64 */
68
70 /** Number of bytes per RRAM word. */
72 /** Number of bytes per RRAM page. */
74 /** Number of pages in the data partition. */
75 uint32_t data_pages;
76 /** Number of pages in the info partition. */
77 uint32_t info_pages;
78} dif_rram_ctrl_device_info_t;
79
80/**
81 * Get information on the RRAM controller sizes.
82 *
83 * @return A `dif_rram_ctrl_device_info_t` representing the feature sizes for
84 * various components of the RRAM.
85 */
87dif_rram_ctrl_device_info_t dif_rram_ctrl_get_device_info(void);
88
89/**
90 * Set whether the RRAM is enabled.
91 *
92 * Generally, this is used to disable RRAM functionality in case of an
93 * emergency. RRAM functionality is ordinarily enabled.
94 *
95 * @param handle The RRAM controller DIF state.
96 * @param enable Enable/disable RRAM functionality.
97 * @return `kDifBadArg` if `handle` is null. `kDifOk` on success.
98 */
101 dif_toggle_t enable);
102
103/**
104 * Get whether RRAM functionality is enabled.
105 *
106 * @param handle The RRAM controller DIF state.
107 * @param[out] enabled_out Out parameter, where to store whether RRAM is
108 * enabled.
109 * @return `kDifBadArg` if `handle` or `enabled_out` is null. `kDifOk`
110 * otherwise.
111 */
114 const dif_rram_ctrl_state_t *handle, dif_toggle_t *enabled_out);
115
116/**
117 * Set whether execution / fetch access is enabled.
118 *
119 * @param handle The RRAM controller DIF state.
120 * @param enable Enable/disable execution / fetch access.
121 * @return `kDifBadArg` if `handle` is null. `kDifOk` otherwise.
122 */
125 dif_toggle_t enable);
126
127/**
128 * Get whether execution / fetch access is enabled.
129 *
130 * @param handle The RRAM controller DIF state.
131 * @param[out] enabled_out Out parameter, whether execution / fetch access is
132 * allowed.
133 * @return `kDifBadArg` if `handle` or `enabled_out` is null. `kDifOk`
134 * otherwise.
135 */
138 const dif_rram_ctrl_state_t *handle, dif_toggle_t *enabled_out);
139
140/**
141 * Begins the RRAM controller's initialization sequence. The RRAM controller
142 * will read out the root seeds before allowing other usage of the controller.
143 * This operation will only be performed once, and controller initialization
144 * cannot be requested again until after a reset.
145 *
146 * @param handle The RRAM controller DIF state.
147 * @return `kDifError` if initialization has already been started, and
148 * `kDifOk` otherwise.
149 */
152
153/**
154 * Status bits that can be queried.
155 */
156typedef struct dif_rram_ctrl_status {
157 /**
158 * RRAM read FIFO full, software must consume data.
159 */
161 /**
162 * RRAM read FIFO empty.
163 */
165 /**
166 * RRAM write FIFO full.
167 */
169 /**
170 * RRAM write FIFO empty, software must provide data.
171 */
173 /**
174 * RRAM controller init complete.
175 */
177 /**
178 * RRAM controller keys valid.
179 */
182
183/**
184 * Query the status registers on the RRAM controller.
185 *
186 * This function checks the various status bits as described in
187 * `dif_rram_ctrl_status_t`.
188 *
189 * @param handle The RRAM controller DIF state.
190 * @param[out] status_out Out parameter. The current status of the RRAM
191 * controller.
192 * @return `kDifBadArg` if `handle` or `status_out` is null. `kDifOk`
193 * otherwise.
194 */
197 dif_rram_ctrl_status_t *status_out);
198
199/**
200 * Enum to represent the RRAM partition type (data or info).
201 */
203 kDifRramCtrlPartitionTypeData = 0,
204 kDifRramCtrlPartitionTypeInfo = 1
206
208 /** Read the specified number of words. */
210 /** Write the specified number of words. */
212 /** Rewrite a specific word to repair it. */
214} dif_rram_ctrl_operation_t;
215
217 dif_rram_ctrl_operation_t op;
218 /**
219 * The partition type for the transaction.
220 *
221 */
223 /**
224 * Byte address (in the RRAM address space) to start the operation.
225 *
226 * For operations at a granularity of words, the RRAM controller will
227 * truncate to the closest, lower word aligned address. For example, if 0x13
228 * is supplied for a read, the controller will perform a read at address 0x10.
229 *
230 * For write operations, the granularity is 4 words or 16 bytes. The RRAM
231 * controller and `dif_rram_ctrl_start_unsafe()` will truncate the address
232 * to the closest, lower aligned 16 byte address; `dif_rram_ctrl_start()`
233 * instead rejects a misaligned write address with `kDifBadArg`.
234 */
235 uint32_t byte_address;
236 /**
237 * Number of 32-bit words in the operation. Must be in the range [1,1024]
238 * (inclusive) for write or read operations.
239 * For write operations the number of 32-bit words must be a multiple of 4.
240 */
241 uint32_t word_count;
242} dif_rram_ctrl_transaction_t;
243
244/**
245 * Start a RRAM controller operation.
246 *
247 * @param handle The RRAM controller DIF state.
248 * @param transaction The parameters that constitute the operation to start.
249 * @return `kDifBadArg` if `handle` is null, if `transaction` contains an
250 * invalid or unsupported operation, if `word_count` is zero or out of range,
251 * if `word_count` is not a multiple of 4 for write operations, or if
252 * `byte_address` is not 16-byte aligned for write operations;
253 * `kDifUnavailable` if a RRAM transaction is in progress at the controller,
254 * `kDifIpFifoFull` if the FIFOs are not empty, and `kDifOk` otherwise.
255 */
258 dif_rram_ctrl_transaction_t transaction);
259
260/**
261 * Start a RRAM controller operation, with fewer safeguards. (unsafe version)
262 *
263 * Unlike `dif_rram_ctrl_start()`, this variant does not check whether the
264 * word count is valid, whether the write address is 16-byte aligned, or
265 * whether the FIFOs have been emptied. This function is intended to be used
266 * to trigger errors on purpose, for testing the hardware responses.
267 *
268 * @param handle The RRAM controller DIF state.
269 * @param transaction The parameters that constitute the operation to start.
270 * @return `kDifBadArg` if `handle` is null, `kDifUnavailable` if a RRAM
271 * transaction is in progress, and `kDifOk` otherwise.
272 */
275 dif_rram_ctrl_state_t *handle, dif_rram_ctrl_transaction_t transaction);
276
277/**
278 * Push data to the write FIFO. (unsafe version)
279 *
280 * This function is primarily for testing hardware error responses. If you are
281 * not specifically trying to force an error, consider
282 * `dif_rram_ctrl_wr_fifo_push()` instead. This function does not check if a
283 * write transaction has begun, nor if the number of words would exceed the
284 * size of the current transaction.
285 *
286 * Attempts to write the contents of `data` to the write FIFO without
287 * consideration for the current controller state.
288 *
289 * It is up to the caller to call `dif_rram_ctrl_end()` to ensure the
290 * RRAM controller completed this transaction successfully.
291 *
292 * @param handle The RRAM controller DIF state.
293 * @param word_count The number of words to write.
294 * @param data The data to write.
295 * @return `kDifBadArg` if `handle` or `data` are null. `kDifOk` otherwise.
296 */
299 uint32_t word_count,
300 const uint32_t *data);
301
302/**
303 * Push data to the write FIFO.
304 *
305 * Attempts to write the contents of `data` to the write FIFO. It is required
306 * that a write transaction be started prior to calling this function, else
307 * the call will fail with `kDifError`.
308 *
309 * The following conditions are also required:
310 * - `data` must reference a contiguous, allocated, readable region of at
311 * least `word_count` words, violation of this will produce undefined
312 * behavior.
313 * - The first call to this function after starting the write transaction
314 * the same `word_count` must not exceed what was supplied at the start of
315 * the write transaction.
316 * - Each subsequent call the new `word_count` must not exceed `word_count -
317 * words_sent_out` from the previous call.
318 * All deviations on the above will produce a `kDifBadArg` error
319 * unless otherwise specified.
320 *
321 * If the FIFO fills up, this function will cause the CPU to block until the
322 * RRAM controller frees up more space.
323 *
324 * It is up to the caller to call `dif_rram_ctrl_end()` to ensure the
325 * RRAM controller completed this transaction successfully.
326 *
327 * @param handle The RRAM controller DIF state.
328 * @param word_count The number of words to write.
329 * @param data The data to write.
330 * @return `kDifBadArg` if `handle` or `data` are null or if the value of
331 * `word_count` is illegal. `kDifError` if a write transaction was not
332 * started. `kDifOk` otherwise.
333 */
336 uint32_t word_count,
337 const uint32_t *data);
338
339/**
340 * Read data from the read FIFO. (unsafe version)
341 *
342 * This function is primarily for testing hardware error responses. If you are
343 * not specifically trying to force an error, consider
344 * `dif_rram_ctrl_read_fifo_pop()` instead. This function does not check if a
345 * transaction is currently in progress, nor if this would cause a read beyond
346 * the number of words for the current operation.
347 *
348 * Attempts to read `word_count` words from the read FIFO without consideration
349 * for the current controller state.
350 *
351 * It is up to the caller to call `dif_rram_ctrl_end()` to ensure the
352 * RRAM controller completed this transaction successfully.
353 *
354 * @param handle The RRAM controller DIF state.
355 * @param word_count The number of words to read.
356 * @param[out] data_out The region in memory to store the data read off the
357 * FIFO.
358 * @return `kDifBadArg` if `handle` or `data_out` are null. `kDifOk` otherwise.
359 */
362 uint32_t word_count,
363 uint32_t *data_out);
364
365/**
366 * Read data from the read FIFO.
367 *
368 * Attempts to read `word_count` words from the read FIFO.
369 *
370 * The following conditions are required:
371 * - `data_out` must reference a contiguous, allocated, writable region of at
372 * least `word_count` words, violation of this will produce undefined
373 * behavior.
374 * - The first call to this function after starting the write transaction
375 * the same `word_count` must not exceed what was supplied at the start of
376 * the read transaction.
377 * - Each subsequent call the new `word_count` must not exceed `word_count -
378 * words_received` from the previous call.
379 * All deviations on the above will produce a `kDifBadArg` error unless
380 * otherwise specified.
381 *
382 * If the FIFO empties this function will cause the CPU to block until the RRAM
383 * controller fills the FIFO with more data.
384 *
385 * It is up to the caller to call `dif_rram_ctrl_end()` to ensure the
386 * RRAM controller completed this transaction successfully.
387 *
388 * @param handle The RRAM controller DIF state.
389 * @param word_count The number of words to read.
390 * @param[out] data_out The region in memory to store the data read off the
391 * FIFO.
392 * @return `kDifBadArg` if `handle` or `data_out` are null, or if the value of
393 * `word_count` is illegal. `kDifOk` otherwise.
394 */
397 uint32_t word_count,
398 uint32_t *data_out);
399
401 /**
402 * Controller operation error.
403 */
405 /**
406 * Access permission error.
407 */
409 /**
410 * Uncorrectable RRAM read data error.
411 */
413 /**
414 * RRAM write error.
415 */
417} dif_rram_ctrl_error_codes_t;
418
419/**
420 * Represents recoverable errors and synchronous errors caused by software.
421 */
422typedef struct dif_rram_ctrl_error {
423 /**
424 * For errors associated with an address, the address where the error
425 * occurred.
426 */
427 uint32_t address;
428
429 /**
430 * A set of error codes.
431 */
432 dif_rram_ctrl_error_codes_t codes;
434
435/**
436 * Get the error codes and address of the last associated error.
437 *
438 * @param handle The RRAM controller DIF state.
439 * @param[out] error_code_out Output parameter. The location where the current
440 * status is to be stored.
441 * @return `kDifBadArg` if `handle` or `error_code_out` is null. `kDifOk`
442 * otherwise.
443 */
446 const dif_rram_ctrl_state_t *handle, dif_rram_ctrl_error_t *error_code_out);
447
448/**
449 * Clear the error codes.
450 *
451 * @param handle The RRAM controller DIF state.
452 * @param codes The error codes to clear.
453 * @return `kDifBadArg` if `handle` is null. `kDifOk` otherwise.
454 */
457 dif_rram_ctrl_error_codes_t codes);
458
459typedef struct dif_rram_ctrl_output {
460 /**
461 * The error code associated with an `operation_error`. This field is only
462 * valid if `operation_error` is true.
463 */
465 /**
466 * RRAM operation done.
467 */
469 /**
470 * RRAM operation error.
471 */
473
474} dif_rram_ctrl_output_t;
475
476/**
477 * Check that the transaction has completed and return any resulting error
478 * codes. Does not clear the error codes, but does clear the operation status if
479 * the operation has terminated.
480 *
481 * @param handle The RRAM controller DIF state.
482 * @param[out] out Out parameter. Contains the transaction status and error
483 * codes.
484 * @return `kDifBadArg` if `handle` or `out` are null, `kDifError` if no
485 * transaction was pending, `kDifUnavailable` if the controller is still
486 * processing the transaction, `kDifIpFifoFull` if there are still words
487 * remaining for the FIFOs, and `kDifOk` otherwise.
488 */
491 dif_rram_ctrl_output_t *out);
492
493/**
494 * Memory protection configuration options.
495 */
497 /** Read enable flag. */
498 multi_bit_bool_t rd_en;
499 /** Write enable flag. */
500 multi_bit_bool_t wr_en;
501 /** Scramble enable flag*/
502 multi_bit_bool_t scramble_en;
503 /** ECC enable flag. */
504 multi_bit_bool_t ecc_en;
506
507/**
508 * A composite of a data region and its memory properties.
509 */
511 /** Region base page index. */
512 uint32_t base;
513 /** Region config size (in number of pages). */
514 uint32_t size;
515 /** Memory properties of the region. */
518
519/**
520 * Representation of the memory protection regions for the info pages.
521 */
523 /** Region page index. */
524 uint32_t page;
526
527/**
528 * Enable/disable the data region of RRAM indexed by `region`.
529 *
530 * This may only be done if region configuration has not been locked.
531 *
532 * @param handle The RRAM controller DIF state.
533 * @param region The region to operate on.
534 * @param enable Enable or disable this `region`.
535 * @return `kDifBadArg` if `handle` is null or `region` is invalid, `kDifLocked`
536 * if region configuration has been locked, and `kDifOk` otherwise.
537 */
540 dif_rram_ctrl_state_t *handle, uint32_t region, dif_toggle_t enable);
541
542/**
543 * Get the enabled/disabled state for the indicated data `region`.
544 *
545 * @param handle The RRAM controller DIF state.
546 * @param region The region in question.
547 * @param[out] enabled_out Out-parameter, the enabled/disabled state of this
548 * region.
549 * @return `kDifBadArg` if `handle` or `enabled_out` is null, or if `region` is
550 * invalid, `kDifOk` otherwise.
551 */
554 const dif_rram_ctrl_state_t *handle, uint32_t region,
555 dif_toggle_t *enabled_out);
556
557/**
558 * Enable/disable the info region of RRAM identified by `region`.
559 *
560 * This may only be done if region configuration has not been locked.
561 *
562 * @param handle The RRAM controller DIF state.
563 * @param region The region to operate on.
564 * @param enable Enable or disable this `region`.
565 * @return `kDifBadArg` if `handle` is null or `region` is invalid, `kDifLocked`
566 * if region configuration has been locked, and `kDifOk` otherwise.
567 */
571 dif_toggle_t enable);
572
573/**
574 * Get the enabled/disabled state for the indicated info `region`.
575 *
576 * @param handle The RRAM controller DIF state.
577 * @param region The region in question.
578 * @param[out] enabled_out Out-parameter, the enabled/disabled state of this
579 * region.
580 * @return `kDifBadArg` if `handle` or `enabled_out` is null, or if `region` is
581 * invalid, `kDifOk` otherwise.
582 */
586 dif_toggle_t *enabled_out);
587
588/**
589 * Set the default memory properties for data regions, when not overridden by a
590 * specific entry in the data region memory properties table.
591 *
592 * @param handle The RRAM controller DIF state.
593 * @param properties The memory properties to control.
594 * @return `kDifBadArg` if `handle` is null. `kDifOk` otherwise.
595 */
598 dif_rram_ctrl_state_t *handle,
600
601/**
602 * Get the default memory properties for data regions, when they are not
603 * overridden by a specific entry in the data region memory properties table.
604 *
605 * @param handle The RRAM controller DIF state.
606 * @param[out] properties_out Out-parameter, a pointer to a
607 * `dif_rram_ctrl_region_properties_t` struct for writing the memory
608 * properties.
609 * @return `kDifBadArg` if `handle` or `properties_out` is null. `kDifOk`
610 * otherwise.
611 */
614 const dif_rram_ctrl_state_t *handle,
615 dif_rram_ctrl_region_properties_t *properties_out);
616
617/**
618 * Set memory properties for the data region of RRAM indexed by `region`.
619 *
620 * This may only be done if region configuration has not been locked.
621 *
622 * @param handle The RRAM controller DIF state.
623 * @param region The region to operate on.
624 * @param config The memory properties to control for this `region`.
625 * @return `kDifBadArg` if `handle` is null or `region` is invalid, `kDifLocked`
626 * if region configuration has been locked, and `kDifOk` otherwise.
627 */
630 dif_rram_ctrl_state_t *handle, uint32_t region,
632
633/**
634 * Get the memory properties for the data region of RRAM indexed by `region`.
635 *
636 * @param handle The RRAM controller DIF state.
637 * @param region The index of the region entry in question.
638 * @param[out] config_out Out-parameter, a pointer to a
639 * `dif_rram_ctrl_data_region_properties_t` struct for writing the full entry
640 * showing the region configuration and its memory properties.
641 * @return `kDifBadArg` if `handle` or `config_out` is null or if `region`
642 * is invalid. `kDifOk` otherwise.
643 */
646 const dif_rram_ctrl_state_t *handle, uint32_t region,
648
649/**
650 * Set memory properties for the info region of RRAM identified by `region`.
651 *
652 * This may only be done if region configuration has not been locked.
653 *
654 * @param handle The RRAM controller DIF state.
655 * @param region The region to operate on.
656 * @param properties The memory properties to control for this `region`.
657 * @return `kDifBadArg` if `handle` is null or `region` is invalid, `kDifLocked`
658 * if region configuration has been locked, and `kDifOk` otherwise.
659 */
664
665/**
666 * Get the memory properties for the info region of RRAM identified by
667 * `region`.
668 *
669 * @param handle The RRAM controller DIF state.
670 * @param region The index of the region entry in question.
671 * @param[out] properties_out Out-parameter, a pointer to a
672 * `dif_rram_ctrl_region_properties_t` struct for writing memory properties
673 * associated with the indicated `region`.
674 * @return `kDifBadArg` if `handle` or `properties_out` is null or if `region`
675 * is invalid. `kDifOk` otherwise.
676 */
680 dif_rram_ctrl_region_properties_t *properties_out);
681
682/**
683 * Lock data region memory properties configuration until the device is reset.
684 *
685 * This will prevent any further configuration of region properties until device
686 * reset. Future calls to functions that set data region memory properties will
687 * return `kDifLocked`.
688 *
689 * @param handle The RRAM controller DIF state.
690 * @param region The region to lock.
691 * @return `kDifBadArg` if `handle` is null or `region` is invalid,
692 * `kDifLocked` if configuration is already locked, `kDifOk` otherwise.
693 */
696 dif_rram_ctrl_state_t *handle, uint32_t region);
697
698/**
699 * Lock info region memory properties configuration until the device is reset.
700 *
701 * This will prevent any further configuration of region properties until device
702 * reset. Future calls to functions that set info region memory properties will
703 * return `kDifLocked`.
704 *
705 * @param handle The RRAM controller DIF state.
706 * @param region The region to lock.
707 * @return `kDifBadArg` if `handle` is null or `region` is invalid,
708 * `kDifLocked` if configuration is already locked, `kDifOk` otherwise.
709 */
713
714/**
715 * Query the state of the region configuration lock for the given data `region`
716 * entry's index.
717 *
718 * This function checks if memory region configuration is still enabled or if it
719 * has been locked. Once locked, region configuration cannot be enabled again,
720 * and all calls to region configuration functions will return `kDifLocked`
721 * until the device is restarted.
722 *
723 * @param handle The RRAM controller DIF state.
724 * @param region The region in question.
725 * @param[out] locked_out Out-parameter, the current state of the region's
726 * configuration lock.
727 * @return `kDifBadArg` if `handle` or `locked_out` is null, or if `region` is
728 * invalid, `kDifOk` otherwise.
729 */
732 const dif_rram_ctrl_state_t *handle, uint32_t region, bool *locked_out);
733
734/**
735 * Query the state of the region configuration lock for the given info `region`.
736 *
737 * This function checks if memory region configuration is still enabled or if it
738 * has been locked. Once locked, region configuration cannot be enabled again,
739 * and all calls to region configuration functions will return `kDifLocked`
740 * until the device is restarted.
741 *
742 * @param handle The RRAM controller DIF state.
743 * @param region The region in question.
744 * @param[out] locked_out Out-parameter, the current state of the region's
745 * configuration lock.
746 * @return `kDifBadArg` if `handle` or `locked_out` is null, or if `region` is
747 * invalid, `kDifOk` otherwise.
748 */
752 bool *locked_out);
753
754/**
755 * Set the interrupt watermarks for the write FIFO.
756 *
757 * The value of `level` defines the level the write FIFO must drain to before
758 * triggering a `wr_lvl` interrupt.
759 *
760 * This interrupts will only trigger if enabled through the interrupt API.
761 *
762 * @param handle The RRAM controller DIF state.
763 * @param level Trigger an interrupt when the write FIFO drains to this level.
764 * @return `kDifBadArg` if `handle` is null or the value `level` is out of
765 * range, `kDifOk` otherwise.
766 */
769 uint32_t level);
770
771/**
772 * Set the interrupt watermarks for the read FIFO.
773 *
774 * The value of `level` defines the level the read FIFO must fill to before
775 * triggering a `rd_lvl` interrupt.
776 *
777 * This interrupt will only trigger if enabled through the interrupt API.
778 *
779 * @param handle The RRAM controller DIF state.
780 * @param level Trigger an interrupt when the read FIFO fills to this level.
781 * @return `kDifBadArg` if `handle` is null or the value of `level` is out of
782 * range, `kDifOk` otherwise.
783 */
786 dif_rram_ctrl_state_t *handle, uint32_t level);
787
788/**
789 * Get the interrupt watermarks for the write and read FIFOs.
790 *
791 * @param handle The RRAM controller DIF state.
792 * @param[out] write_out Out-parameter, the write FIFO watermark level. If the
793 * write FIFO empties to this level, a corresponding status bit and possibly
794 * an interrupt may be generated. May be null.
795 * @param[out] read_out Out-parameter, the read FIFO watermark level. If the
796 * read FIFO fills to this level, a corresponding status bit and possibly an
797 * interrupt may be generated. May be null.
798 * @return `kDifBadArg` if `handle` is null. `kDifOk` otherwise.
799 */
802 const dif_rram_ctrl_state_t *handle, uint32_t *write_out,
803 uint32_t *read_out);
804
805/**
806 * Clears the write FIFO.
807 *
808 * This is useful in the event of an unexpected error as a means of reseting
809 * state.
810 *
811 * Note that this does not reset the handle's internal `words_remaining` or
812 * `transaction_pending` tracking. After an aborted transaction, the handle
813 * must be reinitialized with `dif_rram_ctrl_init_state()` (which has no MMIO
814 * side effects) before starting a new one; otherwise `dif_rram_ctrl_start()`
815 * returns `kDifUnavailable` and `dif_rram_ctrl_end()` returns
816 * `kDifIpFifoFull`. See #30909 for adding a proper way to abort an ongoing
817 * transaction.
818 *
819 * @param handle The RRAM controller DIF state.
820 * @return `kDifBadArg` if `handle` is null. `kDifOk` otherwise.
821 */
824
825/**
826 * Clears the read FIFO.
827 *
828 * This is useful in the event of an unexpected error as a means of reseting
829 * state.
830 *
831 * Note that this does not reset the handle's internal `words_remaining` or
832 * `transaction_pending` tracking. After an aborted transaction, the handle
833 * must be reinitialized with `dif_rram_ctrl_init_state()` (which has no MMIO
834 * side effects) before starting a new one; otherwise `dif_rram_ctrl_start()`
835 * returns `kDifUnavailable` and `dif_rram_ctrl_end()` returns
836 * `kDifIpFifoFull`. See #30909 for adding a proper way to abort an ongoing
837 * transaction.
838 *
839 * @param handle The RRAM controller DIF state.
840 * @return `kDifBadArg` if `handle` is null. `kDifOk` otherwise.
841 */
844
845// TODO(#30908): This only covers FAULT_STATUS bits 0-7. It is missing
846// `seed_err`, `phy_relbl_err`, `phy_rd_intg_err`, `phy_rd_ctrl_err`,
847// `spurious_done`, and `host_gnt_err`. `phy_relbl_err` in particular has no
848// accessor to read or clear it (it is `rw0c` and firmware needs to clear it
849// during firmware selection), nor is there a way to set the companion
850// `DIS.RELBL_ERR_FATAL`. `STD_FAULT_STATUS`, `HW_INFO_CFG_OVERRIDE`, and
851// `CURR_FIFO_LVL` also have no accessors.
852typedef struct dif_rram_ctrl_faults {
853 /** The lcmgr hardware interface encountered an invalid operation. */
855 /** The lcmgr hardware interface encountered a memory permission error. */
857 /** The lcmgr hardware interface encountered a read data error. */
859 /** The lcmgr hardware interface encountered a write data error. */
861 /** The otp hardware interface encountered an invalid operation. */
863 /** The otp hardware interface encountered a memory permission error. */
865 /** The otp hardware interface encountered a read data error. */
867 /** The otp hardware interface encountered a write data error. */
869} dif_rram_ctrl_faults_t;
870
871/**
872 * Gets the unrecoverable or hardware faults.
873 *
874 * @param handle The RRAM controller DIF state.
875 * @param[out] faults_out Out parameter, a pointer to the location to write
876 * the fault values.
877 * @return `kDifBadArg` if `handle` or `faults_out` is null. `kDifOk`
878 * otherwise.
879 */
882 dif_rram_ctrl_faults_t *faults_out);
883
885 /** Count of the number of correctable ECC errors. */
887 /** The last address that produced a correctable ECC error. */
889 /** The last partition that produced a correctable ECC error. */
891} dif_rram_ctrl_ecc_errors_t;
892
893/**
894 * Get the ECC error information of the RRAM.
895 *
896 * @param handle The RRAM controller DIF state.
897 * @param[out] errors_out Out parameter, the ECC error information.
898 * @return `kDifBadArg` if `handle` or `errors_out` is null. `kDifOk`
899 * otherwise.
900 */
903 const dif_rram_ctrl_state_t *handle,
904 dif_rram_ctrl_ecc_errors_t *errors_out);
905
907 /** RRAM phy controller initialization complete. */
909 /** RRAM phy write operation in progress. */
911} dif_rram_ctrl_phy_status_t;
912
913/**
914 * Query the status registers on the RRAM controller.
915 *
916 * This function checks the various status bits as described in
917 * `dif_rram_ctrl_phy_status_t`.
918 *
919 * @param handle The RRAM controller DIF state.
920 * @param[out] status_out Out-parameter, the current status of the RRAM phy.
921 * @return `kDifBadArg` if `handle` or `status_out` is null. `kDifOk`
922 * otherwise.
923 */
926 const dif_rram_ctrl_state_t *handle,
927 dif_rram_ctrl_phy_status_t *status_out);
928
929/**
930 * Set the value of the scratch register.
931 *
932 * @param handle The RRAM controller DIF state.
933 * @param value The value to set the scratch register to.
934 * @return `kDifBadArg` if `handle` is null. `kDifOk` otherwise.
935 */
938 uint32_t value);
939
940/**
941 * Get the value of the scratch register.
942 *
943 * @param handle The RRAM controller DIF state.
944 * @param[out] value_out Out parameter. The location to write the scratch
945 * register's value to.
946 * @return `kDifBadArg` if `handle` or `value_out` is null. `kDifOk` otherwise.
947 */
950 uint32_t *value_out);
951
952#ifdef __cplusplus
953} // extern "C"
954#endif // __cplusplus
955
956#endif // OPENTITAN_SW_DEVICE_LIB_DIF_DIF_RRAM_CTRL_H_