Software APIs
dif_pwrmgr_unittest.cc
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 #include "sw/device/lib/dif/dif_pwrmgr.h"
6 
7 #include <array>
8 
9 #include "gtest/gtest.h"
10 #include "sw/device/lib/base/mmio.h"
11 #include "sw/device/lib/base/mock_mmio.h"
12 #include "sw/device/lib/dif/dif_base.h"
13 #include "sw/device/lib/dif/dif_test_base.h"
14 
15 #include "pwrmgr_regs.h" // Generated
16 
17 namespace dif_pwrmgr_unittest {
18 namespace {
19 
20 /**
21  * Returns a `uint32_t` with a single zero bit.
22  */
23 uint32_t AllOnesExcept(uint32_t index) { return ~(1u << index); }
24 
25 /**
26  * Common constants used in tests.
27  */
28 static constexpr std::array<dif_toggle_t, 2> kAllToggles = {
29  kDifToggleDisabled,
30  kDifToggleEnabled,
31 };
32 static constexpr std::array<bool, 2> kAllBools = {true, false};
33 static constexpr dif_toggle_t kBadToggle = static_cast<dif_toggle_t>(2);
34 static constexpr dif_pwrmgr_req_type_t kBadReqType =
35  static_cast<dif_pwrmgr_req_type_t>(kDifPwrmgrReqTypeReset + 1);
36 static constexpr dif_pwrmgr_domain_config_t kBadConfig =
37  std::numeric_limits<uint8_t>::max();
38 static constexpr dif_pwrmgr_request_sources_t kBadSources =
39  std::numeric_limits<uint32_t>::max();
40 
41 // Base class for the rest of the tests in this file, provides a
42 // `dif_pwrmgr_t` instance.
43 class DifPwrmgrInitialized : public testing::Test, public mock_mmio::MmioTest {
44  protected:
45  /**
46  * Expectations for functions that need to sync data to slow clock domain.
47  *
48  * Sync is triggered by writing a 1 to the CFG_CDC_SYNC register, which is
49  * reset back to 0 by the hardware when the operation is complete.
50  */
51  void ExpectSync() {
52  EXPECT_WRITE32(PWRMGR_CFG_CDC_SYNC_REG_OFFSET, 1);
53  // Insert a small random delay.
54  uint8_t rand_delay = dev().GarbageMemory<uint32_t>() & 0x7F;
55  for (uint8_t i = 0; i < rand_delay; ++i) {
56  EXPECT_READ32(PWRMGR_CFG_CDC_SYNC_REG_OFFSET, 1);
57  }
58  EXPECT_READ32(PWRMGR_CFG_CDC_SYNC_REG_OFFSET, 0);
59  }
60 
61  /**
62  * Initialized `dif_pwrmgr_t` used in tests.
63  */
64  const dif_pwrmgr_t pwrmgr_ = {.base_addr = dev().region()};
65 };
66 
67 class LowPowerTest : public DifPwrmgrInitialized {};
68 
69 TEST_F(LowPowerTest, SetBadArgs) {
70  EXPECT_DIF_BADARG(dif_pwrmgr_low_power_set_enabled(nullptr, kDifToggleEnabled,
71  kDifToggleEnabled));
72  EXPECT_DIF_BADARG(dif_pwrmgr_low_power_set_enabled(&pwrmgr_, kBadToggle,
73  kDifToggleEnabled));
74  EXPECT_DIF_BADARG(dif_pwrmgr_low_power_set_enabled(
75  &pwrmgr_, kDifToggleEnabled, kBadToggle));
76  EXPECT_DIF_BADARG(
77  dif_pwrmgr_low_power_set_enabled(nullptr, kBadToggle, kDifToggleEnabled));
78  EXPECT_DIF_BADARG(
79  dif_pwrmgr_low_power_set_enabled(nullptr, kDifToggleEnabled, kBadToggle));
80  EXPECT_DIF_BADARG(
81  dif_pwrmgr_low_power_set_enabled(&pwrmgr_, kBadToggle, kBadToggle));
82  EXPECT_DIF_BADARG(
83  dif_pwrmgr_low_power_set_enabled(nullptr, kBadToggle, kBadToggle));
84 }
85 
86 TEST_F(LowPowerTest, SetLocked) {
87  for (auto new_toggle : kAllToggles) {
88  for (auto sync_toggle : kAllToggles) {
89  EXPECT_READ32(PWRMGR_CTRL_CFG_REGWEN_REG_OFFSET,
90  AllOnesExcept(PWRMGR_CTRL_CFG_REGWEN_EN_BIT));
91 
92  EXPECT_EQ(
93  dif_pwrmgr_low_power_set_enabled(&pwrmgr_, new_toggle, sync_toggle),
94  kDifLocked);
95  }
96  }
97 }
98 
99 TEST_F(LowPowerTest, Set) {
100  for (auto new_toggle : kAllToggles) {
101  for (auto sync_toggle : kAllToggles) {
102  EXPECT_READ32(PWRMGR_CTRL_CFG_REGWEN_REG_OFFSET,
103  {{
104  .offset = PWRMGR_CTRL_CFG_REGWEN_EN_BIT,
105  .value = 1,
106  }});
107  EXPECT_MASK32(PWRMGR_CONTROL_REG_OFFSET,
108  {{
109  .offset = PWRMGR_CONTROL_LOW_POWER_HINT_BIT,
110  .mask = 1,
111  .value = (new_toggle == kDifToggleEnabled),
112  }});
113  if (sync_toggle == kDifToggleEnabled)
114  ExpectSync();
115 
116  EXPECT_DIF_OK(
117  dif_pwrmgr_low_power_set_enabled(&pwrmgr_, new_toggle, sync_toggle));
118  }
119  }
120 }
121 
122 TEST_F(LowPowerTest, GetBadArgs) {
123  dif_toggle_t state;
124 
125  EXPECT_DIF_BADARG(dif_pwrmgr_low_power_get_enabled(nullptr, &state));
126  EXPECT_DIF_BADARG(dif_pwrmgr_low_power_get_enabled(&pwrmgr_, nullptr));
127  EXPECT_DIF_BADARG(dif_pwrmgr_low_power_get_enabled(nullptr, nullptr));
128 }
129 
130 TEST_F(LowPowerTest, Get) {
131  for (auto toggle : kAllToggles) {
132  dif_toggle_t state;
133 
134  EXPECT_READ32(PWRMGR_CONTROL_REG_OFFSET,
135  {{
136  .offset = PWRMGR_CONTROL_LOW_POWER_HINT_BIT,
137  .value = (toggle == kDifToggleEnabled),
138  }});
139 
140  EXPECT_DIF_OK(dif_pwrmgr_low_power_get_enabled(&pwrmgr_, &state));
141  EXPECT_EQ(state, toggle);
142  }
143 }
144 
145 class DomainConfig : public DifPwrmgrInitialized {
146  protected:
147  /**
148  * Constants used in set and get tests.
149  */
150  static constexpr bitfield_field32_t kConfigBitfield{
151  .mask = kDifPwrmgrDomainOptionCoreClockInLowPower |
152  kDifPwrmgrDomainOptionIoClockInLowPower |
153  kDifPwrmgrDomainOptionUsbClockInLowPower |
154  kDifPwrmgrDomainOptionUsbClockInActivePower |
155  kDifPwrmgrDomainOptionMainPowerInLowPower,
156  .index = PWRMGR_CONTROL_CORE_CLK_EN_BIT,
157  };
158  static constexpr std::array<dif_pwrmgr_domain_config_t, 4> kConfigs = {
159  // All disabled.
160  0,
161  // All enabled.
162  kDifPwrmgrDomainOptionCoreClockInLowPower |
163  kDifPwrmgrDomainOptionIoClockInLowPower |
164  kDifPwrmgrDomainOptionUsbClockInLowPower |
165  kDifPwrmgrDomainOptionUsbClockInActivePower |
166  kDifPwrmgrDomainOptionMainPowerInLowPower,
167  // Some enabled.
168  kDifPwrmgrDomainOptionCoreClockInLowPower |
169  kDifPwrmgrDomainOptionUsbClockInLowPower |
170  kDifPwrmgrDomainOptionMainPowerInLowPower,
171  // Some enabled.
172  kDifPwrmgrDomainOptionIoClockInLowPower |
173  kDifPwrmgrDomainOptionUsbClockInActivePower,
174  };
175 };
176 // We need this definition for the `for` loops.
177 constexpr std::array<dif_pwrmgr_domain_config_t, 4> DomainConfig::kConfigs;
178 
179 TEST_F(DomainConfig, SetBadArgs) {
180  EXPECT_DIF_BADARG(
181  dif_pwrmgr_set_domain_config(nullptr, 0, kDifToggleEnabled));
182  EXPECT_DIF_BADARG(
183  dif_pwrmgr_set_domain_config(&pwrmgr_, kBadConfig, kDifToggleEnabled));
184  EXPECT_DIF_BADARG(dif_pwrmgr_set_domain_config(&pwrmgr_, 0, kBadToggle));
185  EXPECT_DIF_BADARG(
186  dif_pwrmgr_set_domain_config(nullptr, kBadConfig, kDifToggleEnabled));
187  EXPECT_DIF_BADARG(dif_pwrmgr_set_domain_config(nullptr, 0, kBadToggle));
188  EXPECT_DIF_BADARG(
189  dif_pwrmgr_set_domain_config(&pwrmgr_, kBadConfig, kBadToggle));
190  EXPECT_DIF_BADARG(
191  dif_pwrmgr_set_domain_config(nullptr, kBadConfig, kBadToggle));
192 }
193 
194 TEST_F(DomainConfig, SetLocked) {
195  EXPECT_READ32(PWRMGR_CTRL_CFG_REGWEN_REG_OFFSET,
196  AllOnesExcept(PWRMGR_WAKEUP_EN_REGWEN_EN_BIT));
197 
198  EXPECT_EQ(dif_pwrmgr_set_domain_config(&pwrmgr_, 0, kDifToggleEnabled),
199  kDifLocked);
200 }
201 
202 TEST_F(DomainConfig, Set) {
203  for (auto config : kConfigs) {
204  for (auto toggle : kAllToggles) {
205  EXPECT_READ32(PWRMGR_CTRL_CFG_REGWEN_REG_OFFSET,
206  {{
207  .offset = PWRMGR_CTRL_CFG_REGWEN_EN_BIT,
208  .value = 1,
209  }});
210  EXPECT_MASK32(PWRMGR_CONTROL_REG_OFFSET,
211  {{
212  .offset = kConfigBitfield.index,
213  .mask = kConfigBitfield.mask,
214  .value = config,
215  }});
216  if (toggle == kDifToggleEnabled)
217  ExpectSync();
218 
219  EXPECT_DIF_OK(dif_pwrmgr_set_domain_config(&pwrmgr_, config, toggle));
220  }
221  }
222 }
223 
224 TEST_F(DomainConfig, GetBadArgs) {
225  dif_pwrmgr_domain_config_t config;
226  EXPECT_DIF_BADARG(dif_pwrmgr_get_domain_config(nullptr, &config));
227  EXPECT_DIF_BADARG(dif_pwrmgr_get_domain_config(&pwrmgr_, nullptr));
228  EXPECT_DIF_BADARG(dif_pwrmgr_get_domain_config(nullptr, nullptr));
229 }
230 
231 TEST_F(DomainConfig, Get) {
232  for (auto exp_config : kConfigs) {
233  EXPECT_READ32(PWRMGR_CONTROL_REG_OFFSET,
234  {{
235  .offset = kConfigBitfield.index,
236  .value = exp_config,
237  }});
238 
239  dif_pwrmgr_domain_config_t act_config;
240  EXPECT_DIF_OK(dif_pwrmgr_get_domain_config(&pwrmgr_, &act_config));
241  EXPECT_EQ(act_config, exp_config);
242  }
243 }
244 
245 class RequestSources : public DifPwrmgrInitialized {
246  protected:
247  /**
248  * Constants used in set and get tests.
249  */
250  static constexpr std::array<dif_pwrmgr_request_sources_t, 2> kWakeupSources =
251  {
252  // No sources.
253  0,
254  // All sources.
255  kDifPwrmgrWakeupRequestSourceOne,
256  };
257  static constexpr std::array<dif_pwrmgr_request_sources_t, 2> kResetSources = {
258  // No sources.
259  0,
260  // All sources.
261  kDifPwrmgrResetRequestSourceOne,
262  };
263 };
264 // We need these definitions for the `for` loops.
265 constexpr std::array<dif_pwrmgr_request_sources_t, 2>
266  RequestSources::kWakeupSources;
267 constexpr std::array<dif_pwrmgr_request_sources_t, 2>
268  RequestSources::kResetSources;
269 
270 TEST_F(RequestSources, SetBadArgs) {
271  EXPECT_DIF_BADARG(dif_pwrmgr_set_request_sources(
272  nullptr, kDifPwrmgrReqTypeWakeup, kDifPwrmgrWakeupRequestSourceOne,
273  kDifToggleEnabled));
274  EXPECT_DIF_BADARG(dif_pwrmgr_set_request_sources(
275  &pwrmgr_, kBadReqType, kDifPwrmgrWakeupRequestSourceOne,
276  kDifToggleEnabled));
277  EXPECT_DIF_BADARG(dif_pwrmgr_set_request_sources(
278  &pwrmgr_, kDifPwrmgrReqTypeWakeup, kBadSources, kDifToggleEnabled));
279  EXPECT_DIF_BADARG(dif_pwrmgr_set_request_sources(
280  &pwrmgr_, kDifPwrmgrReqTypeWakeup, kDifPwrmgrWakeupRequestSourceOne,
281  kBadToggle));
282  EXPECT_DIF_BADARG(dif_pwrmgr_set_request_sources(
283  nullptr, kBadReqType, kDifPwrmgrWakeupRequestSourceOne,
284  kDifToggleEnabled));
285  EXPECT_DIF_BADARG(dif_pwrmgr_set_request_sources(
286  nullptr, kDifPwrmgrReqTypeWakeup, kBadSources, kDifToggleEnabled));
287  EXPECT_DIF_BADARG(dif_pwrmgr_set_request_sources(
288  nullptr, kDifPwrmgrReqTypeWakeup, kDifPwrmgrWakeupRequestSourceOne,
289  kBadToggle));
290  EXPECT_DIF_BADARG(dif_pwrmgr_set_request_sources(
291  &pwrmgr_, kBadReqType, kBadSources, kDifToggleEnabled));
292  EXPECT_DIF_BADARG(dif_pwrmgr_set_request_sources(
293  &pwrmgr_, kBadReqType, kDifPwrmgrWakeupRequestSourceOne, kBadToggle));
294  EXPECT_DIF_BADARG(dif_pwrmgr_set_request_sources(
295  &pwrmgr_, kDifPwrmgrReqTypeWakeup, kBadSources, kBadToggle));
296  EXPECT_DIF_BADARG(dif_pwrmgr_set_request_sources(
297  nullptr, kBadReqType, kBadSources, kDifToggleEnabled));
298  EXPECT_DIF_BADARG(dif_pwrmgr_set_request_sources(
299  nullptr, kBadReqType, kDifPwrmgrWakeupRequestSourceOne, kBadToggle));
300  EXPECT_DIF_BADARG(dif_pwrmgr_set_request_sources(
301  nullptr, kDifPwrmgrReqTypeWakeup, kBadSources, kBadToggle));
302  EXPECT_DIF_BADARG(dif_pwrmgr_set_request_sources(&pwrmgr_, kBadReqType,
303  kBadSources, kBadToggle));
304 
305  EXPECT_DIF_BADARG(dif_pwrmgr_set_request_sources(nullptr, kBadReqType,
306  kBadSources, kBadToggle));
307 }
308 
309 TEST_F(RequestSources, SetWakeupLocked) {
310  EXPECT_READ32(PWRMGR_WAKEUP_EN_REGWEN_REG_OFFSET,
311  AllOnesExcept(PWRMGR_WAKEUP_EN_REGWEN_EN_BIT));
312 
313  EXPECT_EQ(dif_pwrmgr_set_request_sources(&pwrmgr_, kDifPwrmgrReqTypeWakeup,
314  kDifPwrmgrWakeupRequestSourceOne,
315  kDifToggleEnabled),
316  kDifLocked);
317 }
318 
319 TEST_F(RequestSources, SetResetLocked) {
320  EXPECT_READ32(PWRMGR_RESET_EN_REGWEN_REG_OFFSET,
321  AllOnesExcept(PWRMGR_RESET_EN_REGWEN_EN_BIT));
322 
323  EXPECT_EQ(dif_pwrmgr_set_request_sources(&pwrmgr_, kDifPwrmgrReqTypeReset,
324  kDifPwrmgrResetRequestSourceOne,
325  kDifToggleEnabled),
326  kDifLocked);
327 }
328 
329 TEST_F(RequestSources, SetWakeup) {
330  for (auto toggle : kAllToggles) {
331  EXPECT_READ32(PWRMGR_WAKEUP_EN_REGWEN_REG_OFFSET,
332  {{
333  .offset = PWRMGR_WAKEUP_EN_REGWEN_EN_BIT,
334  .value = 1,
335  }});
336  EXPECT_WRITE32(PWRMGR_WAKEUP_EN_REG_OFFSET,
337  kDifPwrmgrWakeupRequestSourceOne);
338  if (toggle == kDifToggleEnabled)
339  ExpectSync();
340 
341  EXPECT_DIF_OK(dif_pwrmgr_set_request_sources(
342  &pwrmgr_, kDifPwrmgrReqTypeWakeup, kDifPwrmgrWakeupRequestSourceOne,
343  toggle));
344  }
345 }
346 
347 TEST_F(RequestSources, SetReset) {
348  for (auto toggle : kAllToggles) {
349  EXPECT_READ32(PWRMGR_RESET_EN_REGWEN_REG_OFFSET,
350  {{
351  .offset = PWRMGR_RESET_EN_REGWEN_EN_BIT,
352  .value = 1,
353  }});
354  EXPECT_WRITE32(PWRMGR_RESET_EN_REG_OFFSET, kDifPwrmgrResetRequestSourceOne);
355  if (toggle == kDifToggleEnabled)
356  ExpectSync();
357 
358  EXPECT_DIF_OK(dif_pwrmgr_set_request_sources(
359  &pwrmgr_, kDifPwrmgrReqTypeReset, kDifPwrmgrResetRequestSourceOne,
360  toggle));
361  }
362 }
363 
364 TEST_F(RequestSources, GetBadArgs) {
365  dif_pwrmgr_request_sources_t sources;
366 
367  EXPECT_DIF_BADARG(dif_pwrmgr_get_request_sources(
368  nullptr, kDifPwrmgrReqTypeWakeup, &sources));
369  EXPECT_DIF_BADARG(
370  dif_pwrmgr_get_request_sources(&pwrmgr_, kBadReqType, &sources));
371  EXPECT_DIF_BADARG(dif_pwrmgr_get_request_sources(
372  &pwrmgr_, kDifPwrmgrReqTypeWakeup, nullptr));
373  EXPECT_DIF_BADARG(
374  dif_pwrmgr_get_request_sources(nullptr, kBadReqType, &sources));
375  EXPECT_DIF_BADARG(dif_pwrmgr_get_request_sources(
376  nullptr, kDifPwrmgrReqTypeWakeup, nullptr));
377  EXPECT_DIF_BADARG(
378  dif_pwrmgr_get_request_sources(&pwrmgr_, kBadReqType, nullptr));
379  EXPECT_DIF_BADARG(
380  dif_pwrmgr_get_request_sources(nullptr, kBadReqType, nullptr));
381 }
382 
383 TEST_F(RequestSources, GetWakeup) {
384  for (auto exp_sources : kWakeupSources) {
385  EXPECT_READ32(PWRMGR_WAKEUP_EN_REG_OFFSET, exp_sources);
386 
387  dif_pwrmgr_request_sources_t act_sources = 0;
388  EXPECT_DIF_OK(dif_pwrmgr_get_request_sources(
389  &pwrmgr_, kDifPwrmgrReqTypeWakeup, &act_sources));
390  EXPECT_EQ(act_sources, exp_sources);
391  }
392 }
393 
394 TEST_F(RequestSources, GetReset) {
395  for (auto exp_sources : kResetSources) {
396  EXPECT_READ32(PWRMGR_RESET_EN_REG_OFFSET, exp_sources);
397 
398  dif_pwrmgr_request_sources_t act_sources = 0;
399  EXPECT_DIF_OK(dif_pwrmgr_get_request_sources(
400  &pwrmgr_, kDifPwrmgrReqTypeReset, &act_sources));
401  EXPECT_EQ(act_sources, exp_sources);
402  }
403 }
404 
405 TEST_F(RequestSources, GetCurrentBadArgs) {
406  dif_pwrmgr_request_sources_t sources;
407 
408  EXPECT_DIF_BADARG(dif_pwrmgr_get_current_request_sources(
409  nullptr, kDifPwrmgrReqTypeWakeup, &sources));
410  EXPECT_DIF_BADARG(
411  dif_pwrmgr_get_current_request_sources(&pwrmgr_, kBadReqType, &sources));
412  EXPECT_DIF_BADARG(dif_pwrmgr_get_current_request_sources(
413  &pwrmgr_, kDifPwrmgrReqTypeWakeup, nullptr));
414  EXPECT_DIF_BADARG(
415  dif_pwrmgr_get_current_request_sources(nullptr, kBadReqType, &sources));
416  EXPECT_DIF_BADARG(dif_pwrmgr_get_current_request_sources(
417  nullptr, kDifPwrmgrReqTypeWakeup, nullptr));
418  EXPECT_DIF_BADARG(
419  dif_pwrmgr_get_current_request_sources(&pwrmgr_, kBadReqType, nullptr));
420  EXPECT_DIF_BADARG(
421  dif_pwrmgr_get_current_request_sources(nullptr, kBadReqType, nullptr));
422 }
423 
424 TEST_F(RequestSources, GetCurrentWakeup) {
425  for (auto exp_sources : kWakeupSources) {
426  EXPECT_READ32(PWRMGR_WAKE_STATUS_REG_OFFSET, exp_sources);
427 
428  dif_pwrmgr_request_sources_t act_sources = 0;
429  EXPECT_DIF_OK(dif_pwrmgr_get_current_request_sources(
430  &pwrmgr_, kDifPwrmgrReqTypeWakeup, &act_sources));
431  EXPECT_EQ(act_sources, exp_sources);
432  }
433 }
434 
435 TEST_F(RequestSources, GetCurrentReset) {
436  for (auto exp_sources : kResetSources) {
437  EXPECT_READ32(PWRMGR_RESET_STATUS_REG_OFFSET, exp_sources);
438 
439  dif_pwrmgr_request_sources_t act_sources = 0;
440  EXPECT_DIF_OK(dif_pwrmgr_get_current_request_sources(
441  &pwrmgr_, kDifPwrmgrReqTypeReset, &act_sources));
442  EXPECT_EQ(act_sources, exp_sources);
443  }
444 }
445 
446 TEST_F(RequestSources, LockBadArgs) {
447  EXPECT_DIF_BADARG(
448  dif_pwrmgr_request_sources_lock(nullptr, kDifPwrmgrReqTypeWakeup));
449  EXPECT_DIF_BADARG(dif_pwrmgr_request_sources_lock(&pwrmgr_, kBadReqType));
450  EXPECT_DIF_BADARG(dif_pwrmgr_request_sources_lock(nullptr, kBadReqType));
451 }
452 
453 TEST_F(RequestSources, LockWakeup) {
454  EXPECT_WRITE32(PWRMGR_WAKEUP_EN_REGWEN_REG_OFFSET, 0);
455 
456  EXPECT_DIF_OK(
457  dif_pwrmgr_request_sources_lock(&pwrmgr_, kDifPwrmgrReqTypeWakeup));
458 }
459 
460 TEST_F(RequestSources, LockReset) {
461  EXPECT_WRITE32(PWRMGR_RESET_EN_REGWEN_REG_OFFSET, 0);
462 
463  EXPECT_DIF_OK(
464  dif_pwrmgr_request_sources_lock(&pwrmgr_, kDifPwrmgrReqTypeReset));
465 }
466 
467 TEST_F(RequestSources, IsLockedBadArgs) {
468  bool is_locked;
469 
470  EXPECT_DIF_BADARG(dif_pwrmgr_request_sources_is_locked(
471  nullptr, kDifPwrmgrReqTypeWakeup, &is_locked));
472  EXPECT_DIF_BADARG(
473  dif_pwrmgr_request_sources_is_locked(&pwrmgr_, kBadReqType, &is_locked));
474  EXPECT_DIF_BADARG(dif_pwrmgr_request_sources_is_locked(
475  &pwrmgr_, kDifPwrmgrReqTypeWakeup, nullptr));
476  EXPECT_DIF_BADARG(
477  dif_pwrmgr_request_sources_is_locked(nullptr, kBadReqType, &is_locked));
478  EXPECT_DIF_BADARG(dif_pwrmgr_request_sources_is_locked(
479  nullptr, kDifPwrmgrReqTypeWakeup, nullptr));
480  EXPECT_DIF_BADARG(
481  dif_pwrmgr_request_sources_is_locked(&pwrmgr_, kBadReqType, nullptr));
482  EXPECT_DIF_BADARG(
483  dif_pwrmgr_request_sources_is_locked(nullptr, kBadReqType, nullptr));
484 }
485 
486 TEST_F(RequestSources, IsLockedWakeup) {
487  for (auto exp_val : kAllBools) {
488  EXPECT_READ32(PWRMGR_WAKEUP_EN_REGWEN_REG_OFFSET,
489  {{
490  .offset = PWRMGR_WAKEUP_EN_REGWEN_EN_BIT,
491  .value = !exp_val,
492  }});
493 
494  bool is_locked = !exp_val;
495  EXPECT_DIF_OK(dif_pwrmgr_request_sources_is_locked(
496  &pwrmgr_, kDifPwrmgrReqTypeWakeup, &is_locked));
497  EXPECT_EQ(is_locked, exp_val);
498  }
499 }
500 
501 TEST_F(RequestSources, IsLockedReset) {
502  for (auto exp_val : kAllBools) {
503  EXPECT_READ32(PWRMGR_RESET_EN_REGWEN_REG_OFFSET,
504  {{
505  .offset = PWRMGR_RESET_EN_REGWEN_EN_BIT,
506  .value = !exp_val,
507  }});
508 
509  bool is_locked = !exp_val;
510  EXPECT_DIF_OK(dif_pwrmgr_request_sources_is_locked(
511  &pwrmgr_, kDifPwrmgrReqTypeReset, &is_locked));
512  EXPECT_EQ(is_locked, exp_val);
513  }
514 }
515 
516 class WakeupRecording : public DifPwrmgrInitialized {};
517 
518 TEST_F(WakeupRecording, SetEnabledBadArgs) {
519  EXPECT_DIF_BADARG(dif_pwrmgr_wakeup_request_recording_set_enabled(
520  nullptr, kDifToggleEnabled));
521  EXPECT_DIF_BADARG(
522  dif_pwrmgr_wakeup_request_recording_set_enabled(&pwrmgr_, kBadToggle));
523  EXPECT_DIF_BADARG(
524  dif_pwrmgr_wakeup_request_recording_set_enabled(nullptr, kBadToggle));
525 }
526 
527 TEST_F(WakeupRecording, SetEnabled) {
528  for (auto new_state : kAllToggles) {
529  EXPECT_WRITE32(PWRMGR_WAKE_INFO_CAPTURE_DIS_REG_OFFSET,
530  {{
531  .offset = PWRMGR_WAKE_INFO_CAPTURE_DIS_VAL_BIT,
532  .value = (new_state == kDifToggleDisabled),
533  }});
534 
535  EXPECT_DIF_OK(
536  dif_pwrmgr_wakeup_request_recording_set_enabled(&pwrmgr_, new_state));
537  }
538 }
539 
540 TEST_F(WakeupRecording, GetEnabledBadArgs) {
541  dif_toggle_t is_enabled;
542 
543  EXPECT_DIF_BADARG(
544  dif_pwrmgr_wakeup_request_recording_get_enabled(nullptr, &is_enabled));
545  EXPECT_DIF_BADARG(
546  dif_pwrmgr_wakeup_request_recording_get_enabled(&pwrmgr_, nullptr));
547  EXPECT_DIF_BADARG(
548  dif_pwrmgr_wakeup_request_recording_get_enabled(nullptr, nullptr));
549 }
550 
551 TEST_F(WakeupRecording, GetEnabled) {
552  for (auto exp_val : kAllToggles) {
553  EXPECT_READ32(PWRMGR_WAKE_INFO_CAPTURE_DIS_REG_OFFSET,
554  {{
555  .offset = PWRMGR_WAKE_INFO_CAPTURE_DIS_VAL_BIT,
556  .value = (exp_val == kDifToggleDisabled),
557  }});
558 
559  dif_toggle_t is_enabled =
560  (exp_val == kDifToggleEnabled) ? kDifToggleDisabled : kDifToggleEnabled;
561  EXPECT_DIF_OK(
562  dif_pwrmgr_wakeup_request_recording_get_enabled(&pwrmgr_, &is_enabled));
563  EXPECT_EQ(is_enabled, exp_val);
564  }
565 }
566 
567 TEST_F(WakeupRecording, GetReasonBadArgs) {
568  dif_pwrmgr_wakeup_reason_t wakeup_reason;
569 
570  EXPECT_DIF_BADARG(dif_pwrmgr_wakeup_reason_get(nullptr, &wakeup_reason));
571  EXPECT_DIF_BADARG(dif_pwrmgr_wakeup_reason_get(&pwrmgr_, nullptr));
572  EXPECT_DIF_BADARG(dif_pwrmgr_wakeup_reason_get(nullptr, nullptr));
573 }
574 
575 /**
576  * Custom equality matcher for `dif_pwrmgr_wakeup_reason_t`s.
577  */
578 testing::Matcher<dif_pwrmgr_wakeup_reason_t> Eq(
579  const dif_pwrmgr_wakeup_reason_t &rhs) {
580  return testing::AllOf(
581  testing::Field("types", &dif_pwrmgr_wakeup_reason_t::types, rhs.types),
582  testing::Field("request_sources",
583  &dif_pwrmgr_wakeup_reason_t::request_sources,
584  rhs.request_sources));
585 }
586 
587 TEST_F(WakeupRecording, GetReason) {
588  struct TestCase {
589  /**
590  * Value that will be read from hardware.
591  */
592  std::initializer_list<mock_mmio::BitField> read_val;
593  /**
594  * Expected output.
595  */
596  dif_pwrmgr_wakeup_reason_t exp_output;
597  };
598 
599  std::array<TestCase, 10> test_cases = {{
600  // No bits set.
601  {
602  .read_val = {{
603  .offset = 0,
604  .value = 0,
605  }},
606  .exp_output =
607  {
608  .types = 0,
609  .request_sources = 0,
610  },
611  },
612  // All bits set.
613  {
614  .read_val = {{
615  .offset = PWRMGR_WAKE_INFO_ABORT_BIT,
616  .value = 1,
617  },
618  {
619  .offset = PWRMGR_WAKE_INFO_FALL_THROUGH_BIT,
620  .value = 1,
621  },
622  {
623  .offset = PWRMGR_PARAM_SYSRST_CTRL_AON_WKUP_REQ_IDX,
624  .value = 1,
625  },
626  {
627  .offset = PWRMGR_PARAM_ADC_CTRL_AON_WKUP_REQ_IDX,
628  .value = 1,
629  },
630  {
631  .offset = PWRMGR_PARAM_PINMUX_AON_PIN_WKUP_REQ_IDX,
632  .value = 1,
633  },
634  {
635  .offset = PWRMGR_PARAM_PINMUX_AON_USB_WKUP_REQ_IDX,
636  .value = 1,
637  },
638  {
639  .offset = PWRMGR_PARAM_AON_TIMER_AON_WKUP_REQ_IDX,
640  .value = 1,
641  },
642  {
643  .offset = PWRMGR_PARAM_SENSOR_CTRL_AON_WKUP_REQ_IDX,
644  .value = 1,
645  }},
646  .exp_output = {.types = kDifPwrmgrWakeupTypeAbort |
647  kDifPwrmgrWakeupTypeFallThrough |
648  kDifPwrmgrWakeupTypeRequest,
649  .request_sources = kDifPwrmgrWakeupRequestSourceOne |
650  kDifPwrmgrWakeupRequestSourceTwo |
651  kDifPwrmgrWakeupRequestSourceThree |
652  kDifPwrmgrWakeupRequestSourceFour |
653  kDifPwrmgrWakeupRequestSourceFive |
654  kDifPwrmgrWakeupRequestSourceSix},
655  },
656  // Only abort.
657  {
658  .read_val = {{
659  .offset = PWRMGR_WAKE_INFO_ABORT_BIT,
660  .value = 1,
661  }},
662  .exp_output =
663  {
664  .types = kDifPwrmgrWakeupTypeAbort,
665  .request_sources = 0,
666  },
667  },
668  // Only fall-through.
669  {
670  .read_val = {{
671  .offset = PWRMGR_WAKE_INFO_FALL_THROUGH_BIT,
672  .value = 1,
673  }},
674  .exp_output =
675  {
676  .types = kDifPwrmgrWakeupTypeFallThrough,
677  .request_sources = 0,
678  },
679  },
680  // Only requests from peripherals.
681  {
682  .read_val = {{
683  .offset = PWRMGR_PARAM_SYSRST_CTRL_AON_WKUP_REQ_IDX,
684  .value = 1,
685  }},
686  .exp_output =
687  {
688  .types = kDifPwrmgrWakeupTypeRequest,
689  .request_sources = kDifPwrmgrWakeupRequestSourceOne,
690  },
691  },
692  {
693  .read_val = {{
694  .offset = PWRMGR_PARAM_ADC_CTRL_AON_WKUP_REQ_IDX,
695  .value = 1,
696  }},
697  .exp_output =
698  {
699  .types = kDifPwrmgrWakeupTypeRequest,
700  .request_sources = kDifPwrmgrWakeupRequestSourceTwo,
701  },
702  },
703  {
704  .read_val = {{
705  .offset = PWRMGR_PARAM_PINMUX_AON_PIN_WKUP_REQ_IDX,
706  .value = 1,
707  }},
708  .exp_output =
709  {
710  .types = kDifPwrmgrWakeupTypeRequest,
711  .request_sources = kDifPwrmgrWakeupRequestSourceThree,
712  },
713  },
714  {
715  .read_val = {{
716  .offset = PWRMGR_PARAM_PINMUX_AON_USB_WKUP_REQ_IDX,
717  .value = 1,
718  }},
719  .exp_output =
720  {
721  .types = kDifPwrmgrWakeupTypeRequest,
722  .request_sources = kDifPwrmgrWakeupRequestSourceFour,
723  },
724  },
725  {
726  .read_val = {{
727  .offset = PWRMGR_PARAM_AON_TIMER_AON_WKUP_REQ_IDX,
728  .value = 1,
729  }},
730  .exp_output =
731  {
732  .types = kDifPwrmgrWakeupTypeRequest,
733  .request_sources = kDifPwrmgrWakeupRequestSourceFive,
734  },
735  },
736  {
737  .read_val = {{
738  .offset = PWRMGR_PARAM_SENSOR_CTRL_AON_WKUP_REQ_IDX,
739  .value = 1,
740  }},
741  .exp_output =
742  {
743  .types = kDifPwrmgrWakeupTypeRequest,
744  .request_sources = kDifPwrmgrWakeupRequestSourceSix,
745  },
746  },
747  }};
748 
749  for (const auto &test_case : test_cases) {
750  EXPECT_READ32(PWRMGR_WAKE_INFO_REG_OFFSET, test_case.read_val);
751 
752  dif_pwrmgr_wakeup_reason_t wakeup_reason;
753  EXPECT_DIF_OK(dif_pwrmgr_wakeup_reason_get(&pwrmgr_, &wakeup_reason));
754  EXPECT_THAT(wakeup_reason, Eq(test_case.exp_output));
755  }
756 }
757 
758 TEST_F(WakeupRecording, ClearReasonBadArgs) {
759  EXPECT_DIF_BADARG(dif_pwrmgr_wakeup_reason_clear(nullptr));
760 }
761 
762 TEST_F(WakeupRecording, ClearReason) {
763  EXPECT_WRITE32(PWRMGR_WAKE_INFO_REG_OFFSET,
764  std::numeric_limits<uint32_t>::max());
765 
766  EXPECT_DIF_OK(dif_pwrmgr_wakeup_reason_clear(&pwrmgr_));
767 }
768 
769 class FatalErrorTest : public DifPwrmgrInitialized {};
770 
771 TEST_F(FatalErrorTest, GetBadArgs) {
772  dif_pwrmgr_fatal_err_codes_t codes;
773  EXPECT_DIF_BADARG(dif_pwrmgr_fatal_err_code_get_codes(nullptr, nullptr));
774  EXPECT_DIF_BADARG(dif_pwrmgr_fatal_err_code_get_codes(nullptr, &codes));
775  EXPECT_DIF_BADARG(dif_pwrmgr_fatal_err_code_get_codes(&pwrmgr_, nullptr));
776 }
777 
778 TEST_F(FatalErrorTest, GetCodes) {
779  dif_pwrmgr_fatal_err_codes_t codes;
780  EXPECT_READ32(PWRMGR_FAULT_STATUS_REG_OFFSET, 6);
781  EXPECT_DIF_OK(dif_pwrmgr_fatal_err_code_get_codes(&pwrmgr_, &codes));
782  EXPECT_EQ(codes, 6);
783 }
784 
785 } // namespace
786 } // namespace dif_pwrmgr_unittest
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