Software APIs
dif_pinmux_unittest.cc
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 #include "sw/device/lib/dif/dif_pinmux.h"
6 
7 #include "gtest/gtest.h"
8 #include "sw/device/lib/base/mmio.h"
9 #include "sw/device/lib/base/mock_mmio.h"
10 #include "sw/device/lib/dif/dif_base.h"
11 #include "sw/device/lib/dif/dif_test_base.h"
12 
13 #include "pinmux_regs.h" // Generated.
14 
15 namespace dif_pinmux_unittest {
16 namespace {
17 using mock_mmio::MmioTest;
18 using mock_mmio::MockDevice;
19 using testing::Test;
20 
21 class PinmuxTest : public Test, public MmioTest {
22  protected:
23  void SetUp() { ASSERT_DIF_OK(dif_pinmux_init(dev().region(), &dif_pinmux_)); }
24 
25  dif_pinmux_t dif_pinmux_;
26 };
27 
28 TEST_F(PinmuxTest, NullArgs) {
29  dif_pinmux_index_t index_arg{};
30  dif_pinmux_lock_target_t lock_arg{};
31  bool bool_arg{};
32  EXPECT_DIF_BADARG(dif_pinmux_lock(nullptr, index_arg, lock_arg));
33  EXPECT_DIF_BADARG(
34  dif_pinmux_is_locked(nullptr, index_arg, lock_arg, &bool_arg));
35  EXPECT_DIF_BADARG(
36  dif_pinmux_is_locked(&dif_pinmux_, index_arg, lock_arg, nullptr));
37  EXPECT_DIF_BADARG(dif_pinmux_input_select(nullptr, index_arg, index_arg));
38  EXPECT_DIF_BADARG(dif_pinmux_output_select(nullptr, index_arg, index_arg));
39 
40  dif_pinmux_pad_attr_t pad_attr_arg{};
41  dif_pinmux_pad_kind_t pad_kind_arg{};
42  EXPECT_DIF_BADARG(dif_pinmux_pad_write_attrs(nullptr, index_arg, pad_kind_arg,
43  pad_attr_arg, &pad_attr_arg));
44  EXPECT_DIF_BADARG(dif_pinmux_pad_write_attrs(
45  &dif_pinmux_, index_arg, pad_kind_arg, pad_attr_arg, nullptr));
46  EXPECT_DIF_BADARG(dif_pinmux_pad_get_attrs(nullptr, index_arg, pad_kind_arg,
47  &pad_attr_arg));
48  EXPECT_DIF_BADARG(
49  dif_pinmux_pad_get_attrs(&dif_pinmux_, index_arg, pad_kind_arg, nullptr));
50 
51  dif_pinmux_sleep_mode_t sleep_mode_arg{};
52  EXPECT_DIF_BADARG(dif_pinmux_pad_sleep_enable(nullptr, index_arg,
53  pad_kind_arg, sleep_mode_arg));
54  EXPECT_DIF_BADARG(
55  dif_pinmux_pad_sleep_disable(nullptr, index_arg, pad_kind_arg));
56  EXPECT_DIF_BADARG(dif_pinmux_pad_sleep_get_state(nullptr, index_arg,
57  pad_kind_arg, &bool_arg));
58  EXPECT_DIF_BADARG(dif_pinmux_pad_sleep_get_state(&dif_pinmux_, index_arg,
59  pad_kind_arg, nullptr));
60  EXPECT_DIF_BADARG(
61  dif_pinmux_pad_sleep_clear_state(nullptr, index_arg, pad_kind_arg));
62 
63  dif_pinmux_wakeup_config_t wakeup_arg{};
64  EXPECT_DIF_BADARG(
65  dif_pinmux_wakeup_detector_enable(nullptr, index_arg, wakeup_arg));
66  EXPECT_DIF_BADARG(dif_pinmux_wakeup_detector_disable(nullptr, index_arg));
67  EXPECT_DIF_BADARG(dif_pinmux_wakeup_cause_clear(nullptr));
68 
69  uint32_t uint32_arg{};
70  EXPECT_DIF_BADARG(dif_pinmux_wakeup_cause_get(nullptr, &uint32_arg));
71 }
72 
73 TEST_F(PinmuxTest, LockConfig) {
74  bool is_locked;
75  EXPECT_READ32(PINMUX_MIO_PERIPH_INSEL_REGWEN_0_REG_OFFSET, 1);
76  EXPECT_DIF_OK(dif_pinmux_is_locked(&dif_pinmux_, /*index=*/0,
77  kDifPinmuxLockTargetInsel, &is_locked));
78  EXPECT_FALSE(is_locked);
79 
80  EXPECT_READ32(PINMUX_DIO_PAD_SLEEP_REGWEN_1_REG_OFFSET, 0);
81  EXPECT_DIF_OK(dif_pinmux_is_locked(&dif_pinmux_, /*index=*/1,
82  kDifPinmuxLockTargetDioSleep, &is_locked));
83  EXPECT_TRUE(is_locked);
84 
85  EXPECT_WRITE32(PINMUX_MIO_PAD_SLEEP_REGWEN_2_REG_OFFSET, 0);
86  EXPECT_DIF_OK(
87  dif_pinmux_lock(&dif_pinmux_, /*index=*/2, kDifPinmuxLockTargetMioSleep));
88 }
89 
90 TEST_F(PinmuxTest, InputSelection) {
91  EXPECT_READ32(PINMUX_MIO_PERIPH_INSEL_REGWEN_0_REG_OFFSET, 0);
92  EXPECT_EQ(dif_pinmux_input_select(&dif_pinmux_, /*peripheral_input=*/0,
93  /*insel=*/3),
94  kDifLocked);
95 
96  EXPECT_READ32(PINMUX_MIO_PERIPH_INSEL_REGWEN_2_REG_OFFSET, 1);
97  EXPECT_WRITE32(PINMUX_MIO_PERIPH_INSEL_2_REG_OFFSET, 1);
98  EXPECT_DIF_OK(dif_pinmux_input_select(&dif_pinmux_, /*peripheral_input=*/2,
99  /*insel=*/1));
100 }
101 
102 TEST_F(PinmuxTest, OutputSelection) {
103  EXPECT_READ32(PINMUX_MIO_OUTSEL_REGWEN_1_REG_OFFSET, 0);
104  EXPECT_EQ(dif_pinmux_output_select(&dif_pinmux_, /*mio_pad_output=*/1,
105  /*outsel=*/3),
106  kDifLocked);
107 
108  EXPECT_READ32(PINMUX_MIO_OUTSEL_REGWEN_3_REG_OFFSET, 1);
109  EXPECT_WRITE32(PINMUX_MIO_OUTSEL_3_REG_OFFSET, 4);
110  EXPECT_DIF_OK(dif_pinmux_output_select(&dif_pinmux_, /*mio_pad_output=*/3,
111  /*outsel=*/4));
112 }
113 
114 TEST_F(PinmuxTest, PadAttributes) {
115  dif_pinmux_pad_attr_t attrs = {
116  .slew_rate = 2,
117  .drive_strength = 5,
118  .flags = static_cast<dif_pinmux_pad_attr_flags_t>(
119  kDifPinmuxPadAttrInvertLevel | kDifPinmuxPadAttrPullResistorEnable |
120  kDifPinmuxPadAttrPullResistorUp | kDifPinmuxPadAttrInputDisable),
121  };
122  dif_pinmux_pad_attr_t attrs_check;
123  EXPECT_READ32(PINMUX_MIO_PAD_ATTR_REGWEN_1_REG_OFFSET, 0);
124  EXPECT_EQ(dif_pinmux_pad_write_attrs(&dif_pinmux_, /*pad=*/1,
125  /*type=*/kDifPinmuxPadKindMio, attrs,
126  &attrs_check),
127  kDifLocked);
128 
129  EXPECT_READ32(PINMUX_DIO_PAD_ATTR_REGWEN_2_REG_OFFSET, 0);
130  EXPECT_EQ(dif_pinmux_pad_write_attrs(&dif_pinmux_, /*pad=*/2,
131  /*type=*/kDifPinmuxPadKindDio, attrs,
132  &attrs_check),
133  kDifLocked);
134 
135  EXPECT_READ32(PINMUX_MIO_PAD_ATTR_REGWEN_1_REG_OFFSET, 1);
136  EXPECT_READ32(PINMUX_MIO_PAD_ATTR_1_REG_OFFSET, 0);
137  EXPECT_WRITE32(PINMUX_MIO_PAD_ATTR_1_REG_OFFSET,
138  {
139  {PINMUX_MIO_PAD_ATTR_1_INVERT_1_BIT, 1},
140  {PINMUX_MIO_PAD_ATTR_1_PULL_EN_1_BIT, 1},
141  {PINMUX_MIO_PAD_ATTR_1_PULL_SELECT_1_BIT, 1},
142  {PINMUX_MIO_PAD_ATTR_1_INPUT_DISABLE_1_BIT, 1},
143  {PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_OFFSET, 2},
144  {PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_OFFSET, 5},
145  });
146  EXPECT_READ32(PINMUX_MIO_PAD_ATTR_1_REG_OFFSET,
147  {
148  {PINMUX_MIO_PAD_ATTR_1_INVERT_1_BIT, 1},
149  {PINMUX_MIO_PAD_ATTR_1_PULL_EN_1_BIT, 1},
150  {PINMUX_MIO_PAD_ATTR_1_PULL_SELECT_1_BIT, 1},
151  {PINMUX_MIO_PAD_ATTR_1_INPUT_DISABLE_1_BIT, 1},
152  {PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_OFFSET, 2},
153  {PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_OFFSET, 5},
154  });
155  EXPECT_DIF_OK(dif_pinmux_pad_write_attrs(&dif_pinmux_, /*pad=*/1,
156  /*type=*/kDifPinmuxPadKindMio, attrs,
157  &attrs_check));
158  EXPECT_EQ(attrs_check.slew_rate, attrs.slew_rate);
159  EXPECT_EQ(attrs_check.drive_strength, attrs.drive_strength);
160  EXPECT_EQ(attrs_check.flags, attrs.flags);
161 
162  EXPECT_READ32(PINMUX_DIO_PAD_ATTR_REGWEN_3_REG_OFFSET, 1);
163  EXPECT_READ32(PINMUX_DIO_PAD_ATTR_3_REG_OFFSET, 0);
164  EXPECT_WRITE32(PINMUX_DIO_PAD_ATTR_3_REG_OFFSET,
165  {
166  {PINMUX_DIO_PAD_ATTR_3_INVERT_3_BIT, 1},
167  {PINMUX_DIO_PAD_ATTR_3_PULL_EN_3_BIT, 1},
168  {PINMUX_DIO_PAD_ATTR_3_PULL_SELECT_3_BIT, 1},
169  {PINMUX_DIO_PAD_ATTR_3_INPUT_DISABLE_3_BIT, 1},
170  {PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_OFFSET, 2},
171  {PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_OFFSET, 5},
172  });
173  EXPECT_READ32(PINMUX_DIO_PAD_ATTR_3_REG_OFFSET,
174  {
175  {PINMUX_DIO_PAD_ATTR_3_INVERT_3_BIT, 0},
176  {PINMUX_DIO_PAD_ATTR_3_PULL_EN_3_BIT, 1},
177  {PINMUX_DIO_PAD_ATTR_3_PULL_SELECT_3_BIT, 1},
178  {PINMUX_DIO_PAD_ATTR_3_INPUT_DISABLE_3_BIT, 1},
179  {PINMUX_DIO_PAD_ATTR_3_SLEW_RATE_3_OFFSET, 2},
180  {PINMUX_DIO_PAD_ATTR_3_DRIVE_STRENGTH_3_OFFSET, 5},
181  });
182  EXPECT_EQ(dif_pinmux_pad_write_attrs(&dif_pinmux_, /*pad=*/3,
183  /*type=*/kDifPinmuxPadKindDio, attrs,
184  &attrs_check),
185  kDifError);
186  EXPECT_EQ(attrs_check.slew_rate, attrs.slew_rate);
187  EXPECT_EQ(attrs_check.drive_strength, attrs.drive_strength);
188  EXPECT_EQ(attrs_check.flags, kDifPinmuxPadAttrPullResistorEnable |
189  kDifPinmuxPadAttrPullResistorUp |
190  kDifPinmuxPadAttrInputDisable);
191 
192  EXPECT_READ32(PINMUX_MIO_PAD_ATTR_1_REG_OFFSET,
193  {
194  {PINMUX_MIO_PAD_ATTR_1_KEEPER_EN_1_BIT, 1},
195  {PINMUX_MIO_PAD_ATTR_1_OD_EN_1_BIT, 1},
196  {PINMUX_MIO_PAD_ATTR_1_INPUT_DISABLE_1_BIT, 1},
197  {PINMUX_MIO_PAD_ATTR_1_SLEW_RATE_1_OFFSET, 1},
198  {PINMUX_MIO_PAD_ATTR_1_DRIVE_STRENGTH_1_OFFSET, 3},
199  });
200  EXPECT_DIF_OK(dif_pinmux_pad_get_attrs(
201  &dif_pinmux_, /*pad=*/1, /*type=*/kDifPinmuxPadKindMio, &attrs_check));
202  EXPECT_EQ(attrs_check.slew_rate, 1);
203  EXPECT_EQ(attrs_check.drive_strength, 3);
204  EXPECT_EQ(attrs_check.flags, kDifPinmuxPadAttrKeeper |
205  kDifPinmuxPadAttrOpenDrain |
206  kDifPinmuxPadAttrInputDisable);
207 }
208 
209 TEST_F(PinmuxTest, SleepModeConfig) {
210  EXPECT_READ32(PINMUX_MIO_PAD_SLEEP_REGWEN_0_REG_OFFSET, 0);
211  EXPECT_EQ(
212  dif_pinmux_pad_sleep_enable(&dif_pinmux_, /*pad=*/0, kDifPinmuxPadKindMio,
213  kDifPinmuxSleepModeHighZ),
214  kDifLocked);
215 
216  EXPECT_READ32(PINMUX_DIO_PAD_SLEEP_REGWEN_1_REG_OFFSET, 0);
217  EXPECT_EQ(dif_pinmux_pad_sleep_disable(&dif_pinmux_, /*pad=*/1,
218  kDifPinmuxPadKindDio),
219  kDifLocked);
220 
221  EXPECT_READ32(PINMUX_MIO_PAD_SLEEP_REGWEN_1_REG_OFFSET, 1);
222  EXPECT_WRITE32(PINMUX_MIO_PAD_SLEEP_MODE_1_REG_OFFSET,
223  kDifPinmuxSleepModeHighZ);
224  EXPECT_WRITE32(PINMUX_MIO_PAD_SLEEP_EN_1_REG_OFFSET,
225  {{PINMUX_MIO_PAD_SLEEP_EN_1_EN_1_BIT, 1}});
226  EXPECT_DIF_OK(dif_pinmux_pad_sleep_enable(
227  &dif_pinmux_, /*pad=*/1, kDifPinmuxPadKindMio, kDifPinmuxSleepModeHighZ));
228 
229  EXPECT_READ32(PINMUX_DIO_PAD_SLEEP_REGWEN_2_REG_OFFSET, 1);
230  EXPECT_WRITE32(PINMUX_DIO_PAD_SLEEP_EN_2_REG_OFFSET,
231  {{PINMUX_DIO_PAD_SLEEP_EN_2_EN_2_BIT, 0}});
232  EXPECT_DIF_OK(dif_pinmux_pad_sleep_disable(&dif_pinmux_, /*pad=*/2,
233  kDifPinmuxPadKindDio));
234 }
235 
236 TEST_F(PinmuxTest, SleepStatus) {
237  bool in_sleep_mode;
238  EXPECT_READ32(PINMUX_MIO_PAD_SLEEP_STATUS_0_REG_OFFSET, 0xfffffff7u);
239  EXPECT_DIF_OK(dif_pinmux_pad_sleep_get_state(
240  &dif_pinmux_, /*pad=*/3, kDifPinmuxPadKindMio, &in_sleep_mode));
241  EXPECT_FALSE(in_sleep_mode);
242 
243  EXPECT_READ32(PINMUX_DIO_PAD_SLEEP_STATUS_REG_OFFSET, 0x00000004u);
244  EXPECT_DIF_OK(dif_pinmux_pad_sleep_get_state(
245  &dif_pinmux_, /*pad=*/2, kDifPinmuxPadKindDio, &in_sleep_mode));
246  EXPECT_TRUE(in_sleep_mode);
247 
248  EXPECT_READ32(PINMUX_MIO_PAD_SLEEP_STATUS_0_REG_OFFSET, 0xffff7777u);
249  EXPECT_WRITE32(PINMUX_MIO_PAD_SLEEP_STATUS_0_REG_OFFSET, 0xffff7757u);
250  EXPECT_DIF_OK(dif_pinmux_pad_sleep_clear_state(&dif_pinmux_, /*pad=*/5,
251  kDifPinmuxPadKindMio));
252 }
253 
254 TEST_F(PinmuxTest, WakeupConfig) {
255  dif_pinmux_wakeup_config_t config = {
256  .signal_filter = kDifToggleDisabled,
257  .pad_type = kDifPinmuxPadKindMio,
258  .pad_select = 4,
259  .mode = kDifPinmuxWakeupModeTimedHigh,
260  .counter_threshold = 23,
261  };
262  EXPECT_READ32(PINMUX_WKUP_DETECTOR_REGWEN_1_REG_OFFSET, 0);
263  EXPECT_EQ(dif_pinmux_wakeup_detector_disable(&dif_pinmux_, /*detector=*/1),
264  kDifLocked);
265 
266  EXPECT_READ32(PINMUX_WKUP_DETECTOR_REGWEN_0_REG_OFFSET, 0);
267  EXPECT_EQ(
268  dif_pinmux_wakeup_detector_enable(&dif_pinmux_, /*detector=*/0, config),
269  kDifLocked);
270 
271  EXPECT_READ32(PINMUX_WKUP_DETECTOR_REGWEN_2_REG_OFFSET, 1);
272  EXPECT_WRITE32(PINMUX_WKUP_DETECTOR_EN_2_REG_OFFSET, 0);
273  EXPECT_DIF_OK(
274  dif_pinmux_wakeup_detector_disable(&dif_pinmux_, /*detector=*/2));
275 
276  EXPECT_READ32(PINMUX_WKUP_DETECTOR_REGWEN_3_REG_OFFSET, 1);
277  EXPECT_WRITE32(PINMUX_WKUP_DETECTOR_EN_3_REG_OFFSET, 0);
278  EXPECT_WRITE32(PINMUX_WKUP_DETECTOR_3_REG_OFFSET,
279  {
280  {PINMUX_WKUP_DETECTOR_3_MODE_3_OFFSET,
281  PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_TIMEDHIGH},
282  {PINMUX_WKUP_DETECTOR_3_FILTER_3_BIT, 0},
283  {PINMUX_WKUP_DETECTOR_3_MIODIO_3_BIT, 0},
284  });
285  EXPECT_WRITE32(PINMUX_WKUP_DETECTOR_CNT_TH_3_REG_OFFSET, 23);
286  EXPECT_WRITE32(PINMUX_WKUP_DETECTOR_PADSEL_3_REG_OFFSET, 4);
287  EXPECT_WRITE32(PINMUX_WKUP_DETECTOR_EN_3_REG_OFFSET, 1);
288  EXPECT_DIF_OK(
289  dif_pinmux_wakeup_detector_enable(&dif_pinmux_, /*detector=*/3, config));
290 
291  config.signal_filter = kDifToggleEnabled;
292  config.pad_select = 3;
293  config.pad_type = kDifPinmuxPadKindDio;
294  config.mode = kDifPinmuxWakeupModeAnyEdge;
295  EXPECT_READ32(PINMUX_WKUP_DETECTOR_REGWEN_3_REG_OFFSET, 1);
296  EXPECT_WRITE32(PINMUX_WKUP_DETECTOR_EN_3_REG_OFFSET, 0);
297  EXPECT_WRITE32(PINMUX_WKUP_DETECTOR_3_REG_OFFSET,
298  {
299  {PINMUX_WKUP_DETECTOR_3_MODE_3_OFFSET,
300  PINMUX_WKUP_DETECTOR_0_MODE_0_VALUE_EDGE},
301  {PINMUX_WKUP_DETECTOR_3_FILTER_3_BIT, 1},
302  {PINMUX_WKUP_DETECTOR_3_MIODIO_3_BIT, 1},
303  });
304  EXPECT_WRITE32(PINMUX_WKUP_DETECTOR_PADSEL_3_REG_OFFSET, 3);
305  EXPECT_WRITE32(PINMUX_WKUP_DETECTOR_EN_3_REG_OFFSET, 1);
306  EXPECT_DIF_OK(
307  dif_pinmux_wakeup_detector_enable(&dif_pinmux_, /*detector=*/3, config));
308 }
309 
310 TEST_F(PinmuxTest, WakeupCause) {
311  uint32_t detector_map;
312  EXPECT_READ32(PINMUX_WKUP_CAUSE_REG_OFFSET, 0x4);
313  EXPECT_DIF_OK(dif_pinmux_wakeup_cause_get(&dif_pinmux_, &detector_map));
314  EXPECT_EQ(detector_map, 4);
315 
316  EXPECT_WRITE32(PINMUX_WKUP_CAUSE_REG_OFFSET, 0x0);
317  EXPECT_DIF_OK(dif_pinmux_wakeup_cause_clear(&dif_pinmux_));
318 }
319 
320 } // namespace
321 } // namespace dif_pinmux_unittest
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