Software APIs
dif_pattgen_unittest.cc
1 // Copyright lowRISC contributors (OpenTitan project).
2 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3 // SPDX-License-Identifier: Apache-2.0
4 
5 #include "sw/device/lib/dif/dif_pattgen.h"
6 
7 #include "gtest/gtest.h"
8 #include "sw/device/lib/base/mock_mmio.h"
9 #include "sw/device/lib/dif/dif_base.h"
10 #include "sw/device/lib/dif/dif_test_base.h"
11 
12 #include "pattgen_regs.h" // Generated.
13 
14 namespace dif_pattgen_unittest {
15 namespace {
16 using ::mock_mmio::LeInt;
17 using ::mock_mmio::MmioTest;
18 using ::mock_mmio::MockDevice;
19 
20 class PattgenTest : public testing::Test, public MmioTest {
21  protected:
22  dif_pattgen_t pattgen_ = {.base_addr = dev().region()};
23  dif_pattgen_channel_config_t config_ = {
24  .polarity = kDifPattgenPolarityHigh,
25  .clock_divisor = 31,
26  .seed_pattern_lower_word = 0xDEADBEEF,
27  .seed_pattern_upper_word = 0xCAFEFEED,
28  .seed_pattern_length = 64,
29  .num_pattern_repetitions = 64,
30  };
31 };
32 
33 class ConfigChannelTest : public PattgenTest {};
34 
35 TEST_F(ConfigChannelTest, NullHandle) {
36  EXPECT_DIF_BADARG(
37  dif_pattgen_configure_channel(nullptr, kDifPattgenChannel0, config_));
38 }
39 
40 TEST_F(ConfigChannelTest, BadChannel) {
41  EXPECT_DIF_BADARG(dif_pattgen_configure_channel(
42  &pattgen_, static_cast<dif_pattgen_channel_t>(2), config_));
43 }
44 
45 TEST_F(ConfigChannelTest, BadPolarity) {
46  config_.polarity = static_cast<dif_pattgen_polarity_t>(2);
47  EXPECT_DIF_BADARG(
48  dif_pattgen_configure_channel(&pattgen_, kDifPattgenChannel0, config_));
49 }
50 
51 TEST_F(ConfigChannelTest, BadSeedPatternLength) {
52  config_.seed_pattern_length = 0;
53  EXPECT_DIF_BADARG(
54  dif_pattgen_configure_channel(&pattgen_, kDifPattgenChannel0, config_));
55 
56  config_.seed_pattern_length = 65;
57  EXPECT_DIF_BADARG(
58  dif_pattgen_configure_channel(&pattgen_, kDifPattgenChannel0, config_));
59 }
60 
61 TEST_F(ConfigChannelTest, BadNumPatternRepetitions) {
62  config_.num_pattern_repetitions = 0;
63  EXPECT_DIF_BADARG(
64  dif_pattgen_configure_channel(&pattgen_, kDifPattgenChannel0, config_));
65 
66  config_.num_pattern_repetitions = 1025;
67  EXPECT_DIF_BADARG(
68  dif_pattgen_configure_channel(&pattgen_, kDifPattgenChannel0, config_));
69 }
70 
71 TEST_F(ConfigChannelTest, ConfigAttemptWhileEnabled) {
72  EXPECT_READ32(PATTGEN_CTRL_REG_OFFSET, {{PATTGEN_CTRL_ENABLE_CH0_BIT, 1}});
73  EXPECT_EQ(
74  dif_pattgen_configure_channel(&pattgen_, kDifPattgenChannel0, config_),
75  kDifError);
76 
77  EXPECT_READ32(PATTGEN_CTRL_REG_OFFSET, {{PATTGEN_CTRL_ENABLE_CH1_BIT, 1}});
78  EXPECT_EQ(
79  dif_pattgen_configure_channel(&pattgen_, kDifPattgenChannel1, config_),
80  kDifError);
81 }
82 
83 TEST_F(ConfigChannelTest, FullSeedSuccess) {
84  EXPECT_READ32(PATTGEN_CTRL_REG_OFFSET, {{PATTGEN_CTRL_ENABLE_CH0_BIT, 0},
85  {PATTGEN_CTRL_ENABLE_CH1_BIT, 1}});
86  EXPECT_WRITE32(PATTGEN_CTRL_REG_OFFSET, {{PATTGEN_CTRL_POLARITY_CH0_BIT, 1},
87  {PATTGEN_CTRL_ENABLE_CH1_BIT, 1}});
88  EXPECT_WRITE32(PATTGEN_PREDIV_CH0_REG_OFFSET, config_.clock_divisor);
89  EXPECT_WRITE32(PATTGEN_DATA_CH0_0_REG_OFFSET,
90  config_.seed_pattern_lower_word);
91  EXPECT_WRITE32(PATTGEN_DATA_CH0_1_REG_OFFSET,
92  config_.seed_pattern_upper_word);
93  EXPECT_READ32(PATTGEN_SIZE_REG_OFFSET, {{PATTGEN_SIZE_REPS_CH1_OFFSET, 127},
94  {PATTGEN_SIZE_LEN_CH1_OFFSET, 31}});
95  EXPECT_WRITE32(PATTGEN_SIZE_REG_OFFSET,
96  {{PATTGEN_SIZE_LEN_CH0_OFFSET,
97  static_cast<uint8_t>(config_.seed_pattern_length - 1)},
98  {PATTGEN_SIZE_REPS_CH0_OFFSET,
99  static_cast<uint16_t>(config_.num_pattern_repetitions - 1)},
100  {PATTGEN_SIZE_LEN_CH1_OFFSET, 31},
101  {PATTGEN_SIZE_REPS_CH1_OFFSET, 127}});
102  EXPECT_DIF_OK(
103  dif_pattgen_configure_channel(&pattgen_, kDifPattgenChannel0, config_));
104 }
105 
106 TEST_F(ConfigChannelTest, HalfSeedSuccess) {
107  config_.seed_pattern_length = 16;
108  EXPECT_READ32(PATTGEN_CTRL_REG_OFFSET, {{PATTGEN_CTRL_ENABLE_CH1_BIT, 0}});
109  EXPECT_WRITE32(PATTGEN_CTRL_REG_OFFSET, {{PATTGEN_CTRL_POLARITY_CH1_BIT, 1}});
110  EXPECT_WRITE32(PATTGEN_PREDIV_CH1_REG_OFFSET, config_.clock_divisor);
111  EXPECT_WRITE32(PATTGEN_DATA_CH1_0_REG_OFFSET,
112  config_.seed_pattern_lower_word);
113  EXPECT_READ32(PATTGEN_SIZE_REG_OFFSET, 0);
114  EXPECT_WRITE32(
115  PATTGEN_SIZE_REG_OFFSET,
116  {{PATTGEN_SIZE_LEN_CH1_OFFSET,
117  static_cast<uint8_t>(config_.seed_pattern_length - 1)},
118  {PATTGEN_SIZE_REPS_CH1_OFFSET,
119  static_cast<uint16_t>(config_.num_pattern_repetitions - 1)}});
120  EXPECT_DIF_OK(
121  dif_pattgen_configure_channel(&pattgen_, kDifPattgenChannel1, config_));
122 }
123 
124 class ChannelSetEnabledTest : public PattgenTest {};
125 
126 TEST_F(ChannelSetEnabledTest, NullHandle) {
127  EXPECT_DIF_BADARG(dif_pattgen_channel_set_enabled(
128  nullptr, kDifPattgenChannel0, kDifToggleEnabled));
129 }
130 
131 TEST_F(ChannelSetEnabledTest, BadChannel) {
132  EXPECT_DIF_BADARG(dif_pattgen_channel_set_enabled(
133  &pattgen_, static_cast<dif_pattgen_channel_t>(2), kDifToggleEnabled));
134 }
135 
136 TEST_F(ChannelSetEnabledTest, BadEnableValue) {
137  EXPECT_DIF_BADARG(dif_pattgen_channel_set_enabled(
138  &pattgen_, kDifPattgenChannel0, static_cast<dif_toggle_t>(2)));
139 }
140 
141 TEST_F(ChannelSetEnabledTest, Success) {
142  EXPECT_READ32(PATTGEN_CTRL_REG_OFFSET, {{PATTGEN_CTRL_ENABLE_CH0_BIT, 0},
143  {PATTGEN_CTRL_ENABLE_CH1_BIT, 1}});
144  EXPECT_WRITE32(PATTGEN_CTRL_REG_OFFSET, {{PATTGEN_CTRL_ENABLE_CH0_BIT, 1},
145  {PATTGEN_CTRL_ENABLE_CH1_BIT, 1}});
146  EXPECT_DIF_OK(dif_pattgen_channel_set_enabled(&pattgen_, kDifPattgenChannel0,
147  kDifToggleEnabled));
148 
149  EXPECT_READ32(PATTGEN_CTRL_REG_OFFSET, {{PATTGEN_CTRL_ENABLE_CH0_BIT, 1},
150  {PATTGEN_CTRL_ENABLE_CH1_BIT, 1}});
151  EXPECT_WRITE32(PATTGEN_CTRL_REG_OFFSET, {{PATTGEN_CTRL_ENABLE_CH0_BIT, 1},
152  {PATTGEN_CTRL_ENABLE_CH1_BIT, 0}});
153  EXPECT_DIF_OK(dif_pattgen_channel_set_enabled(&pattgen_, kDifPattgenChannel1,
154  kDifToggleDisabled));
155 }
156 
157 class ChannelGetEnabledTest : public PattgenTest {};
158 
159 TEST_F(ChannelGetEnabledTest, NullArgs) {
160  dif_toggle_t is_enabled;
161  EXPECT_DIF_BADARG(dif_pattgen_channel_get_enabled(
162  nullptr, kDifPattgenChannel0, &is_enabled));
163  EXPECT_DIF_BADARG(
164  dif_pattgen_channel_get_enabled(&pattgen_, kDifPattgenChannel0, nullptr));
165 }
166 
167 TEST_F(ChannelGetEnabledTest, BadChannel) {
168  dif_toggle_t is_enabled;
169  EXPECT_DIF_BADARG(dif_pattgen_channel_get_enabled(
170  &pattgen_, static_cast<dif_pattgen_channel_t>(2), &is_enabled));
171 }
172 
173 TEST_F(ChannelGetEnabledTest, Success) {
174  dif_toggle_t is_enabled;
175 
176  EXPECT_READ32(PATTGEN_CTRL_REG_OFFSET, {{PATTGEN_CTRL_ENABLE_CH1_BIT, 1}});
177  EXPECT_DIF_OK(dif_pattgen_channel_get_enabled(&pattgen_, kDifPattgenChannel1,
178  &is_enabled));
179  EXPECT_EQ(is_enabled, kDifToggleEnabled);
180 
181  EXPECT_READ32(PATTGEN_CTRL_REG_OFFSET, {{PATTGEN_CTRL_ENABLE_CH0_BIT, 0}});
182  EXPECT_DIF_OK(dif_pattgen_channel_get_enabled(&pattgen_, kDifPattgenChannel0,
183  &is_enabled));
184  EXPECT_EQ(is_enabled, kDifToggleDisabled);
185 }
186 
187 } // namespace
188 } // namespace dif_pattgen_unittest
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